U.S. patent application number 11/019658 was filed with the patent office on 2006-01-05 for thin film transistor and method for fabricating the same.
Invention is credited to Ki-Yong Lee, Byoung-Keon Park, Jin-Wook Seo, Tae-Hoon Yang.
Application Number | 20060003503 11/019658 |
Document ID | / |
Family ID | 34928850 |
Filed Date | 2006-01-05 |
United States Patent
Application |
20060003503 |
Kind Code |
A1 |
Yang; Tae-Hoon ; et
al. |
January 5, 2006 |
Thin film transistor and method for fabricating the same
Abstract
A thin film transistor that has improved characteristics and
uniformity is developed by uniformly controlling low concentration
of crystallization catalyst and controlling crystallization
position so that no seed exists and no grain boundary exists, or
one grain boundary exists in a channel layer of the thin film
transistor. The thin film transistor includes a substrate; a
semiconductor layer pattern which is formed on the substrate, the
semiconductor layer pattern having a channel layer of which no seed
exists and no grain boundary exists; a gate insulating film formed
on the semiconductor layer pattern; and a gate electrode formed on
the gate insulating film. A method for fabricating the thin film
transistor includes forming an amorphous silicon layer on a
substrate; forming a semiconductor layer pattern having a channel
layer in which no seed exists and no grain boundary exists by
crystallizing and patterning the amorphous silicon layer; forming a
gate insulating film on the semiconductor layer pattern; and
forming a gate electrode on the gate insulating film.
Inventors: |
Yang; Tae-Hoon;
(Seongnam-si, KR) ; Lee; Ki-Yong; (Yongin-si,
KR) ; Seo; Jin-Wook; (Suwon-si, KR) ; Park;
Byoung-Keon; (Incheon-si, KR) |
Correspondence
Address: |
CHRISTIE, PARKER & HALE, LLP
PO BOX 7068
PASADENA
CA
91109-7068
US
|
Family ID: |
34928850 |
Appl. No.: |
11/019658 |
Filed: |
December 20, 2004 |
Current U.S.
Class: |
438/151 ;
257/E21.413; 257/E21.415; 257/E29.286; 257/E29.293 |
Current CPC
Class: |
H01L 29/66772 20130101;
H01L 29/78654 20130101; H01L 29/78696 20130101; H01L 29/78675
20130101; H01L 29/66757 20130101 |
Class at
Publication: |
438/151 |
International
Class: |
H01L 21/00 20060101
H01L021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 2004 |
KR |
2004-50915 |
Claims
1. A thin film transistor comprising: a substrate; a semiconductor
layer pattern formed on the substrate, the semiconductor layer
pattern having a channel layer, the channel layer having no seed
and no grain boundary; a gate insulating film formed on the
semiconductor layer pattern; and a gate electrode formed on the
gate insulating film.
2. The thin film transistor according to claim 1, wherein the
semiconductor layer pattern has a source region and a drain region,
wherein a seed is formed in the source region or the drain region,
and wherein a width and a length of the semiconductor layer pattern
are each shorter than a radius of a grain formed by the seed.
3. The thin film transistor according to claim 1, wherein the
semiconductor layer pattern has a source region and a drain region,
wherein a seed is formed on an outer part of the channel layer
between the source region and the drain region, and wherein a width
and a length of the semiconductor layer pattern are each shorter
than a diameter of a grain formed by the seed.
4. The thin film transistor according to claim 1, wherein the
channel layer has a crystallinity of about 0.7 to 0.9.
5. The thin film transistor according to claim 1, wherein the thin
film transistor is used in a liquid crystal display (LCD) device or
an organic electroluminescence device.
6. A thin film transistor comprising: a substrate; a semiconductor
layer pattern formed on the substrate, the semiconductor layer
pattern having a channel layer, the channel layer having a single
grain boundary; a gate insulating film formed on the semiconductor
layer pattern; and a gate electrode formed on the gate insulating
film.
7. The thin film transistor according to claim 6, wherein the
semiconductor layer pattern has a source region and a drain region,
wherein a seed is formed in the source region or the drain region,
and a length of the semiconductor layer pattern is about 1.1 to 1.3
times the radius of a grain formed by the seed.
8. The thin film transistor according to claim 5, wherein the thin
film transistor is used in a liquid crystal display (LCD) device or
an organic electroluminescence device.
9. A method for fabricating a thin film transistor comprising:
forming an amorphous silicon layer on a substrate; forming a
semiconductor layer pattern having a channel layer in which no seed
exists and no grain boundary exists by crystallizing and patterning
the amorphous silicon layer; forming a gate insulating film on the
semiconductor layer pattern; and forming a gate electrode on the
gate insulating film.
10. The method for fabricating the thin film transistor according
to claim 9, wherein the forming the semiconductor layer pattern
comprises: forming a capping layer on the amorphous silicon layer;
forming a grooved part on the capping layer so that a seed is
formed in a source region or a drain region of the semiconductor
layer pattern; forming a metal catalyst layer on the capping layer;
diffusing a metal catalyst of the metal catalyst layer into the
amorphous silicon layer; and forming a polycrystalline silicon
layer by crystallizing the amorphous silicon layer using the
diffused metal catalyst.
11. The method for fabricating the thin film transistor according
to claim 9, wherein the forming the semiconductor layer pattern
comprises: forming a first capping layer on the amorphous silicon
layer; patterning the first capping layer so that a seed is formed
in a source region or a drain region of the semiconductor layer
pattern; forming a second capping layer on the patterned first
capping layer; forming a metal catalyst layer on the second capping
layer; diffusing a metal catalyst of the metal catalyst layer into
the amorphous silicon layer; and forming a polycrystalline silicon
layer by crystallizing the amorphous silicon layer using the
diffused metal catalyst.
12. The method for fabricating the thin film transistor according
to claim 10, wherein the semiconductor layer pattern is formed in
such a manner that a width and a length of the semiconductor layer
pattern are each shorter than a radius of a grain formed by the
seed.
13. The method for fabricating the thin film transistor according
to claim 11, wherein the semiconductor layer pattern is formed in
such a manner that a width and a length of the semiconductor layer
pattern are each shorter than a radius of a grain formed by the
seed.
14. The method for fabricating the thin film transistor according
to claim 9, wherein the forming the semiconductor layer pattern
comprises: forming a capping layer on the amorphous silicon layer;
forming a grooved part on the capping layer so that a seed is
formed on an outer part of a channel layer between a source region
and a drain region of the semiconductor layer pattern; forming a
metal catalyst layer on the capping layer; diffusing a metal
catalyst of the metal catalyst layer into the amorphous silicon
layer; and forming a polycrystalline silicon layer by crystallizing
the amorphous silicon layer using the diffused metal catalyst.
15. The method for fabricating the thin film transistor according
to claim 9, wherein the forming the semiconductor layer pattern
comprises: forming a first capping layer on the amorphous silicon
layer; patterning the first capping layer so that a seed is formed
on an outer part of a channel layer between a source region and a
drain region of the semiconductor layer pattern; forming a second
capping layer on the patterned first capping layer; forming a metal
catalyst layer on the second capping layer; diffusing a metal
catalyst of the metal catalyst layer into the amorphous silicon
layer; and forming a polycrystalline silicon layer by crystallizing
the amorphous silicon layer using the diffused metal catalyst.
16. The method for fabricating the thin film transistor according
to claim 14, wherein the semiconductor layer pattern is formed in
such a manner that a width and a length of the semiconductor layer
pattern are each shorter than a diameter of a grain formed by the
seed.
17. The method for fabricating the thin film transistor according
to claim 15, wherein the semiconductor layer pattern is formed in
such a manner that a width and a length of the semiconductor layer
pattern are each shorter than a diameter of a grain formed by the
seed.
18. The method for fabricating the thin film transistor according
to claim 10, wherein the capping layer is formed of a silicon
nitride film or a silicon oxide film.
19. The method for fabricating the thin film transistor according
to claim 14, wherein the capping layer is formed of a silicon
nitride film or a silicon oxide film.
20. The method for fabricating the thin film transistor according
to claim 11, wherein the first capping layer pattern and the second
capping layer are each formed of a silicon nitride film or a
silicon oxide film.
21. The method for fabricating the thin film transistor according
to claim 15, wherein the first capping layer pattern and the second
capping layer are each formed of a silicon nitride film or a
silicon oxide film.
22. The method for fabricating the thin film transistor according
to claim 11, wherein a thickness of a part of the first capping
layer pattern is thicker than that of the second capping layer.
23. The method for fabricating the thin film transistor according
to claim 15, wherein a thickness of a part of the first capping
layer pattern is thicker than that of the second capping layer.
24. The method for fabricating the thin film transistor according
to claim 11, wherein a density of a part the first capping layer
pattern is higher than that of the second capping layer.
25. The method for fabricating the thin film transistor according
to claim 15, wherein a density of a part of the first capping layer
pattern is higher than that of the second capping layer.
26. A method for fabricating a thin film transistor comprising:
forming an amorphous silicon layer on a substrate; forming a
semiconductor layer pattern having a channel layer in which one
grain boundary exists by crystallizing and patterning the amorphous
silicon layer; forming a gate insulating film on the semiconductor
layer pattern; and forming a gate electrode on the gate insulating
film.
27. The method for fabricating the thin film transistor according
to claim 26, wherein the forming the semiconductor layer pattern
comprises: forming a capping layer on the amorphous silicon layer;
forming a grooved part on the capping layer so that a seed is
formed in a source region or a drain region of the semiconductor
layer pattern; forming a metal catalyst layer on the capping layer;
diffusing a metal catalyst of the metal catalyst layer into the
amorphous silicon layer; and forming a polycrystalline silicon
layer by crystallizing the amorphous silicon layer using the
diffused metal catalyst.
28. The method for fabricating the thin film transistor according
to claim 26, wherein the forming the semiconductor layer pattern
comprises: forming a first capping layer on the amorphous silicon
layer; patterning the first capping layer so that a seed is formed
in a source region or a drain region of the semiconductor layer
pattern; forming a second capping layer on the patterned first
capping layer; forming a metal catalyst layer on the second capping
layer; diffusing a metal catalyst of the metal catalyst layer into
the amorphous silicon layer; and forming a polycrystalline silicon
layer by crystallizing the amorphous silicon layer using the
diffused metal catalyst.
29. The method for fabricating the thin film transistor according
to claim 27, wherein the semiconductor layer pattern is formed in
such a way that a length of the semiconductor layer pattern is
about 1.1 to 1.3 times a radius of a grain formed by the seed.
30. The method for fabricating the thin film transistor according
to claim 28, wherein the semiconductor layer pattern is formed in
such a way that a length of the semiconductor layer pattern is
about 1.1 to 1.3 times a radius of a grain formed by the seed.
31. The method for fabricating the thin film transistor according
to claim 27, wherein the capping layer is formed of a silicon
nitride film or a silicon oxide film.
32. The method for fabricating the thin film transistor according
to claim 28, wherein the first capping layer pattern and the second
capping layer are each formed of a silicon nitride film or a
silicon oxide film.
33. The method for fabricating the thin film transistor according
to claim 28, wherein a thickness of a part of the first capping
layer pattern is thicker than that of the second capping layer.
34. The method for fabricating the thin film transistor according
to claim 28, wherein a density of a part of the first capping layer
pattern is higher than that of the second capping layer.
Description
CROSS REFERENCE
[0001] This application claims priority to and the benefit of
Korean Patent Application No. 10-2004-0050915, filed on Jun. 30,
2004, the content of which is incorporated herein by reference in
its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a thin film transistor and
a method for fabricating the same, more particularly, to a thin
film transistor having a channel layer of which no seed exists and
no grain boundary exists, or one grain boundary exists, and a
method for fabricating the thin film transistor.
[0004] 2. Description of Related Art
[0005] Generally, a polycrystalline silicon layer is used for
various purposes as a semiconductor layer for a thin film
transistor. For example, since the polycrystalline silicon layer
has a high electric field effect and mobility, it can be applied to
circuits operated at high speed, and it enables Complementary Metal
Oxide Semiconductor (CMOS) circuit to be constructed. A thin film
transistor using the polycrystalline silicon layer can also be used
in an active element of an active matrix liquid crystal display
(AMLCD) and a switching element and a driving element of an organic
light emitting diode (OLED).
[0006] The polycrystalline silicon layer used in the thin film
transistor is fabricated by direct deposition, high temperature
thermal annealing or laser annealing. In case of the laser
annealing, while it can be performed at low temperature, and can
result in high electric field effect and mobility, many alternative
technologies are being studied because of the requirement for
expensive laser equipment.
[0007] At present, a method for crystallizing amorphous silicon
using metal is mostly being studied since the method has merits
that the amorphous silicon is promptly crystallized at a lower
temperature compared with solid phase crystallization. The
crystallization method using metal can be categorized into a metal
induced crystallization method and a metal induced lateral
crystallization method. Regardless of its category, however, the
crystallization method using metal has the problem that
characteristics of elements for thin film transistors are
deteriorated by metal contamination.
[0008] As such, a technology of forming a good polycrystalline
silicon layer by controlling concentration of ions of metal through
an ion injector has been developed. The technology performs high
temperature annealing, rapid thermal annealing or laser irradiation
and a method for crystallizing the thin film by thermal annealing
after depositing a thin film by spin coating a mixture of organic
film having viscous property and liquid phase metal on the
polycrystalline silicon layer to flatten the surface of
polycrystalline silicon layer as metal induced crystallization are
developed to reduce quantity of metal and form a polycrystalline
silicon layer of good quality. However, even in this case, there
are problems in aspects of scale-up of grain size and uniformity of
grain in the polycrystalline silicon layer.
[0009] In order to solve the foregoing problems, a method for
manufacturing polycrystalline silicon layer as a crystallization
method using a capping (or cover) layer has been developed as
disclosed in Korean Patent Laid-open Publication No.
10-2003-0060403. The disclosed method uses an amorphous silicon
layer that is formed on a substrate, and a capping layer is formed
on the amorphous silicon layer. Subsequently, a seed is formed by
depositing a metal catalyst layer on the capping layer and
diffusing metal catalyst into the amorphous silicon layer through
the capping layer by thermal annealing or laser annealing. A
polycrystalline silicon layer is obtained using the formed seed.
This method has merits in reducing metal contamination because the
metal catalyst is diffused through the capping (or cover)
layer.
[0010] However, the foregoing method has problems in that it is
difficult to uniformly control low concentration of crystallization
catalyst and control crystallization position and grain size.
Particularly, the foregoing method has problems in that it is
difficult to control the number of boundaries between the seeds and
the grains since characteristics and uniformity of elements for
thin film transistors are greatly influenced by the number of
boundaries between seeds and grains formed in a channel of the thin
film transistor.
SUMMARY OF THE INVENTION
[0011] It is an aspect of the present invention to provide a thin
film transistor for uniformly controlling a concentration of a
crystallization catalyst and a crystallization position so that no
seed exists and no grain boundary exists in a channel layer of the
thin film transistor or for controlling the number of seeds or
grain boundaries so that characteristics and uniformity of the thin
film transistor are improved, and a method for fabricating the thin
film transistor.
[0012] One exemplary embodiment of the present invention provides a
thin film transistor. The thin film transistor includes a
substrate; a semiconductor layer pattern formed on the substrate,
the semiconductor layer pattern having a channel layer, the channel
layer having no seed and no grain boundary; a gate insulating film
formed on the semiconductor layer pattern; and a gate electrode
formed on the gate insulating film.
[0013] A seed may be formed in a source region or a drain region of
the semiconductor layer pattern, and a width and a length of the
semiconductor layer pattern may each be shorter than a radius of a
grain formed by the seed.
[0014] A seed may be formed on an outer part of the channel layer
between a source region and a drain region of the semiconductor
layer pattern, and a width and a length of the semiconductor layer
pattern may each be shorter than a diameter of a grain formed by
the seed.
[0015] The channel layer may have a crystallinity or a
crystallization ratio of about 0.7 to 0.9.
[0016] One exemplary embodiment of the present invention provides a
thin film transistor. The thin film transistor includes a
substrate; a semiconductor layer pattern formed on the substrate,
the semiconductor layer pattern has a channel layer, the channel
layer having a single grain boundary; a gate insulating film formed
on the semiconductor layer pattern; and a gate electrode formed on
the gate insulating film.
[0017] A seed may be formed in a source region or a drain region of
the semiconductor layer pattern, and a length of the semiconductor
layer pattern may be about 1.1 to 1.3 times a radius of a grain
formed by the seed.
[0018] The thin film transistor may further include a buffer layer
formed between the substrate and the semiconductor layer pattern.
The buffer layer may be formed of a silicon nitride film or a
silicon oxide film.
[0019] The thin film transistor may be used in a liquid crystal
layer (LCD) device or an organic electroluminescence device.
[0020] One exemplary embodiment of the present invention provides a
method for fabricating a thin film transistor. The method includes
forming an amorphous silicon layer on a substrate; forming a
semiconductor layer pattern having a channel layer in which no seed
exists and no grain boundary exists by crystallizing and patterning
the amorphous silicon layer; forming a gate insulating film on the
semiconductor layer pattern; and forming a gate electrode on the
gate insulating film.
[0021] The forming the semiconductor layer pattern may include
forming a capping layer on the amorphous silicon layer; forming a
grooved part on the capping layer so that a seed is formed in a
source region or a drain region of the semiconductor layer pattern;
forming a metal catalyst layer on the capping layer; diffusing a
metal catalyst of the metal catalyst layer into the amorphous
silicon layer; and forming a polycrystalline silicon layer by
crystallizing the amorphous silicon layer using the diffused metal
catalyst.
[0022] The forming the semiconductor layer pattern may include
forming a first capping layer on the amorphous silicon layer;
patterning the first capping layer so that a seed is formed in a
source region or a drain region of the semiconductor layer pattern;
forming a second capping layer on the patterned first capping
layer; forming a metal catalyst layer on the second capping layer;
diffusing a metal catalyst of the metal catalyst layer into the
amorphous silicon layer; and forming a polycrystalline silicon
layer by crystallizing the amorphous silicon layer using the
diffused metal catalyst.
[0023] The semiconductor layer pattern may be formed in such a
manner that a width and a length of the semiconductor layer pattern
are each shorter than a radius of a grain formed by the seed.
[0024] The forming the semiconductor layer pattern may include
forming a capping layer on the amorphous silicon layer; forming a
grooved part on the capping layer so that a seed is formed on an
outer part of a channel layer between a source region and a drain
region of the semiconductor layer pattern; forming a metal catalyst
layer on the capping layer; diffusing a metal catalyst of the metal
catalyst layer into the amorphous silicon layer; and forming a
polycrystalline silicon layer by crystallizing the amorphous
silicon layer using the diffused metal catalyst.
[0025] The forming the semiconductor layer pattern may include
forming a first capping layer on the amorphous silicon layer;
patterning the first capping layer so that a seed is formed on an
outer part of a channel layer between a source region and a drain
region of the semiconductor layer pattern; forming a second capping
layer on the patterned first capping layer; forming a metal
catalyst layer on the second capping layer; diffusing a metal
catalyst of the metal catalyst layer into the amorphous silicon
layer; and forming a polycrystalline silicon layer by crystallizing
the amorphous silicon layer using the diffused metal catalyst.
[0026] The semiconductor layer pattern may be formed in such a
manner that a width and a length of the semiconductor layer pattern
are each shorter than a diameter of a grain formed by the seed.
[0027] One exemplary embodiment of the present invention provides a
method for fabricating a thin film transistor. The method includes
forming an amorphous silicon layer on a substrate; forming a
semiconductor layer pattern having a channel layer in which one
grain boundary exists by crystallizing and patterning the amorphous
silicon layer; forming a gate insulating film on the semiconductor
layer pattern; and forming a gate electrode on the gate insulating
film.
[0028] The semiconductor layer pattern may be formed in such a way
that a length of the semiconductor layer pattern is about 1.1 to
1.3 times a radius of a grain.
[0029] The capping layer may be formed of a silicon nitride film or
a silicon oxide film.
[0030] The first capping layer pattern and the second capping layer
may each be formed of a silicon nitride film or a silicon oxide
film.
[0031] A thickness of a part of the first capping layer pattern may
be thicker than that of the second capping layer.
[0032] A density of a part of the first capping layer pattern may
be higher than that of the second capping layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The accompanying drawings, together with the specification,
illustrate exemplary embodiments of the present invention, and,
together with the description, serve to explain the principles of
the present invention:
[0034] FIG. 1 is a cross sectional structure chart of a thin film
transistor according to one embodiment of the present
invention;
[0035] FIG. 2 is a plan view of a semiconductor layer pattern
according to a first exemplary embodiment of the present
invention;
[0036] FIG. 3 is a plan view of a semiconductor layer pattern
according to a second exemplary embodiment of the present
invention;
[0037] FIG. 4 is a plan view of a semiconductor layer pattern
according to a third exemplary embodiment of the present
invention;
[0038] FIG. 5 is a scanning electron microscope (SEM) photograph of
a growth completed grain;
[0039] FIG. 6A, FIG. 6B, and FIG. 6C are Raman graphs for showing
difference of crystallinity according to a position inside a
grain;
[0040] FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D are cross sectional
structure charts for explaining a first exemplary method for
fabricating a thin film transistor according to the present
invention;
[0041] FIG. 8 is a cross sectional structure chart for explaining a
second exemplary method for fabricating a thin film transistor
according to the present invention; and
[0042] FIG. 9 is a cross sectional structure chart for explaining a
third exemplary method for fabricating thin film transistor
according to the present invention.
[0043] Explanation of marks for certain parts of drawings:
TABLE-US-00001 10, 70, 80, 90: substrate 11, 76: semiconductor
layer pattern 12, 22, 32, 42, 77a: source region 13, 23, 33, 43,
77b: drain region 14, 24, 34, 44, 77c: channel layer 21, 31, 41,
75, 85, 95: seed W: width of the semiconductor layer pattern L:
length of the semiconductor layer pattern R: diameter of grain r:
radius of grain 71, 81, 91: amorphous silicon layer 72: first
capping layer pattern 73: second capping layer 74, 84, 94: metal
catalyst 82: first capping layer 83: second capping layer pattern
92: capping layer
DETAILED DESCRIPTION
[0044] In the following detailed description, only certain
exemplary embodiments of the present invention are shown and
described, simply by way of illustration. As those skilled in the
art would realize, the described embodiments may be modified in
various different ways, all without departing from the spirit or
scope of the present invention. Accordingly, the drawings and
description are to be regarded as illustrative in nature, and not
restrictive. There may be parts shown in the drawings, or parts not
shown in the drawings, that are not discussed in the specification
as they are not essential to a complete understanding of the
invention. Like reference numbers designate like elements.
[0045] FIG. 1 is a cross sectional structure chart of thin film
transistor according to one exemplary embodiment of the present
invention.
[0046] Referring to FIG. 1, a semiconductor layer pattern 11 is
formed on a substrate 10. An insulating substrate can be used as
the substrate 10. The semiconductor layer pattern 11 is formed of
source/drain regions 12, 13 and a channel layer 14. No seed exists
and no grain boundary exists in the channel layer 14, or only one
grain boundary exists in the channel layer 14. Since existence of
seeds in the channel layer 14 causes deterioration and
non-uniformity of characteristics of thin film transistors, the
channel layer 14 is controlled in such a way that no seed exists
and no grain boundary exists or only one grain boundary exists in
the channel layer 14 through a pattern of a first capping layer
used during crystallization of the embodiment of FIG. 1.
[0047] As shown in FIG. 1, a gate insulating film 15 is formed on
the semiconductor layer pattern 11, and a gate electrode 16 is
formed on the gate insulating film 15. An interlayer insulating
film 17 including contact holes is formed on an upper part of the
gate insulating film 15 and the gate electrode 16, and source/drain
electrodes 18, 19 contacted with source/drain regions 12, 13
through the contact holes are formed on the interlayer insulating
film 17.
[0048] FIG. 2 is a plan view of semiconductor layer pattern
according to a first exemplary embodiment of the present
invention.
[0049] Referring to FIG. 2, a semiconductor layer pattern is formed
on a growth completed grain, seeds 21 are formed in a source region
22, and no seed exists and no grain boundary exists in a channel
layer 24. Width W and length L of the semiconductor layer pattern
are each shorter than radius r of the grain. Width W of the
semiconductor layer pattern is the width of the source/drain
regions 22, 23, and length L of the semiconductor layer pattern is
the total length of the source/drain regions 21, 23 and the channel
layer 24 as illustrated in FIG. 2.
[0050] Alternatively, the seeds 21 can be formed in the drain
region 23.
[0051] FIG. 3 is a plan view of a semiconductor layer pattern
according to a second exemplary embodiment of the present
invention.
[0052] Referring to FIG. 3, a seed 31 is formed on an outer part of
a channel layer 34 between a source region 32 and a drain region
33, and no seed exists and no grain boundary exists in the channel
layer 34, where width W and length L of the semiconductor layer
pattern are each shorter than diameter R of the grain.
[0053] FIG. 4 is a plan view of a semiconductor layer pattern
according to a third exemplary embodiment of the present
invention.
[0054] Referring to FIG. 4, a seed 41 is formed in a source region
42, no seed exists in a channel layer 44, but one grain boundary
exists in the channel layer, where width W and length L of the
semiconductor layer pattern are each about 1.1 to 1.3 times of
radius r of the grain.
[0055] Alternatively, the seed 41 can be formed in a drain region
43.
[0056] FIG. 5 is a scanning electron microscope (SEM) photograph of
a growth completed grain. The completed grain has a grain central
part 51, a grain boundary 52, and a part 52 between the grain
central part 51 and the grain boundary 53.
[0057] FIG. 6A, FIG. 6B, and FIG. 6C are Raman graphs for showing
the difference of crystallinity according to the position inside
the grain illustrated in FIG. 5, where an X-axis shows applied wave
number cm.sup.-1 and a Y axis shows beam intensity of the measured
component. The crystallinity is represented as a relative ratio
value of the beam intensity of crystal component to the beam
intensity of amorphous component. In the Raman graphs, a sluggish
part indicates an amorphous component, and a peak part indicates a
crystal component.
[0058] FIG. 6A shows crystallinity of a grain central part. The
measured crystallinity of the grain central part is about 0.45.
That is, the number of amorphous components is greater than that of
crystal components, and the crystallinity is very low.
[0059] FIG. 6C shows crystallinity on a grain boundary. The
measured crystallinity on the grain boundary is 0.52. That is, the
crystallinity on the grain boundary is also very low although it is
somewhat higher than crystallinity at the grain central part.
[0060] FIG. 6B shows crystallinity on a part between the grain
central part and the grain boundary. The measured crystallinity on
the part between the grain central part and the grain boundary is
0.74. That is, the crystallinity on the part between the grain
central part and the grain boundary is substantially higher than
that at the grain central part and that at the grain boundary.
[0061] As described above, characteristics of thin film transistors
can be displayed evenly or unevenly according to a formation
position of the channel layer since crystallization ratio varies
according to a position of the channel layer inside the grain even
in one grain. In one embodiment of the present invention, a part
having crystallinity of about 0.7 to 0.9 or about 0.74 is used as
the channel layer. By controlling the channel layer in such a
manner, no seed has to exist and no grain boundary has to exist in
the channel layer, or one grain boundary exists in the channel
layer.
[0062] FIG. 7A, FIG. 7B, FIG. 7C, and FIG. 7D are cross sectional
structure charts for explaining a first exemplary method for
fabricating thin film transistors according to the present
invention. FIG. 8 is a cross sectional structure chart for
explaining a second exemplary method for fabricating thin film
transistors according to the present invention, and FIG. 9 is a
cross sectional structure chart for explaining a third exemplary
method for fabricating thin film transistors according to the
present invention.
[0063] Referring to FIG. 7A, an amorphous silicon layer 71 is
deposited on a substrate 70. The amorphous silicon layer 71 can be
formed by chemical vapor deposition (CVD) using plasma.
[0064] First capping layer is then formed on the amorphous silicon
layer 71. The first capping layer can be formed of a silicon
nitride film or a silicon oxide film by plasma enhanced chemical
vapor deposition (PECVD). Subsequently, first capping layer pattern
72 having a hollow part 700 is formed by patterning the first
capping layer. A seed to be mentioned later is formed in a source
region or a drain region, and the first capping layer is patterned
on a channel layer so that no seed exists and no grain boundary
exists in the channel layer. Alternatively, the seed can be formed
on an outer part of the channel layer between the source region and
the drain region, and the first capping layer can be patterned on
the channel layer so that no seed exists and no grain boundary
exists in the channel layer. In addition, the seed can be formed in
the source region or the drain region, and the first capping layer
can be patterned on the channel layer so that one grain boundary
exists in the channel layer although no seed exists in the channel
layer.
[0065] The solid part of the first capping layer pattern 72 (i.e.,
not including the hollow part 700) can be formed by the silicon
nitride film or the silicon oxide film having a certain control
thickness or the capping layer pattern 72 have a certain control
density of the silicon nitride film or the silicon oxide film so
that it substantially prevents diffusion of a metal catalyst in the
solid part of the first capping layer pattern 72. That is, the
solid part of the first capping layer pattern 72 functions as a
metal catalyst diffusion impossible or blocking layer.
[0066] Referring to FIG. 7B, a second capping layer 73 is formed on
the first capping layer pattern 72. The second capping layer 73 can
be formed of a silicon nitride film or a silicon oxide film and be
controlled in such a manner that thickness of the second capping
layer 73 is thinner than that of the first capping layer pattern
72, or the density of the second capping layer 73 is lower than
that of the first capping layer pattern 72 to enable the metal
catalyst to be diffused. That is, the second capping layer 73
functions as a metal catalyst diffusion possible layer. Generally,
since an oxide film or a nitride film functions as a barrier in
diffusion of impurities, the oxide film or the nitride film is
capable of preventing the metal catalyst from diffusing through it
by increasing the density and/or the thickness of the silicon oxide
film or the silicon nitride film. On the other hand, the metal
catalyst can be easily diffused through either of these two films
if the density and/or the thickness of the silicon oxide film or
the silicon nitride film is lowered.
[0067] Subsequently, a layer of metal catalyst 74 is formed on the
second capping layer 73. The metal catalyst 74 can be nickel, and
the layer of metal catalyst 74 can be formed using a sputter.
Alternatively, the metal catalyst 74 can be formed by an ion
implantation process or a plasma process. In the plasma process,
the metal catalyst 74 can be formed by arranging a metallic
material on the second capping layer 73 and exposing the metallic
material to plasma.
[0068] Referring to FIG. 7C, the metal catalyst 74 is diffused. The
metal catalyst can be diffused by heat treating the metal catalyst
at a temperature of 200 to 700.degree. C. for one hour. The metal
catalyst 74 is heat treated so that it is diffused into the
amorphous silicon layer 71 after passing through the second capping
layer 73. The diffused metal catalyst 74 forms a seed 75 in the
amorphous silicon layer 71. The seed 75 is a metal silicide formed
when the metal catalyst is contacted with the silicon. The seed 75
can be formed in a source region or drain region and on an outer
part of the channel layer between the source and drain regions as
described above. Crystallization to be mentioned later is performed
starting from the seed 75. Generally, only about 1/100 of the metal
catalyst 74 is diffused to form the seed 75. The metal catalyst 75
that is not diffused by the hollow part 700 of the first capping
layer pattern 72 remains in the second capping layer 73.
[0069] Next, a polycrystalline silicon layer is formed by
crystallizing the amorphous silicon layer 71. The crystallization
can be performed through heat treatment, and the heat treatment can
be carried out by heating the amorphous silicon layer 71 in a
furnace for a long time, where a crystallization temperature of
about 400 to 1,000.degree. C. or of about 550 to 700.degree. C. can
be used. If the amorphous silicon layer 71 is heat treated in the
above described temperature range, the amorphous silicon layer 71
grows to the side from the seed 75 and contacts neighboring grains
to form a grain boundary and completely crystallize the amorphous
silicon layer 71.
[0070] A crystallization method capable of controlling grain size
and grain growing position and direction by forming a seed through
selective diffusion of metal catalysts, thereby crystallizing the
amorphous silicon layer as described in the above process can be
referred to as a super grain silicon (SGS) method, and grains of a
polycrystalline silicon layer formed by this crystallization method
can be grown to a size of 3 to 400 .mu.m.
[0071] Referring now to FIG. 8, first capping layer 82 is formed on
a substrate 80 on which an amorphous silicon layer 81 is formed.
The second capping layer is patterned after forming the second
capping layer on the first capping layer 82. The second capping
layer pattern 83 has a hollow part 800 and can be formed of a
silicon nitride film or a silicon oxide film, and the second
capping layer pattern 83 is controlled in such a way that thickness
of the solid part of the second capping layer pattern 83 is thicker
than that of the first capping layer 82, or density of the solid
part of the second capping layer pattern 83 is higher than that of
the first capping layer 82 so that it is impossible to diffuse a
metal catalyst 84 through the solid part of the second capping
layer pattern 83. That is, the second capping layer pattern 83
functions as a metal catalyst diffusion impossible or blocking
layer.
[0072] A method for fabricating thin film transistors according to
the second exemplary embodiment of the present invention is
substantially the same as the method for fabricating thin film
transistors according to first exemplary embodiment of the present
invention with the exception of the above description.
[0073] Referring to FIG. 9, a capping layer 92 is formed on a
substrate 90 on which an amorphous silicon layer 91 is also formed.
A groove 900 is formed on the capping layer 92, and a layer of
metal catalyst 94 is formed on the capping layer 92. Only one
capping layer 94 is formed in this third exemplary method of FIG. 9
for fabricating thin film transistors according to the present
invention, which is different from the first exemplary method of
FIGS. 7A, 7B, 7C, and 7D for fabricating thin film transistors and
the second exemplary method of FIG. 8 for fabricating thin film
transistor. The capping layer 92 can be formed of a silicon nitride
film or a silicon oxide film, and it is possible to diffuse the
metal catalyst 94 into the groove formed part 900 since thickness
of the groove formed part 900 is thinner than the other part of
capping layer 72.
[0074] Referring to FIG. 7D, the first capping layer pattern 72,
second capping layer 73 and metal catalyst 74 are removed through
etching after crystallizing. The above structures 72, 73, 74 are
removed to prevent or reduce metal contamination on the
crystallized polycrystalline silicon layer.
[0075] Subsequently, source/drain regions 77a, 77b and channel
layer 77c are formed by patterning the polycrystalline silicon
layer and performing the ion implantation process. That is, a
semiconductor layer pattern 76 is formed. The semiconductor layer
pattern 76 can be formed in such a way that a width and a length of
the semiconductor layer pattern 76 are shorter than a radius of a
grain, the width and the length of the semiconductor layer pattern
76 are shorter than the diameter of the grain, and the length of
the semiconductor layer pattern 76 is about 1.1 to 1.3 times the
radius of the grain according to the first capping layer pattern 72
or position of crystallization as described above.
[0076] A metal layer and a photoresist layer are sequentially laid
up on the gate insulating film 78 after forming a gate insulating
film 78 on the semiconductor layer pattern 76. A gate electrode 79
is formed by patterning the photoresist layer and etching the metal
layer using the patterned photoresist layer as a mask. A thin film
transistor is completed using the resulting material.
[0077] In view of the foregoing, certain exemplary embodiments of
the present invention provide a thin film transistor that has good
characteristics and uniformity. The embodiments control uniform low
concentration and crystallization position of the crystallization
catalyst so that no seed exists and no grain boundary exists in a
channel layer of the thin film transistor, or one grain boundary
exists in the channel layer of the thin film transistor.
[0078] While the invention has been described in connection with
certain exemplary embodiments, it is to be understood by those
skilled in the art that the invention is not limited to the
disclosed embodiments, but, on the contrary, is intended to cover
various modifications included within the spirit and scope of the
appended claims and equivalents thereof.
* * * * *