U.S. patent application number 11/184361 was filed with the patent office on 2006-01-05 for if fsk receiver.
This patent application is currently assigned to BROADCOM CORPORATION. Invention is credited to Hooman Darabi, Shahla Khorram, Maryam Rofougaran.
Application Number | 20060002491 11/184361 |
Document ID | / |
Family ID | 26943080 |
Filed Date | 2006-01-05 |
United States Patent
Application |
20060002491 |
Kind Code |
A1 |
Darabi; Hooman ; et
al. |
January 5, 2006 |
IF FSK receiver
Abstract
In one embodiment, the present invention is a low-power, and
high performance receiver including an IF demodulator for high data
rate, frequency modulated systems, such as Bluetooth. The IF
demodulator is implemented in analog domain for simplicity and
lower power consumption and operates at an IF frequency. An IF
demodulator comprises: a first IF differentiator for
differentiating an I signal; a second IF differentiator for
differentiating a Q signal; a cross-coupled multiplier for
multiplying the differentiated I signal with the Q signal and
multiplying the differentiated Q signal with the I signal to
extract frequency information from the I signal and the Q signal;
and a slicer for converting the frequency information to digital
data.
Inventors: |
Darabi; Hooman; (Long Beach,
CA) ; Khorram; Shahla; (Los Angeles, CA) ;
Rofougaran; Maryam; (Marina del Rey, CA) |
Correspondence
Address: |
CHRISTIE, PARKER & HALE, LLP
PO BOX 7068
PASADENA
CA
91109-7068
US
|
Assignee: |
BROADCOM CORPORATION
|
Family ID: |
26943080 |
Appl. No.: |
11/184361 |
Filed: |
July 18, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09960536 |
Sep 21, 2001 |
6968019 |
|
|
11184361 |
Jul 18, 2005 |
|
|
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60253268 |
Nov 27, 2000 |
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Current U.S.
Class: |
375/330 ;
329/304 |
Current CPC
Class: |
H04L 2027/0016 20130101;
H04L 25/062 20130101; H04L 27/1525 20130101; H04L 2027/0024
20130101; H04L 27/142 20130101 |
Class at
Publication: |
375/330 ;
329/304 |
International
Class: |
H04L 27/22 20060101
H04L027/22 |
Claims
1. An IF receiver comprising: an I-mixer for down converting a
received analog input signal to a first lower frequency signal; a
Q-mixer for down converting the input signal to a second lower
frequency signal; a channel selector filter coupled to the I-mixer
and the Q-mixer for generating an I signal and a Q signal; and an
IF demodulator for receiving the I signal and the Q signal without
down conversion to a baseband signal and extracting information
from the input signal responsive to the I signal and Q signal.
2. The IF receiver of claim 1, further comprising an amplifier for
receiving the analog input signal, amplifying the received analog
signal and outputting the amplified input signal to the I-mixer and
the Q-mixer.
3. The IF receiver of claim 1, further comprising a RC calibration
for tuning the receiver.
4. The IF receiver of claim 1, wherein the IF demodulator
comprises: a first IF differentiator for differentiating the I
signal; a second IF differentiator for differentiating the Q
signal; a cross-coupled multiplier for multiplying the
differentiated I signal with the Q signal and multiplying the
differentiated Q signal with the I signal to extract frequency
information from the I signal and the Q signal; and a slicer for
converting the frequency information to digital data.
5. The IF receiver of claim 4, wherein each of the first and second
IF differentiators comprises: an operational amplifier for
receiving an input signal and generating an output signal at an
output node; a first resistor coupled in parallel between the
output node and a negative input; a capacitor coupled between the
native input and the input signal; and a second resistor coupled
between the negative input and Q signal.
6. The IF receiver of claim 5, wherein frequency response for each
of the first and second IF differentiators is defined by: V o V i
.times. ( jw ) = - jRC .times. .times. ( w - 1 R 1 .times. C ) ( 1
) ##EQU4## where V.sub.o is the output signal, V.sub.i is the input
signal, R, R.sub.1, and C are the values for the first resistor,
the second resistor, and the capacitor respectively.
7. The IF receiver of claim 4, wherein the slicer comprises: a peak
detector for receiving an analog data input and a slow/fast signal
for generating a peak signal responsive to peak of the analog data
input signal; a valley detector for receiving an analog data input
and a slow/fast signal for generating a valley signal responsive to
valleys of the analog data input signal; an offset tracker coupled
to the output of the peak detector and the output of the valley
detector for taking the average of the peak signal and the valley
signal; and a comparator coupled to the output of the offset
tracker and the analog data input for generating a high signal if
the analog data input is higher than its average value, and
generating a low signal if the analog data input is lower than its
average value.
8. The IF receiver of claim 7, wherein the peak detector comprises:
a capacitor driven by a current source; a first discharge current
for discharging the capacitor selectable by a first switch; and a
second discharge current for discharging the capacitor selectable
by a second switch, wherein the first switch and the second switch
are adaptively activated to selectively discharge the capacitor
either in a fast discharge mode by the first discharge current or a
slow discharge mode by the second discharge current.
9. The IF receiver of claim 4, wherein the IF demodulator further
comprises a band pass filter for shaping the I signal and the Q
signal.
10. The IF receiver of claim 1, further comprising: a first limiter
for amplifying the I signal; and a second limiter for amplifying
the Q signal.
11. A method for demodulating an IF FSK signal comprising:
receiving a modulated signal; generating an IF I signal and an IF Q
signal from the received modulated signal without converting the
received modulated signal to a baseband signal; and extracting
frequency information from the I signal and the Q signal;
12. The method of claim 11, further comprising converting the
frequency information to digital data.
13. The method of claim 11, further comprising: differentiating the
I signal at the frequency of the I signal by a first IF
differentiator; differentiating the Q signal at the frequency of
the Q signal by a second IF differentiator; multiplying the
differentiated I signal with the Q signal; and multiplying the
differentiated Q signal with the I signal to extract the frequency
information.
14. The method of claim 13, wherein the step of differentiating the
I signal comprises applying a transfer function of V o V i .times.
( jw ) = - jRC .times. .times. ( w - 1 R 1 .times. C ) ( 1 )
##EQU5## to the I signal, where V.sub.o is an output signal,
V.sub.i is an input signal, R, R.sub.1, and C are the values for
two resistors and a capacitor, respectively.
15. The method of claim 13, wherein the step of differentiating the
Q signal comprises applying a transfer function of V o V i .times.
( jw ) = - jRC .times. .times. ( w - 1 R 1 .times. C ) ( 1 )
##EQU6## to the Q signal, where V.sub.o is an output signal,
V.sub.i is an input signal, R, R.sub.1, and C are the values for
two resistors and a capacitor, respectively.
16. The method of claim 13, wherein the step of converting the
frequency information to digital data comprises: receiving an
analog data input and a slow/fast signal for generating a peak
signal responsive to peak of the analog data input signal;
receiving an analog data input and a slow/fast signal for
generating a valley signal responsive to valleys of the analog data
input signal; taking the average of the peak signal and the valley
signal; and generating a high signal if the analog data input is
higher than its average value, and generating a low signal if the
analog data input is lower than its average value.
17. The method of claim 13, further comprising the step of
amplifying the I signal and the Q signal.
18. An IF demodulator comprising: a first IF differentiator for
differentiating an I signal without down conversion to a baseband
signal; a second IF differentiator for differentiating a Q signal
without down conversion to a baseband signal; and an extractor for
extracting frequency information from the I signal and the Q
signal.
19. The IF demodulator of claim 18, further comprising a slicer for
converting the frequency information to digital data.
20. The IF demodulator of claim 18, wherein the extractor comprises
a cross-coupled multiplier for multiplying the differentiated I
signal with the Q signal and multiplying the differentiated Q
signal with the I signal.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This patent application is a continuation of U.S. patent
application Ser. No. 09/960,536, filed Sep. 21, 2001, which claims
the benefit of the filing date of U.S. Provisional Patent
Application Ser. No. 60/253,268, filed Nov. 27, 2000 and entitled
"IF FSK DEMODULATOR"; the entire contents of which are hereby
expressly incorporated by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to communication systems. More
specifically, the invention relates to signal demodulation.
BACKGROUND OF THE INVENTION
[0003] Some radio transmission standards such as, the Bluetooth
standard, specify a 2.4 GHz frequency-hopped, spread-spectrum
system using a Gaussian-FSK (GFSK) modulation scheme with a data
rate of 1 Mb/sec. The frequency offsets are .+-.160 kHz,
corresponding to a nominal modulation index of 0.32 and the data
bandwidth is about 1 MHz. Consequently, an exemplary Bluetooth
receiver has a 2 MHz intermediate frequency (IF), causing the image
signal to be within the 80 MHz ISM band. The image reject
requirement is therefore relaxed, and may be achieved by an on-chip
complex-domain bandpass filter (BPF). Once the desired channel is
selected, a limiter amplifies it to a well-defined level, and the
received signal strength is indicated.
[0004] A commonly used type of pulse-code modulation is FSK, in
which the carrier frequency changes abruptly by an amount .DELTA.f
as the modulating signal changes from the zero level to the one
level, or vice versa. A FSK demodulation typically uses a
differentiator followed by I and Q multipliers. However, if
implemented at base-band, the desired signal at 2 MHz is
down-converted to zero IF. This approach needs to use four
additional mixers for single side-band, quadrature downconversion,
and a 2 MHz clock generator. This increases the receiver power
dissipation, and leads to a larger silicon area. Additionally, the
base-band demodulator is more susceptible to DC offset and low
frequency noise and interference.
[0005] Typically, an analog differentiator followed by an envelope
detector can be used to detect an FM modulated signal. This is
simple and low-power, however, its performance is limited due to
the inaccuracy of the components once realized in an IC. In
contrast, an FSK demodulator may be implemented digitally, which is
more robust, yet it consumes more power, and is more complex.
[0006] Moreover, a direct-conversion receiver also has few
disadvantages. For example, since the GFSK spectrum has energy at
zero IF, DC offset and 1/f noise may degrade the receiver
performance. Also, a limiter at base-band is generally not suitable
for a GFSK signal down-converted to zero IF, since the harmonics of
the limited signal fall inside the desired band, degrading the
receiver BER. This problem may be evaded if the limiter is
substituted by an automatic gain controller (AGC). However, an AGC
is complicated and consumes more power.
[0007] Therefore, there is a need for a radio transceiver having
the characteristics of low size, cost and power. Furthermore, there
is a need for a receiver including an analog demodulator and a
differentiator that operate at an IF frequency rather than a
baseband frequency.
SUMMARY OF THE INVENTION
[0008] In one embodiment, the present invention describes a
low-power, and high performance receiver including an IF
demodulator for high data rate, frequency modulated systems, such
as Bluetooth. The IF demodulator is implemented in analog domain
for simplicity and lower power consumption and operates at an IF
frequency.
[0009] In one aspect, an IF demodulator comprising: a first IF
differentiator for differentiating an I signal; a second IF
differentiator for differentiating a Q signal; a cross-coupled
multiplier for multiplying the differentiated I signal with the Q
signal and multiplying the differentiated Q signal with the I
signal to extract frequency information from the I signal and the Q
signal; and a slicer for converting the frequency information to
digital data is disclosed in the present invention.
[0010] In another aspect, a method for demodulating an IF FSK
signal comprising the steps of: receiving an IF I signal input and
an IF Q signal input; differentiating the I signal at the frequency
of the I signal by a first IF differentiator; differentiating the Q
signal at the frequency of the Q signal by a second IF
differentiator; multiplying the differentiated I signal with the I
signal and multiplying the differentiated Q signal with the Q
signal for extracting frequency information from the I signal and
the Q signal; and converting the frequency information to digital
data is described in the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The objects, advantages and features of this invention will
become more apparent from a consideration of the following detailed
description and the drawings, in which:
[0012] FIG. 1 is an exemplary low-IF receiver architecture,
according to one embodiment of the present invention;
[0013] FIG. 2 is an exemplary block diagram of an IF demodulator,
according to one embodiment of the present invention;
[0014] FIG. 3 is an exemplary block diagram of an IF
differentiator, according to one embodiment of the present
invention;
[0015] FIG. 4 is an exemplary block diagram of a slicer, according
to one embodiment of the present invention;
[0016] FIG. 5 is an exemplary simplified circuit diagram of an IF
differentiator, according to one embodiment of the present
invention;
[0017] FIG. 6 is an exemplary simplified circuit diagram of a
multiplier, according to one embodiment of the present
invention;
[0018] FIG. 7 is an exemplary simplified circuit diagram of an
offset tracker, according to one embodiment of the present
invention; and
[0019] FIG. 8 is an exemplary simplified circuit diagram of a
peak/valley detector, according to one embodiment of the present
invention.
DETAILED DESCRIPTION
[0020] To lower the size, cost and power of portable devices with
wireless connectivity, all the components are integrated into one
single chip. Full integration of a radio transceiver system can
reduce cost and power consumption, which can be accomplished by
moving the bulky and expensive external image reject, channel
select filters and baluns onto a single RF chip and eliminating the
number of off-chip passive elements such as capacitors, inductors,
and resistors by moving them onto the chip, and integrating all the
components including RF, analog, baseband and digital signal
processing (DSP) onto the chip.
[0021] The present invention discloses a receiver including an FSK
demodulator for use in various applications including Bluetooth.
FIG. 1 shows an exemplary low-IF receiver architecture in
accordance with an embodiment of the present invention. Low noise
amplifier (LNA) 10 amplifies the input signal at 2.4 GHz. Down
converters 12 and 14 convert the amplified input signal to a lower
frequency signal, for example, a 2 MHz signal by mixing the input
signal with respective lower frequency signals LOI and LOQ that are
generated locally. A channel selector filter 16 selects a desired
channel of frequency. e.g., a 2 MHz channel. The channel selector
filter is essentially a bandpass filter (BPF) that passes through
the selected frequency and rejects the other frequencies.
[0022] Amplifiers 18 and 19 further amplify the I and Q signals
respectively. In one implementation, limiters which are a special
form of amplifiers are used because they are simpler, low power,
and easier to implement. Demodulator 11 exploits the amplified 2
MHz signal to detect the amplitude of the differentiated signal.
Since the input signal to the demodulator 11 is at 2 MHz, the
demodulator is designed in such a unique way to work at 2 MHz,
without having to convert the 2 MHz signal to the baseband signal.
An RC calibration 13 circuit monitors process variation and
mismatch variations and tunes the receiver to avoid spurious
signals. In one embodiment, the RC calibration 13 calibrates all
the active resistors and capacitors to some reference frequency
that has a well defined behavior. Self-calibration may be used in
the receiver for optimal performance and programmed through
software.
[0023] FIG. 2 is an exemplary implementation of the demodulator 11
in FIG. 1. BPF 21 is used to shape the limited input signal
waveform to a sinusoidal shaped waveform. This BPF rejects the
harmonics of the desired channel. Moreover, it attenuates the
remaining adjacent interference due to the incomplete channel
selection at the BPF. Differentiators 22 and 23 take the I and Q
signal and differentiate them to take the frequency information
(.phi.(t)) out of the sinusoidal input signals I and Q. However,
this frequency information may include some undesired signals and
noise. The cross-couple multipliers 24 and 25 multiply I and Q
signals with differentiated Q and I respectively and subtractor 26
subtracts the multiplied signals so that the sin and cos cancel out
each other to produce a non-sinusoidal signal A .phi.(t) plus spurs
at the output of the subtractor 26.
[0024] As quadrature signals are available at the demodulator 11
input, the differentiators 22 and 23 shift their center frequency
to some desired IF, e.g., 2 MHz. As illustrated in FIG. 3, a
resistor (R1)connected to the Q (and I) input (jv is the input
signal from Q channel), translates the base-band frequency response
to an IF set by 1/R1C. The frequency response of the IF
differentiator is expressed in the following equation: V o V i
.times. ( jw ) = - jRC .times. .times. ( w - 1 R 1 .times. C ) ( 1
) ##EQU1##
[0025] Thus, the center frequency of the IF differentiator moves to
1/R1C. This center frequency may be adjusted by selecting
appropriate values for R1 and C to any IF frequency. In one
implementation the values for R1 and C are selected to obtain an IF
frequency of 2 MHz.
[0026] Referring back to FIG. 2, a lowpass filter (LPF) 27 cleans
the demodulated spectrum whose bandwidth is about .+-.550 kHz to
get ride of the spurs. The LPF 27 is sharp enough to reject the
undesired signals produced due to the non-ideal mixing action in
the multipliers or mismatches, yet wide enough not to filter the
desired signal, or cause settling issues. Following the LPF 27, a
slicer 28 is used to convert the analog detected output to digital
bits.
[0027] FIG. 4 is an exemplary block diagram for the slicer 28 of
FIG. 2. As shown in FIG. 4, the slicer includes a peak detector 41,
a valley detector 42, an offset tracking circuit 43 at the output
of the peak and valley detector, and a comparator 44 at the output
of the offset tracking. The offset tracking circuit 43 adjusts the
DC level of the analog eye by taking the average of the peak and
valley detector outputs. Digital eye is produced by comparing this
DC offset to the analog eye.
[0028] A .phi.(t), the analog signal at the input of the slicer 28
in FIG. 2, is applied to the inputs of the peak detector 41 and the
valley detector 42 in FIG. 4. The peak detector 41 detects the peak
of the analog input signal V.sub.p and the valley detector 42
detect the valleys (minimums) of the analog input signal V.sub.v.
The offset tracking circuit 43 takes the average of V.sub.p and
V.sub.v ((V.sub.p+V.sub.v)/2) to produce a DC average of the peak
and valley. This DC average signal is compared with the original
analog signal by comparator 44 to produce the desired digital
output. At the output of comparator, a high signal is produced if
the analog input signal is higher than its DC average value, and a
low signal is produced if the analog input signal is lower than its
DC average value. The Slow/Fast signal depicted in FIG. 4 indicates
whther the slicer must go to fast attack mode or slow decay mode
described below.
[0029] Any frequency error caused by the crystal inaccuracy would
result in a DC component at demodulator 11 analog output. However,
since the slicer detects the DC level of the analog eye, both
inputs of the comparator are shifted because of this DC offset, and
the digital eye remains unaffected.
[0030] To achieve a robust performance and to minimize the
sensitivity to process variation, in one embodiment, the individual
blocks are implemented using local feedback. Thus, the demodulator
characteristics, such as analog eye amplitude or its DC level are
set merely by the ratio of the resistors or devices which are
accurately defined in an IC.
[0031] FIG. 5 is an exemplary circuit implementation of a
differentiator (blocks 22 or 23 in FIG. 2), according to one
embodiment of the present invention. The IF differentiator uses a
single-stage operational amplifier (op-amp) followed by a
common-source stage in a unity gain feedback, as shown in FIG. 5.
The differential inputs pairs I+, I-, Q+, and Q- are connected to
the differential op-amp 51 via R1, c1, R2, and C2 respectively,
where R1=R2 and C1=C2. There is a feedback loop from each input of
the op-amp 51 to its respective output through transistors M1 and
M2, respectively. This feedback loop preserves the same AC voltage
at the gates of transistors M1 and M3.
[0032] Transistors M3 and M4 form the input stage of a multiplier
(blocks 24 or 25 in FIG. 2). The values for the four transistors
M1, M2, M3, and M4 are the same so that the same amount of current,
I.sub.M3 flows through all of them. Thus, if the signal at the
differentiator input is V.sub.i, the AC current flowing through
transistors M1/M2 will be equal to: i M1 = jC .times. .times. ( w -
1 R 1 .times. C ) .times. V i ( 2 ) ##EQU2##
[0033] This current is mirrored into the input devices (M3/M4) of
the multipliers which are implemented as Gilbert-type mixers, shown
in FIG. 6.
[0034] FIG. 6 is an exemplary circuit implementation for multiplier
25 (I multiplier) of FIG. 2. The Q multiplier 24 has a similar
circuit implementation. The input stage of the multiplier (M3/M4)
takes the differential input IN+ and IN- that is the output of the
BPF 21 in FIG. 2. Transistors M5/M6 and M7/M8 form the differential
pair Gilbert-type mixers that take the differential input LO+ and
LO- to multiply LO signal by IN signal. As shown, the outputs of
the I multiplier are connected to the outputs of the Q multiplier
(not shown) to simply form the subtractor block 26 of FIG. 2. The
common mode feedback (CMFB) 61 is used to adjust the DC output
levels.
[0035] Assuming an ideal switching loss of 2/.pi. and a load
resistance of R in the multipliers, the signal at the multipliers
output will be: V 0 = ( A .times. 2 .pi. .times. RC ) .PHI. .times.
.times. ( t ) ( 3 ) ##EQU3##
[0036] Where A is the amplitude of the signal at the differentiator
input (Vi), and .phi.(t) is its frequency information. In equation
2, 1/R1C is set to 2 MHz.
[0037] Any mismatch between I and Q paths causes an incomplete
addition of Cos.sup.2 and Sin.sup.2 components at the multipliers
output, producing an undesired signal at 2.omega..sub.IF. In
addition, a DC offset at the multiplier LO or input port creates an
undesired signal at .omega.IF at the multiplier output. However,
for 2 MHz IF, all these spurs are located at least at 2 MHz or
above, and the LPF 27 whose bandwidth is about 550 kHZ rejects
them.
[0038] Since the gain and center frequency of the differentiator,
as well as the bandwidth and center frequency of the filters are
determined by the RCs, an on-chip calibration circuit is designed
to adjust the RC time constants in the presence of temperature and
process variation, as shown in FIG. 1. In one embodiment, all the
capacitors are implemented as digitally-controlled binary array of
capacitors. The RC calibration circuit tunes 1/RC to a reference
crystal frequency.
[0039] In this embodiment, both the post-limiter BPF and the LPF
after the multipliers are realized as active RC configuration.
Therefore, their passband gain is accurately set by ratio of the
resistors. Moreover, the input signal amplitude (A in equation 3)
is set by the limiter, which is constant over process or
temperature variation, and is independent of the received signal
power. As a result, the gain of demodulator only depends on the
differentiator gain, that is, RC, which is precisely controlled by
the on-chip calibration circuit.
[0040] FIG. 7 is an exemplary circuit implementation for the offset
tracker 43 of FIG. 4. The drains of the transistors M1 & M2 is
connected and their sources are connected to two equal value
resistors R. Current I1 is proportional to V.sub.p+V.sub.v/R,
therfore proportional to the average of V.sub.p and V.sub.v.
Transistors M3 and M4 have a similar arrangement to M1 and M2
arrangement, except that heir gates are connected together and is
driven by V.sub.a, the analog input. As a result, I2 current is
proportional to 2V.sub.a/R.
[0041] FIG. 8 is an exemplary simplified circuit diagram for a peak
(or valley) detector (blocks 41 and 42 in FIG. 4). The peak/valley
detectors take the peak (or valley) of the input signal as an input
and charge the capacitor C to a peak (or a valley) using the OpAmp
81 and the PMOS transistor M80. However, since the leakage current
of the capacitor C is small, the capacitor C takes a long time to
charge or discharge in response to changes in peaks or valleys.
OpAmp 81 is a differential pair OpAmp with single ended output.
When the signal at the input of the OpAmp increases, because of the
OpAmp's high gain, its output goes to zero which in turn, turns
transistor M80 on. That pulls the output voltage high to adjust the
peak value.
[0042] To ameliorate the slow nature of the peak/valley detectors,
two time constants, namely fast attack and slow decay, are assigned
to the detectors, as shown in FIG. 8. At the receiver start-up, the
detectors are switched to fast attack mode by fast switch S1 that
is connected to a large current sink, regulating their outputs
quickly to the peak and valley of the received analog eye. Once
this initial adjustment is accomplished, the detectors switch to
slow decay mode by S2 that is connected to a small current sink,
where the peak/valley detector capacitor C at the OUT node is
slowly discharged by the leakage current I.sub.small. These time
constants are adaptively set by detecting the received eye
amplitude, and based on the receiver start-up signal through
controlling the timing of the two switches S1 and S2.
[0043] In one embodiment, an FSK demodulator for use in various
applications including Bluetooth is implemented in a 0.35 .mu.m
CMOS process. The entire exemplary demodulator, integrated as a
part of a low-IF receiver with 2 MHz intermediate frequency,
consumes 3 mA from 2.7 V supply. The required signal-to-noise ratio
(SNR) for 0.1% bit error rate (BER) is about 18 dB in this
implementation.
[0044] It will be recognized by those skilled in the art that
various modifications may be made to the illustrated and other
embodiments of the invention described above, without departing
from the broad inventive scope thereof. It will be understood
therefore that the invention is not limited to the particular
embodiments or arrangements disclosed, but is rather intended to
cover any changes, adaptations or modifications which are within
the scope of the invention as defined in the claims.
* * * * *