U.S. patent application number 11/208339 was filed with the patent office on 2005-12-22 for semiconductor constructions.
Invention is credited to Yates, Donald L..
Application Number | 20050282397 11/208339 |
Document ID | / |
Family ID | 33540844 |
Filed Date | 2005-12-22 |
United States Patent
Application |
20050282397 |
Kind Code |
A1 |
Yates, Donald L. |
December 22, 2005 |
Semiconductor constructions
Abstract
The invention includes semiconductor processing patterning
methods and semiconductor constructions. A semiconductor processing
patterning method includes forming a second composition resist
layer over a different first composition resist layer. Overlapping
portions of the first and second composition resist layers are
exposed to actinic energy effective to change solubility of the
exposed portions versus the unexposed portions of each of the first
and second composition resist layers in a developer solution. The
first and second composition resist layers are developed with the
developer solution under conditions effective to remove the exposed
portions of the first composition resist layer at a faster rate
than removing the exposed portions of the second composition resist
layer. Additional aspects and implementations are contemplated.
Inventors: |
Yates, Donald L.; (Boise,
ID) |
Correspondence
Address: |
WELLS ST. JOHN P.S.
601 W. FIRST AVENUE, SUITE 1300
SPOKANE
WA
99201
US
|
Family ID: |
33540844 |
Appl. No.: |
11/208339 |
Filed: |
August 18, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11208339 |
Aug 18, 2005 |
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10609311 |
Jun 26, 2003 |
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Current U.S.
Class: |
438/745 ;
257/E21.027; 257/E21.234; 430/311 |
Current CPC
Class: |
H01L 21/3085 20130101;
G03F 7/095 20130101; H01L 21/0274 20130101 |
Class at
Publication: |
438/745 ;
430/311 |
International
Class: |
G03C 005/00; H01L
021/302; H01L 021/461 |
Claims
1-57. (canceled)
58. A semiconductor construction comprising a semiconductor
substrate having a patterned resist mask received thereon, the
resist mask comprising a first composition resist portion and a
different second composition resist portion received over the first
composition resist portion, the first composition resist portion
having opposing sidewalls in at least one cross section and the
second composition resist portion having opposing sidewalls in the
one cross section, at least a portion of the opposing sidewalls of
the first composition resist portion being recessed laterally
inward of at least a portion of the opposing sidewalls of the
second composition resist portion.
59. The semiconductor construction of claim 58 wherein the second
composition resist portion is received on the first composition
resist portion.
60. The semiconductor construction of claim 58 wherein both the
first composition resist portion and the second composition resist
portion comprise negative resist.
61. The semiconductor construction of claim 58 wherein both the
first composition resist portion and the second composition resist
portion comprise positive resist.
62. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than a
thickness of the second composition resist portion.
63. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than a
total thickness of all layers received over the first composition
resist portion.
64. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than or
equal to about 50% of a total thickness of the first composition
resist portion and all layers received over the first composition
resist portion.
65. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than or
equal to about 25% of a total thickness of the first composition
resist portion and all layers received over the first composition
resist portion.
66. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than or
equal to about 10% of a total thickness of the first composition
resist portion and all layers received over the first composition
resist portion.
67. The semiconductor construction of claim 58 wherein the first
composition resist portion has a thickness which is less than or
equal to about 5% of a total thickness of the first composition
resist portion and all layers received over the first composition
resist portion.
68. The semiconductor construction of claim 58 wherein the opposing
sidewalls of the first composition resist portion are at least
partially curved in the one cross section.
69. The semiconductor construction of claim 58 wherein the opposing
sidewalls of the first composition resist portion and the opposing
sidewalls of the second composition resist portion are of different
shapes in the one cross section.
70. The semiconductor construction of claim 58 wherein an entirety
of the opposing sidewalls of the first composition resist portion
in the one cross section are recessed laterally inward of the
opposing sidewalls of the second composition resist portion in the
one cross section.
Description
TECHNICAL FIELD
[0001] The present invention relates to semiconductor processing
patterning methods and constructions.
BACKGROUND OF THE INVENTION
[0002] A continuing goal of semiconductor processing is increased
miniaturization while maintaining high performance. Modern
semiconductor processes are heavily reliant on photolithography
when preparing semiconductors to achieve this goal.
[0003] Photolithography typically involves the following steps.
Initially, a layer of resist is formed over a substrate. A
reticle/mask is subsequently placed above the resist and radiation
is allowed to pass through openings of the reticle/mask and contact
the resist in patterns defined by the reticle/mask. Depending on
whether the resist is a negative resist or a positive resist, the
radiation renders exposed portions of the resist more or less
soluble in a solvent relative to unexposed portions. The solvent is
subsequently utilized to remove the more soluble portions of the
resist while leaving the less soluble portions as a patterned mask.
The mask pattern can be transferred to the underlying substrate
with a suitable etch. Exemplary methods of prior art
photolithography and a problem therewith are illustrated in FIGS.
1-3.
[0004] Referring first to FIG. 1, a semiconductor substrate 1 at
one stage of semiconductor processing is shown that includes a bulk
substrate 3, multilayers 4 (e.g., conductive, semiconductive and/or
insulative layers) and a resist 5. To aid in interpretation of the
claims that follow, the terms "semiconductive substrate" and
"semiconductor substrate" are defined to mean any construction
comprising semiconductive material, including, but not limited to,
bulk semiconductive materials such as a semiconductive wafer
(either alone or in assemblies comprising other materials thereon),
and semiconductive material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above.
[0005] Referring to FIG. 2, photoresist layer 5 has been processed
to form masking blocks 7. It would be desirable that these masking
blocks be of constant respective width in the illustrated
cross-section from top to bottom. However in certain instances, the
patterned photoresist tends to flare out at the bottoms/bases, as
shown, forming what are commonly referred to as "footing", depicted
by feet 9.
[0006] Referring to FIG. 3, layers 4 have been etched using blocks
7 as an etch mask. As shown, feet 9 have functioned as part of that
mask making the pattern of layers 4 substantially wider than the
predominate width of blocks 7. In many instances, this is
undesirable and/or difficult to predict or control.
SUMMARY OF THE INVENTION
[0007] The invention includes semiconductor processing patterning
methods and semiconductor constructions. In one implementation, a
semiconductor processing patterning method includes forming a
second composition resist layer over a different first composition
resist layer. Overlapping portions of the first and second
composition resist layers are exposed to actinic energy effective
to change solubility of the exposed portions versus the unexposed
portions of each of the first and second composition resist layers
in a developer solution. The first and second composition resist
layers are developed with the developer solution under conditions
effective to remove the exposed portions of the first composition
resist layer at a faster rate than removing the exposed portions of
the second composition resist layer.
[0008] In one implementation, a semiconductor construction includes
a semiconductor substrate having a patterned resist mask received
thereon. The resist mask includes a first composition resist
portion and a different second composition resist portion received
over the first composition resist portion. The first composition
resist portion has opposing sidewalls in at least one cross section
and the second composition resist portion has opposing sidewalls in
the one cross section. At least a portion of the opposing sidewalls
of the first composition resist portion are recessed laterally
inward of at least a portion of the opposing sidewalls of the
second composition resist portion.
[0009] Additional aspects and implementations are contemplated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings
[0011] FIG. 1 is a diagrammatic cross-sectional view of a prior art
semiconductor construction at one stage of processing.
[0012] FIG. 2 is a view of the FIG. 1 construction shown at a
processing step subsequent to that of FIG. 1.
[0013] FIG. 3 is a view of the FIG. 2 construction shown at a
processing step subsequent to that of FIG. 2.
[0014] FIG. 4 is a diagrammatic cross-sectional view of a
semiconductor construction in accordance with an aspect of the
present invention at one stage of processing.
[0015] FIG. 5 is a view of the FIG. 4 construction shown at a
processing step subsequent to that of FIG. 4.
[0016] FIG. 6 is a view of the FIG. 5 construction shown at a
processing step subsequent to that of FIG. 5.
[0017] FIG. 7 is an enlarged view of a portion of the FIG. 6
construction.
[0018] FIG. 8 is a view of the FIG. 6 construction shown at a
processing step subsequent to that of FIG. 6.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0020] An exemplary semiconductor processing patterning method, in
accordance with some aspects of the invention, is described with
reference to FIGS. 4-8. Referring to FIG. 4, a wafer fragment 12
includes a bulk semiconductor substrate material 14, for example
monocrystalline silicon. Of course other substrates, for example
semiconductor-on-insulat- or substrates and other substrates
whether existing or yet-to-be developed, could be utilized. One or
more series of layers 16 are formed over material 14 for
patterning. A first layer of resist 18 is formed over substrate
16/14. Resist layer 18 might be photosensitive or otherwise
impacted by actinic energy (for example UV radiation, e-beam or
other actinic energy) to change solubility of exposed versus
unexposed portions in a suitable developer solution. Further,
resist layer 18 might be a positive resist or a negative resist. In
one implementation, the first layer of resist layer 18 is
photosensitive to electromagnetic radiation at no greater than
about 325 nm. By way of example, an exemplary thickness for layer
18 is less than about 700 .ANG..
[0021] A second layer of resist 20 is formed over first layer of
resist 18. As shown in one implementation, second layer of resist
20 is formed "on" (meaning in direct physical contact) with first
layer of resist 18. First layer of resist 18 and second layer of
resist 20 can be of different compositions at least as initially
formed. Further, second layer of resist 20 might be a positive
resist or a negative resist.
[0022] In one implementation, resist layers 18 and 20 are both
positive resist with layer 18 being provided to have a greater
solubility in a developer solution than does second positive resist
layer 20 at least after exposure to actinic energy effective to
increase the solubility of each of the first and second positive
resist layers in the developer solution. An exemplary material for
first layer of resist 18 includes 1-methoxy-2-propanol, while an
exemplary material for second layer of resist 20 includes
cyclohexanone and 2-heptanone. An exemplary developer solution for
such materials inlcudes tetramethyl ammonium hydroxide (TMAH).
[0023] Regardless of whether positive or negative resist are
utilized, exemplary ways of modifying the erosion rate or the etch
rate of a resist include adding to, subtracting from, or varying
the composition of any of the components within the resist. For
example, the use of, and/or type of resins, stabilizers,
photoactive agents, polymers, molecular weight distribution, etc.,
can have an impact on the erosion or etch rate of a resist as is
known and determined by people of skill in the art.
[0024] By way of example only, a specific exemplary positive resist
material for first layer of resist 18 is SEPR-402 available from
Shin-Etsu Chemical Company of Chiyoda-ku, Tokyo. Such is understood
to include 1-methoxy-2-propanol, ethyl lactate and one or more
proprietary components. After suitable exposure to actinic energy
and development in a 21.degree. C., 2.26 N/2.25% by weight TMAH in
H.sub.2O developer solution, SEPR-402 has an erosion or etch rate
of about 500 Angstroms per minute.
[0025] Another example for first layer of resist 18 is M230Y
available from the JSR Corporation of Sunnyvale, Calif. Such is
understood to include 1-methoxy-2-propanol, ethyl lactate and
various proprietary components. In the same developer solution
described above, such has an erosion rate of about 300 Angstroms
per minute. With such exemplary different etch rates, the M230Y
might be used as an exemplary material for second layer of resist
20, with material SEPR-402 used as an exemplary material for first
layer of resist 18. However, in certain circumstances it may be
beneficial to utilize a material having an even slower etch rate
for second layer of resist 20. By way of example only, such
includes AR-360S manufactured by the JSR Corporation. Such is
understood to include cyclohexanone, 2-heptanone and at least three
proprietary components. Such material has an erosion or etch rate
after exposure and development in the above developer solution of
approximately 50 Angstroms per minute.
[0026] Other layers of resist and/or with other non-resist layers
might also be utilized. For example, multi-level resist which
typically combines resist and non-resist layers might be utilized.
Regardless, in one preferred implementation, first layer of resist
18 has a thickness which is less than a total thickness of all
layers received above it. In one implementation, first layer of
resist 18 has a thickness which is less than or equal to about 50%
(more preferably 25%, even more preferably 10%, and still more
preferably 5%) of the total thickness of first layer of resist 18
and all layers received over first layer of resist 18. Further for
example where the only other layer received above first layer of
resist 18 is second layer of resist 20, the above-referred
relationships apply relative to the thickness of second layer of
resist 20.
[0027] Referring to FIG. 5, overlapping portions of first resist
layer 18 and second resist layer 20 have been exposed to actinic
energy effective to change solubility of the exposed portions
versus the unexposed portions of each of the first and second
resist layers 18 and 20 in a developer solution. For example, such
could be conducted using a photolithographic mask/reticle, or by
any other existing or yet-to-be developed techniques. In the
particular illustrated and described implementation, the first and
second layers of resist are both positive resists, and the
illustrated overlapping portions 22 and 24 are masked while the
remaining portions of layers 18 and 20 would be exposed to
effectively increase their solubility in a developer solution. Of
course, negative resist could be utilized where the opposite
relationship would occur.
[0028] Referring to FIG. 6, first layer of resist 18 and second
layer of resist 20 are developed with a suitable developer solution
to form mask patterns 26 and 28 which comprise the first and second
resist layers. In one implementation, the developing solution
removes or etches the exposed portions, for example those exposed
in FIG. 5, of first layer of resist 18 at a rate that is faster
than the exposed portions of second layer of resist 20. Regardless,
first resist layer 18 of the respective mask patterns 26 and 28 has
respective opposing sidewalls 30 and 32 in at least one
cross-section, for example that illustrated by FIG. 6. Further in
one implementation, second resist layer 20 of the respective mask
patterns 26 and 28 has respective opposing sidewall 34 and 36 in
the one cross-section. As shown, at least a portion of opposing
sidewalls 30 and 32 of first resist layer 18 are received laterally
inward of at least a portion of opposing sidewalls 34 and 36 of
second resist layer 20 in the one cross-section. As shown, the
entirety of the opposing sidewalls 30 and 32 of first resist layer
18 in the one-cross-section are recessed laterally inward of
opposing sidewalls 34 and 36 of second resist layer 20 in the one
cross-section (FIGS. 6 and 7).
[0029] In one implementation, the opposing sidewalls of the first
resist layer and the opposing sidewalls of the second resist layer
are of different shapes in the one cross-section. For example and
by way of example only, opposing sidewalls 34 and 36 of second
resist layer 20 are generally straight along a substantial portion
of their length, while opposing sidewalls 30 and 32 of first resist
layer 18 are not. Further in one implementation, opposing sidewalls
30 and 32 of first resist layer 18 are at least partially curved in
the one cross-section, with FIGS. 6 and 7 showing such sidewalls as
being curved about their substantial entire lengths.
[0030] In addressing the issue or problem identified in the
Background section above, one goal or object might be to reduce or
eliminate the described footing. Where reduced footing or footing
elimination occurs, a possible non-limiting theory is that one or
both of the sidewall recessing, or faster etching rate of the first
layer of resist, provides for the attack of any forming foot from
underneath the foot as well as to a greater degree from its sides.
The prior art processes may essentially be limited to the attack of
only the top of the foot by developer solutions.
[0031] Referring to FIG. 8, material 16 of substrate 12 has been
etched using mask patterns 26 and 28 as a mask. The artisan would,
of course, select a suitable chemistry or chemistries in etching
material 16, and at least some of one or more of resist materials
20 and 18 might also be etched to some degree in the process.
[0032] In one aspect, the invention also contemplates a
semiconductor construction independent of the exemplary
above-described methods. Such a construction comprises a
semiconductor substrate having a patterned resist mask received
thereon, for example as shown in FIG. 6. The resist mask comprises
a first composition resist portion and a different second
composition resist portion received over the first composition
resist portion. The first composition resist portion has opposing
sidewalls in at least one cross-section, and the second composition
resist portion has opposing sidewalls in the one cross-section. At
least a portion of the opposing sidewalls of the first composition
resist portion are recessed laterally inward of at least a portion
of the opposing sidewalls of the second composition resist portion.
Exemplary and preferred attributes of the resist mask, first
composition resist portion, second composition resist portion, and
opposing sidewalls are as described above with respect to the
methodical aspects.
[0033] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *