U.S. patent application number 10/872408 was filed with the patent office on 2005-12-22 for isolation trench geometry for image sensors.
Invention is credited to Cole, Bryan G., Rhodes, Howard E..
Application Number | 20050279998 10/872408 |
Document ID | / |
Family ID | 35479699 |
Filed Date | 2005-12-22 |
United States Patent
Application |
20050279998 |
Kind Code |
A1 |
Cole, Bryan G. ; et
al. |
December 22, 2005 |
Isolation trench geometry for image sensors
Abstract
A pixel cell including a substrate having a top surface. A
photo-conversion device is at a surface of the substrate and a
trench is in the substrate adjacent the photo-conversion device.
The trench has sidewalls and a bottom. At least one sidewall is
angled less than approximately 85 degrees from the plane of the top
surface of the substrate.
Inventors: |
Cole, Bryan G.; (Boise,
ID) ; Rhodes, Howard E.; (Boise, ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L Street, NW
Washington
DC
20037
US
|
Family ID: |
35479699 |
Appl. No.: |
10/872408 |
Filed: |
June 22, 2004 |
Current U.S.
Class: |
257/59 ; 257/79;
257/E27.133; 438/22 |
Current CPC
Class: |
H01L 27/1463 20130101;
H01L 27/14689 20130101; H01L 27/14643 20130101 |
Class at
Publication: |
257/059 ;
257/079; 438/022 |
International
Class: |
H01L 029/04; H01L
021/00 |
Claims
What is claimed as new and desired to be protected by Letters
Patent of the United States is:
1. A pixel cell comprising: a substrate having a top surface; a
photo-conversion device; and a trench formed in the substrate
adjacent the photo-conversion device, the trench having sidewalls,
at least one sidewall on the side of the photo-conversion device
being angled less than approximately 85 degrees from a plane of a
top surface of the substrate.
2. The pixel cell of claim 1, wherein the trench is formed to a
depth of approximately 500 .ANG. to approximately 5000 .ANG..
3. The pixel cell of claim 2, wherein the trench is formed to a
depth of approximately 1000 .ANG. to approximately 3000 .ANG..
4. The pixel cell of claim 1, wherein the at least one angled
sidewall has an angle within the range of approximately 15 degrees
to approximately 70 degrees.
5. The pixel cell of claim 1, wherein the at least one angled
sidewall has an angle within the range of approximately 60 degrees
to approximately 70 degrees.
6. The pixel cell of claim 1, wherein each sidewall is angled less
than approximately 85 degrees with respect to the plane.
7. The pixel cell of claim 1, wherein a first sidewall is angled
less than approximately 85 degrees with respect to the plane, the
first sidewall being adjacent the photo-conversion device, and a
second sidewall is angled greater than or equal to approximately 80
degrees with respect to the plane.
8. The pixel cell of claim 1, further comprising a doped well of a
first conductivity type formed in the substrate surrounding the
trench.
9. The pixel cell of claim 8, wherein the photo-conversion device
is a pinned photodiode comprising a doped surface layer of a first
conductivity type.
10. The pixel cell of claim 9, wherein the doped surface layer is
connected to the doped well.
11. The pixel cell of claim 1, wherein the photo-conversion device
is a p-n type photodiode.
12. The pixel cell of claim 1, wherein the photo-conversion device
is a photoconductor.
13. The pixel cell of claim 1, wherein the photo-conversion device
is a photogate.
14. The pixel cell of claim 1, wherein the trench is at least
partially filled with a dielectric material.
15. The pixel cell of claim 1, wherein the trench is lined with
nitride.
16. The pixel cell of claim 15, wherein the trench is lined with
oxide.
17. The pixel cell of claim 16, wherein the trench is filled with a
dielectric material and the nitride liner is between the dielectric
material and the oxide liner.
18. The pixel cell of claim 1, wherein the trench is at least
partially filled with a material selected from the group consisting
of a silicon oxide, a nitride, silicon carbide, a high temperature
polymer, and a high density plasma.
19. The pixel cell of claim 1, wherein the pixel cell is part of a
CMOS image sensor.
20. The pixel cell of claim 1, wherein the pixel cell is part of a
charge coupled device image sensor.
21. A pixel cell comprising: a substrate having a top surface; a
photo-conversion device; and a trench formed in the substrate
adjacent to the photo-conversion device, the trench having
sidewalls and being lined with a nitride liner, the sidewalls being
angled from a plane of a top surface of the substrate at respective
angles within the range of approximately 60 degrees to
approximately 70 degrees.
22. A pixel cell comprising: a substrate having a top surface; a
pinned photodiode having a doped surface layer of a first
conductivity type; a trench formed in the substrate adjacent the
pinned photodiode, the trench having sidewalls angled from a plane
of a top surface of the substrate at respective angles within the
range of approximately 15 degrees to approximately 70 degrees; and
a doped well of the first conductivity type formed in the substrate
surrounding the trench and being connected to the doped surface
layer.
23. An image sensor comprising: a substrate having a top surface;
and an array of pixel cells, at least one pixel cell comprising: a
photo-conversion device at a surface of the substrate; and a trench
formed in the substrate adjacent to the photo-conversion device,
the trench having side walls, at least one sidewall on a side of
the photo-conversion device being angled less than approximately 85
degrees from a plane of a top surface of the substrate.
24. The image sensor of claim 23, wherein the trench is formed to a
depth of approximately 500 .ANG. to approximately 5000 .ANG..
25. The image sensor of claim 24, wherein the trench is formed to a
depth of approximately 1000 .ANG. to approximately 3000 .ANG..
26. The image sensor of claim 23, wherein the at least one angled
side wall has an angle within the range of approximately 15 degrees
to approximately 70 degrees with respect to the plane.
27. The image sensor of claim 23, wherein the at least one angled
side wall has an angle within the range of approximately 60 degrees
to approximately 70 degrees with respect to the plane.
28. The image sensor of claim 23, further comprising a doped well
of a first conductivity type formed in the substrate surrounding
the trench.
29. The image sensor of claim 28, wherein the photo-conversion
device is a pinned photodiode comprising a doped surface layer of a
first conductivity type.
30. The image sensor of claim 29, wherein the doped surface layer
is connected to the doped well.
31. The image sensor of claim 23, wherein the photo-conversion
device is a p-n type photodiode.
32. The image sensor of claim 23, wherein the photo-conversion
device is a photoconductor.
33. The image sensor of claim 23, wherein the photo-conversion
device is a photogate.
34. The image sensor of claim 23, wherein the trench is lined with
nitride.
35. The image sensor of claim 34, wherein the trench is lined with
oxide.
36. The image sensor of claim 35, wherein the trench is filled with
a dielectric material and the nitride liner is between the
dielectric material and the oxide liner.
37. The image sensor of claim 23, wherein the trench is at least
partially filled with a dielectric material.
38. The image sensor of claim 23, wherein the image sensor is a
CMOS image sensor.
39. The image sensor of claim 23, wherein the image sensor is a
charge coupled device image sensor.
40. A processor-based system comprising: (i) a processor; and (ii)
an image sensor coupled to the processor, the image sensor
comprising: a substrate, an array of pixel cells, at least one of
the pixel cells comprising: a photo-conversion device; and a trench
formed in the substrate adjacent the photo-conversion device, the
trench having side walls, at least one sidewall on a side of the
photo-conversion device being angled less than approximately 85
degrees from a plane of a top surface of the substrate.
41. The processor-based system of claim 40, wherein the image
sensor is a CMOS image sensor.
42. The processor-based system of claim 40, wherein the image
sensor is a charge coupled device image sensor.
43. A method of forming a pixel cell, the method comprising the
acts of: forming a photo-conversion device at a surface of a
substrate; and forming a trench in the substrate adjacent the
photo-conversion device and having at least one sidewall on a side
of the photo-conversion device angled less than approximately 85
degrees from a plane of a top surface of the substrate.
44. The method of claim 43, wherein the trench is formed to a depth
of approximately 500 .ANG. to approximately 5000 .ANG..
45. The method of claim 44, wherein the trench is formed to a depth
of approximately 1000 .ANG. to approximately 3000 .ANG..
46. The method of claim 43, wherein the act of forming the trench
comprises forming the at least one angled sidewall at an angle
within the range of approximately 15 degrees to approximately 70
degrees with respect to the plane.
47. The method of claim 43, wherein the act of forming the trench
comprises forming the at least one angled sidewall at an angle
within the range of approximately 60 degrees to approximately 70
degrees with respect to the plane.
48. The method of claim 43, wherein the act of forming the trench
comprises forming each sidewall angled less than approximately 85
degrees with respect to the plane.
49. The method of claim 43, wherein the act of forming the trench
comprises: forming a first sidewall adjacent to photo-conversion
device and being angled less than approximately 85 degrees with
respect to the plane; and forming a second sidewall angled greater
than or equal to approximately 80 degrees with respect to the
plane.
50. The method of claim 43, further comprising forming a doped well
of a first conductivity type in the substrate surrounding the
trench.
51. The method of claim 50, wherein the act of forming the
photo-conversion device comprises forming a pinned photodiode
comprising a doped surface layer of a first conductivity type.
52. The method of claim 51, wherein the act of forming the
photo-conversion device comprises forming the doped surface layer
connected to the doped well.
53. The method of claim 43, wherein the act of forming the
photo-conversion device comprises forming a p-n type
photodiode.
54. The method of claim 43, wherein the act of forming the
photo-conversion device comprises forming a photoconductor.
55. The method of claim 43, wherein the act of forming the
photo-conversion device comprises forming a photogate.
56. The pixel cell of claim 29, further comprising forming a
nitride layer inside the trench.
57. The pixel cell of claim 56, further comprising forming an oxide
layer inside the trench.
58. The pixel cell of claim 57, further comprising filling the
trench with a dielectric material, and wherein the act of forming
the nitride liner comprises forming the nitride layer between the
oxide layer and the dielectric material.
59. The method of claim 43, further comprising at least partially
filling the trench with a dielectric material.
60. The method of claim 43, wherein the pixel cell is formed as
part of a CMOS image sensor.
61. The method of claim 43, wherein the pixel cell is formed as
part of a charge coupled device image sensor.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
devices, and more particularly, to trench isolation technology for
use in semiconductor devices, including CMOS image sensors.
BACKGROUND OF THE INVENTION
[0002] CMOS image sensors are increasingly being used as low cost
imaging devices. A CMOS image sensor circuit includes a focal plane
array of pixel cells, each one of the cells includes a photogate,
photoconductor, or photodiode having an associated charge
accumulation region within a substrate for accumulating
photo-generated charge. Each pixel cell may include a transistor
for transferring charge from the charge accumulation region to a
sensing node, and a transistor, for resetting the sensing node to a
predetermined charge level prior to charge transference. The pixel
cell may also include a source follower transistor for receiving
and amplifying charge from the sensing node and an access
transistor for controlling the readout of the cell contents from
the source follower transistor.
[0003] In a CMOS image sensor, the active elements of a pixel cell
perform the necessary functions of: (1) photon to charge
conversion; (2) accumulation of image charge; (3) transfer of
charge to the sensing node accompanied by charge amplification; (4)
resetting the sensing node to a known state before the transfer of
charge to it; (5) selection of a pixel for readout; and (6) output
and amplification of a signal representing pixel charge from the
sensing node.
[0004] CMOS image sensors of the type discussed above are generally
known as discussed, for example, in Nixon et al., "256.times.256
CMOS Active Pixel Sensor Camera-on-a-Chip," IEEE Journal of
Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis
et al., "CMOS Active Pixel Image Sensors," IEEE Transactions on
Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S.
Pat. Nos. 6,177,333 and 6,204,524, which describe the operation of
conventional CMOS image sensors and are assigned to Micron
Technology, Inc., the contents of which are incorporated herein by
reference.
[0005] A schematic diagram of a conventional CMOS pixel cell 10 is
shown in FIG. 1. The illustrated CMOS pixel cell 10 is a four
transistor (4T) cell. The CMOS pixel cell 10 generally comprises a
photo-conversion device 23 for generating and collecting charge
generated by light incident on the pixel cell 10, and a transfer
transistor 17 for transferring photoelectric charges from the
photo-conversion device 23 to a sensing node, typically a floating
diffusion region 5. The floating diffusion region 5 is electrically
connected to the gate of an output source follower transistor 19.
The pixel cell 10 also includes a reset transistor 16 for resetting
the floating diffusion region 5 to a predetermined voltage; and a
row select transistor 18 for outputting a signal from the source
follower transistor 19 to an output terminal in response to an
address signal.
[0006] FIG. 2 is a cross-sectional view of a portion of the pixel
cell 10 of FIG. 1 showing the photo-conversion device 23, transfer
transistor 17 and reset transistor 16. The exemplary CMOS pixel
cell 10 has a photo-conversion device 23 may be formed as a pinned
photodiode. The photodiode 23 has a p-n-p construction comprising a
p-type surface layer 22 and an n-type photodiode region 21 within a
p-type active layer 11. The photodiode 23 is adjacent to and
partially underneath the transfer transistor 17. The reset
transistor 16 is on a side of the transfer transistor 17 opposite
the photodiode 23. As shown in FIG. 2, the reset transistor 16
includes a source/drain region 2. The floating diffusion region 5
is between the transfer and reset transistors 17, 16.
[0007] In the CMOS pixel cell 10 depicted in FIGS. 1 and 2,
electrons are generated by light incident on the photo-conversion
device 23 and are stored in the n-type photodiode region 21. These
charges are transferred to the floating diffusion region 5 by the
transfer transistor 17 when the transfer transistor 17 is
activated. The source follower transistor 19 produces an output
signal from the transferred charges. A maximum output signal is
proportional to the number of electrons extracted from the n-type
photodiode region 21.
[0008] Conventionally, a shallow trench isolation (STI) region 3
adjacent to the charge collection region 21 is used to isolate the
pixel cell 10 from other pixel cells and devices of the image
sensor. The STI region 3 is typically formed using a conventional
STI process. The STI region 3 is typically lined with an oxide
liner 38 and filled with a dielectric material 37. Also, the STI
region 3 can include a nitride liner 39. The nitride liner 39
provides several benefits, including improved corner rounding near
the STI region 3 corners, reduced stress adjacent the STI region 3,
and reduced leakage for the transfer transistor 17.
[0009] The trench isolation region 3 is typically formed using a
conventional STI process. The STI region 3 is formed to a depth
between 2000 Angstroms (.ANG.) and 6000 .ANG.. The sidewalls 9 of
the STI region 3 are formed at an angle .theta.1, which is
typically between 85 degrees and 90 degrees. The STI region 3 is
typically filled with a dielectric material and can include a
nitride liner (not shown).
[0010] A common problem associated with the above described STI
region 3 is dangling bonds (e.g., dangling silicon (Si--) bonds) at
the surface of the substrate 11 and along the trench bottom 8 and
sidewalls 9. The dangling bonds create a high density of trap sites
along the trench bottom 8 and sidewalls 9. As a result of these
trap sites formed along the bottom 8 and sidewalls 9 of the STI
region 3, current generation near and along the trench bottom 8 and
sidewalls 9 can be significant. Current generated from trap sites
inside or near the photodiode 23 depletion region causes undesired
dark current and increased fixed pattern noise.
[0011] Additionally, while the nitride liner 39 provides certain
benefits, it also has undesirable effects. The portion of the
transfer transistor 17 gate that overlaps the STI region 3 (not
shown) can undesirably act as a second transistor with a threshold
voltage "field Vt" causing current leakage. Without the nitride
liner 39, the field Vt is typically approximately 15 volts (V),
which is sufficiently high to minimize leakage. With the nitride
liner 39, as shown in FIG. 2, the field Vt is lowered, causing
increased leakage. It is believed that the decreased field Vt is
due to fixed charge or surface states from the nitride liner
39.
[0012] Further, for proper operation of the pinned photodiode 23,
the p-type surface implant region 22 must be continuously to the
p-type substrate 11. FIG. 2 illustrates this as link region 25.
Accordingly, a continuous p-type region from p-type surface layer
22 through link region 25 to the p-type substrate 11 must be
established for the pinned photodiode 23 to work properly. In
situations where this does not occur, e.g., where the link region
25 becomes depleted, the p-type surface region 22 becomes isolated
from the p-type substrate 11 and results in a floating p-type
surface region 22 rather a pinned region 22. This results in a
dramatic capacitance loss in the pinned photodiode 23 and
therefore, decreased image sensor performance.
[0013] It is desirable to have an improved isolation structure for
reducing dark current and fixed pattern noise. It is also desirable
to have an isolation structure that allows a better connection
between the p-type surface region of a pinned photodiode and the
substrate.
BRIEF SUMMARY OF THE INVENTION
[0014] Exemplary embodiments of the invention provide a pixel cell
comprising a substrate having a top surface. A photo-conversion
device is at a surface of the substrate and a trench is in the
substrate adjacent the photo-conversion device. The trench has
sidewalls and a bottom. At least one sidewall is angled less than
approximately 85 degrees from the plane of the top surface of the
substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The foregoing and other aspects of the invention will be
better understood from the following detailed description of the
invention, which is provided in connection with the accompanying
drawings, in which:
[0016] FIG. 1 is a schematic diagram of a conventional pixel
cell;
[0017] FIG. 2 is a cross-sectional view of a conventional pixel
cell;
[0018] FIG. 3 is a cross-sectional view of a pixel cell according
to an exemplary embodiment of the invention;
[0019] FIG. 4A depicts the pixel cell of FIG. 2 at an initial stage
of processing;
[0020] FIGS. 4B-4J depict the pixel cell of FIG. 2 at intermediate
stages of processing;
[0021] FIG. 5 is a cross-sectional view of a pixel cell according
to another exemplary embodiment of the invention;
[0022] FIG. 6 is a block diagram of a CMOS image sensor according
to an exemplary embodiment of the invention; and
[0023] FIG. 7 is a schematic diagram of a computer processor system
incorporating the CMOS image sensor of FIG. 5.
DETAILED DESCRIPTION OF THE INVENTION
[0024] In the following detailed description, reference is made to
the accompanying drawings, which form a part hereof and illustrate
specific embodiments in which the invention may be practiced. In
the drawings, like reference numerals describe substantially
similar components throughout the several views. These embodiments
are described in sufficient detail to enable those skilled in the
art to practice the invention, and it is to be understood that
other embodiments may be utilized, and that structural, logical and
electrical changes may be made without departing from the spirit
and scope of the present invention.
[0025] The terms "wafer" and "substrate" are to be understood as
including silicon, silicon-on-insulator (SOI), silicon-on-sapphire
(SOS), and silicon-on-nothing (SON) technology, doped and undoped
semiconductors, epitaxial layers of silicon supported by a base
semiconductor foundation, and other semiconductor structures.
Furthermore, when reference is made to a "wafer" or "substrate" in
the following description, previous process steps may have been
utilized to form regions or junctions in the base semiconductor
structure or foundation. In addition, the semiconductor need not be
silicon-based, but could be based on silicon-germanium, germanium,
or gallium-arsenide.
[0026] The term "pixel" or "pixel cell" refers to a picture element
unit cell containing a photo-conversion device and transistors for
converting electromagnetic radiation to an electrical signal. For
purposes of illustration, a portion of a representative pixel cell
is illustrated in the figures and description herein, and typically
fabrication of all pixel cells in an image sensor will proceed
concurrently and in a similar fashion.
[0027] FIG. 3 is a cross-sectional view of a pixel cell 300
according to an exemplary embodiment of the invention. The pixel
cell 300 is similar to the pixel cell 10 depicted in FIGS. 1 and 2,
except that the pixel cell 300 includes an improved trench
isolation region 333 rather than a conventional STI region 3 (FIG.
2). Also, the pixel cell 300 may include a p-type well 334
surrounding and below the isolation region 333 and a p-type well
335 below the floating diffusion region 5, the reset transistor 16,
and a portion of the transfer transistor 17. Although not shown in
FIG. 3, the pixel cell 300 also includes source follower and row
select transistors 19, 18, respectively (as shown in FIG. 1).
[0028] The illustrated isolation region 333 has a unique trench
geometry for use adjacent a photo-conversion device, e.g.,
photodiode 23. The isolation region 333 is formed such that its
sidewalls 336a, 336b are at angles .theta.3, .theta.2,
respectively, from the plane of the top surface of the substrate
11. The angles .theta.2, .theta.3 are less than approximately 85
degrees. Preferably, the angles .theta.2, .theta.3 are within the
range of approximately 15 degrees to approximately 70 degrees, and
more preferably are within the range of approximately 60 degrees to
approximately 70 degrees. In the illustrated embodiment, the first
angle .theta.2 is approximately equal to the second angle .theta.3,
but the angles .theta.2, .theta.3 can be different from each other.
Preferably, the isolation region 333 has a depth D2 within the
range of approximately 500 Angstroms (.ANG.) to approximately 5000
.ANG., and more preferably within the range of approximately 1000
.ANG. to approximately 3000 .ANG..
[0029] The angles .theta.2, .theta.3, depth D2, surface width W2,
and bottom width X2 are configured to minimize the substrate 11
surface area used by the isolation region 333. For example, the
angles .theta.3, .theta.2 of the isolation region 333 sidewalls
336a, 336b are shallow as compared to the angles .theta.1 of the
conventional STI region 3 sidewall 9 (FIG. 2). In accordance with
basic geometry, at a same surface width W1=W2, and a same depth
D1=D2, the total length of the bottom width plus the sidewalls,
X2+336a+336b, of the isolation region 333 will be less than that of
the STI region 3 (FIG. 2), X1+9+9. That is, the isolation region
333 will occupy less surface area of the substrate 11 than does the
conventional STI region 3, and therefore, will have fewer dangling
bonds than the conventional STI region 3.
[0030] By minimizing the substrate 11 surface area and the dangling
bonds, the effects of the dangling bonds are also minimized.
Additionally, the reduced substrate 11 surface area results in less
nitride liner being required in the isolation region 333 and,
therefore, an increased field Vt as compared to the conventional
pixel cell 10 (FIGS. 1 and 2). Further, because of the shallow
second angle .theta.3, the sidewall 336a, and the isolation region
333, are a greater distance from the photodiode 23 than when a
steeper angle, e.g., angle .theta.1 (FIG. 2) is used. By maximizing
the distance between the photodiode 23 and the sidewall 336a and
the isolation region 333, less charge from the sidewall 336a will
drift into the photodiode 23, thereby reducing pixel noise and
bright signal bits and providing an increased region for linking
the p-type surface layer 22 of the photodiode 23 with the p-well
334.
[0031] Also, the isolation region 333 can reduce cross-talk. A
certain amount of light incident on the interfaces of the materials
within the isolation region 333 and the substrate 11 are reflected
according to the laws of reflection. As the angles .theta.2,
.theta.3 decrease, light passing through the photodiode 23 will
tend to be reflected more toward the substrate 11, rather than
toward neighboring pixel cells (not shown). This is one more
advantage of the invention.
[0032] FIGS. 4A-4J depict the formation of pixel cell 300 according
to an exemplary embodiment of the invention. No particular order is
required for any of the actions described herein, except for those
logically requiring the results of prior actions. Accordingly,
while the actions below are described as being performed in a
general order, the order is exemplary only and can be altered if
desired.
[0033] As illustrated in FIG. 4A, a pad oxide layer 441, which can
be a thermally grown oxide, is formed on the substrate 11. A
sacrificial layer 442 is formed on the pad oxide layer 441. The
sacrificial layer 442 can be a nitride or dielectric
anti-reflective coating (DARC) layer.
[0034] FIG. 4B depicts the formation of a trench 430 in the
substrate 11 and through the layers 441, 442 on the substrate 11.
The trench 430 is formed such that the sidewalls 336a, 336b are at
angles .theta.3, .theta.2, respectively, from the plane 432 of the
top surface of the substrate 11. The angles .theta.2, .theta.3 are
within the range of approximately 15 degrees to approximately 85
degrees. In the illustrated embodiment of FIG. 4C, the first angle
.theta.2 is approximately equal to the second angle .theta.3. The
trench 430 is formed having a depth within the range of
approximately 500 .ANG. to approximately 5000 .ANG., and preferably
within the range of approximately 1000 .ANG. to approximately 3000
.ANG..
[0035] The trench 430 can be formed by any known technique. For
example, a patterned photoresist layer (not shown) is used as a
mask for an etching process. The first etch is conducted utilizing
dry plasma conditions and difloromethane/carbon tetrafluoride
(CH2F2/CF4) chemistry. Such etching effectively etches both silicon
nitride layer 442 and pad oxide layer 441 to form an opening
extending therethrough and stops upon reaching the substrate 11. A
second etch is conducted to extend the openings into the substrate
11. The second etch is a dry plasma etch utilizing
difloromethane/hydrogen bromide (CH2F2/HBr) chemistry. The timing
of the etch is adjusted to form the trench 430 within substrate 11
to the desired depth. A shorter etch time results in a shallower
trench 430. The photoresist mask (not shown) is removed using
standard photoresist stripping techniques, preferably by a plasma
etch.
[0036] A thin insulator layer 338, between approximately 50 .ANG.
and approximately 250 .ANG. thick, is formed on the trench 430
sidewalls 336a, 336b and bottom 308, as shown in FIG. 4C. In the
embodiment depicted in FIG. 4C, the insulator layer 338 is an oxide
layer 338 is preferably grown by thermal oxidization.
[0037] The trench 430 can be lined with a barrier film 339. In the
embodiment shown in FIG. 4C, the barrier film 339 is a nitride
liner, for example, silicon nitride. The nitride liner 339 is
formed by any suitable technique, to a thickness within the range
of approximately 50 .ANG. to approximately 250 .ANG.. For example,
as is known in the art, a silicon nitride liner 339 can be
deposited using ammonia (NH.sub.3) and silane (SiH.sub.4).
[0038] The trench 430 is filled with a dielectric material 337 as
shown in FIG. 4D. The dielectric material 337 may be an oxide
material, for example a silicon oxide, such as SiO or silicon
dioxide (SiO.sub.2); oxynitride; a nitride material, such as
silicon nitride; silicon carbide; a high temperature polymer; or
other suitable dielectric material. In the illustrated embodiment,
the dielectric material 337 is a high density plasma (HDP)
oxide.
[0039] A chemical mechanical polish (CMP) step is conducted to
remove the nitride layer 339 over the surface of the substrate 11
outside the trench 430 and the nitride layer 442, as shown in FIG.
4E. Also, the pad oxide layer 441 is removed, for example, using a
field wet buffered-oxide etch step and a clean step.
[0040] FIG. 4F depicts the formation of the transfer transistor 17
(FIG. 3) gate stack 407 and the reset transistor 16 (FIG. 3) gate
stack 406. Although not shown, the source follower and row select
transistors 19, 18 (FIG. 1), respectively, can be formed
concurrently with the transfer and reset transistors 17, 16 as
described below.
[0041] To form the transistor gate stacks 407, 406 as shown in FIG.
4F, a first insulating layer 401a of, for example, silicon oxide is
grown or deposited on the substrate 11. The first insulating layer
401a serves as the gate oxide layer for the subsequently formed
transistor gate 401b. Next, a layer of conductive material 401b is
deposited over the oxide layer 401a. The conductive layer 401b
serves as the gate electrode for the transistors 17, 16 (FIG. 3).
The conductive layer 401b may be a layer of polysilicon, which may
be doped to a second conductivity type, e.g., n-type. A second
insulating layer 401c is deposited over the conductive layer 401b.
The second insulating layer 401c may be formed of, for example, an
oxide (SiO.sub.2), a nitride (silicon nitride), an oxynitride
(silicon oxynitride), ON (oxide-nitride), NO (nitride-oxide), or
ONO (oxide-nitride-oxide).
[0042] The gate stack layers 401a, 401b, 401c may be formed by
conventional deposition methods, such as chemical vapor deposition
(CVD) or plasma enhanced chemical vapor deposition (PECVD), among
others. The layers 401a, 401b, 401c are then patterned and etched
to form the multilayer gate stacks 407, 406 shown in FIG. 4F.
[0043] The invention is not limited to the structure of the gate
stacks 407, 406 described above. Additional layers may be added or
the gate stacks 407, 406 may be altered as is desired and known in
the art. For example, a silicide layer (not shown) may be formed
between the gate electrodes 401b and the second insulating layers
401c. The silicide layer may be included in the gate stacks 407,
406, or in all of the transistor gate stack structures in an image
sensor circuit, and may be titanium silicide, tungsten silicide,
cobalt silicide, molybdenum silicide, or tantalum silicide. This
additional conductive layer may also be a barrier layer/refractor
metal, such as titanium nitride/tungsten (TiN/W) or tungsten
nitride/tungsten (WN.sub.x/W), or it could be formed entirely of
tungsten nitride (WN.sub.x).
[0044] Doped p-type wells 334, 335 are implanted into the substrate
11 as shown in FIG. 4G. The first p-well 334 is formed in the
substrate 11 surrounding the isolation region 333 and extending
below the isolation region 333. The second p-well 335 is formed in
the substrate 11 from a point below the transfer gate stack 407
extending in a direction in the substrate 11 away from where the
photodiode 23 (FIG. 3) is to be formed.
[0045] The p-wells 334, 335 are formed by known methods. For
example, a layer of photoresist (not shown) can be patterned over
the substrate 11 having an opening over the area where the p-wells,
334, 335 are to be formed. A p-type dopant, such as boron, can be
implanted into the substrate 11 through the opening in the
photoresist. The p-wells 334, 335 are formed having a p-type dopant
concentration that is higher than adjacent portions of the
substrate 11. Alternatively, the p-wells 334, 335 can be formed
prior to the formation of the trench 430.
[0046] As depicted in FIG. 4H, a doped n-type region 21 is
implanted in the substrate 11 (for the photodiode 23 of FIG. 3).
For example, a layer of photoresist (not shown) may be patterned
over the substrate 11 having an opening over the surface of the
substrate 11 where photodiode 23 (FIG. 3) is to be formed. An
n-type dopant, such as phosphorus, arsenic, or antimony, may be
implanted through the opening and into the substrate 11. Multiple
implants may be used to tailor the profile of region 21. If
desired, an angled implantation may be conducted to form the doped
region 21, such that implantation is carried out at angles other
than 90 degrees relative to the surface of the substrate 11.
[0047] As shown in FIG. 4H, the n-type region 21 is formed from a
point adjacent the transfer gate stack 407 and extending in the
substrate 11 between the gate stack 407 and the isolation region
333. The region 21 forms a photosensitive charge accumulating
region for collecting photo-generated charge.
[0048] The floating diffusion region 5 and source/drain region 2
are implanted by known methods to achieve the structure shown in
FIG. 4H. The floating diffusion region 5 and source/drain region 2
are formed as n-type regions. Any suitable n-type dopant, such as
phosphorus, arsenic, or antimony, may be used. The floating
diffusion region 5 is formed on the side of the transfer gate stack
407 opposite the n-type photodiode region 21. The source/drain
region 2 is formed on a side of the reset gate stack 406 opposite
the floating diffusion region 5.
[0049] FIG. 4I depicts the formation of a dielectric layer 307.
Illustratively, layer 307 is an oxide layer, but layer 307 may be
any appropriate dielectric material, such as silicon dioxide,
silicon nitride, an oxynitride, or tetraethyl orthosilicate (TEOS),
among others, formed by methods known in the art.
[0050] The doped surface layer 22 for the photodiode 23 is
implanted, as illustrated in FIG. 4J. Doped surface layer 22 is
formed as a highly doped p-type surface layer and is formed to a
depth of approximately 0.1 .mu.m. A p-type dopant, such as boron,
indium, or any other suitable p-type dopant, may be used to form
the p-type surface layer 22.
[0051] The p-type surface layer 22 may be formed by known
techniques. For example, layer 22 may be formed by implanting
p-type ions through openings in a layer of photoresist.
Alternatively, layer 22 may be formed by a gas source plasma doping
process, or by diffusing a p-type dopant into the substrate 11 from
an in-situ doped layer or a doped oxide layer deposited over the
area where layer 22 is to be formed.
[0052] The oxide layer 307 is etched such that remaining portions
form a sidewall spacer on a sidewall of the reset gate stack 406.
The layer 307 remains over the transfer gate stack 407, the
photodiode 23, the floating diffusion region 5, and a portion of
the reset gate stack 406 to achieve the structure shown in FIG. 3.
Alternatively, a dry etch step can be conducted to etch portions of
the oxide layer 307 such that only sidewall spacers (not shown)
remain on the transfer gate stack 407 and the reset gate stack
406.
[0053] Conventional processing methods can be used to form other
structures of the pixel 300. For example, insulating, shielding,
and metallization layers to connect gate lines, and other
connections to the pixel 300 may be formed. Also, the entire
surface may be covered with a passivation layer (not shown) of, for
example, silicon dioxide, borosilicate glass (BSG), phosphosilicate
glass (PSG), or borophosphosilicate glass (BPSG), which is CMP
planarized and etched to provide contact holes, which are then
metallized to provide contacts. Conventional layers of conductors
and insulators may also be used to interconnect the structures and
to connect pixel 300 to peripheral circuitry.
[0054] FIG. 5 depicts a pixel cell 500 according to another
embodiment of the invention. The pixel cell 500 is similar to the
pixel cell 300 (FIG. 3) except that isolation region 333 sidewall
336b is at a steep conventional angle .theta.1 from the plane of
the top surface of the substrate 11, rather than the first angle
.theta.2 (FIG. 3). In the illustrated embodiment, the conventional
angle .theta.1 is between approximately 85 degrees and
approximately 90 degrees. The pixel cell 500 can be formed as
described above in connection with FIGS. 4A-4J, but with additional
processing steps to form the sidewall 336b at the conventional
angle .theta.1.
[0055] While the above embodiments are described in connection with
the formation of p-n-p-type photodiodes the invention is not
limited to these embodiments. The invention also has applicability
to other types of photo-conversion devices, such as a photodiode
formed from n-p or n-p-n regions in a substrate, a photogate, or a
photoconductor. If an n-p-n-type photodiode is formed the dopant
and conductivity types of all structures would change
accordingly.
[0056] Although the above embodiments are described in connection
with 4T pixel cells 300, 500, the configuration of pixel cells,
300, 500 is only exemplary and the invention may also be
incorporated into other pixel circuits having different numbers of
transistors. Without being limiting, such a circuit may include a
three-transistor (3T) pixel cell, a five-transistor (5T) pixel
cell, a six-transistor (6T) pixel cell, and a seven-transistor
pixel cell (7T). A 3T cell omits the transfer transistor, but may
have a reset transistor adjacent to a photodiode. The 5T, 6T, and
7T pixel cells differ from the 4T pixel cell by the addition of
one, two, or three transistors, respectively, such as a shutter
transistor, a CMOS photogate transistor, and an anti-blooming
transistor. Further, while the above embodiments are described in
connection with CMOS pixel cells 300, 500, the invention is also
applicable to pixel cells in a charge coupled device (CCD) image
sensor.
[0057] A typical single chip CMOS image sensor 600 is illustrated
by the block diagram of FIG. 6. The image sensor 600 includes a
pixel cell array 680 having one or more pixel cells 300 (FIG. 3) or
500 (FIG. 5) described above. The pixel cells of array 680 are
arranged in a predetermined number of columns and rows.
[0058] The rows of pixel cells in array 680 are read out one by
one. Accordingly, pixel cells in a row of array 680 are all
selected for readout at the same time by a row select line, and
each pixel cell in a selected row provides a signal representative
of received light to a readout line for its column. In the array
680, each column also has a select line, and the pixel cells of
each column are selectively read out in response to the column
select lines.
[0059] The row lines in the array 680 are selectively activated by
a row driver 682 in response to row address decoder 681. The column
select lines are selectively activated by a column driver 684 in
response to column address decoder 685. The array 680 is operated
by the timing and control circuit 683, which controls address
decoders 681, 685 for selecting the appropriate row and column
lines for pixel signal readout.
[0060] The signals on the column readout lines typically include a
pixel reset signal (V.sub.rst) and a pixel image signal
(V.sub.photo) for each pixel cell. Both signals are read into a
sample and hold circuit (S/H) 686 in response to the column driver
684. A differential signal (V.sub.rst-V.sub.photo) is produced by
differential amplifier (AMP) 687 for each pixel cell, and each
pixel cell's differential signal is digitized by analog-to-digital
converter (ADC) 688. The analog-to-digital converter 688 supplies
the digitized pixel signals to an image processor 689, which
performs appropriate image processing before providing digital
signals defining an image output.
[0061] FIG. 7 illustrates a processor-based system 700 including
the image sensor 600 of FIG. 6. The processor-based system 700 is
exemplary of a system having digital circuits that could include
image sensor devices. Without being limiting, such a system could
include a computer system, camera system, scanner, machine vision,
vehicle navigation, video phone, surveillance system, auto focus
system, star tracker system, motion detection system, and other
systems requiring image acquisition.
[0062] The processor-based system 700, for example a camera system,
generally comprises a central processing unit (CPU) 795, such as a
microprocessor, that communicates with an input/output (I/O) device
791 over a bus 793. Image sensor 600 also communicates with the CPU
795 over bus 793. The processor-based system 700 also includes
random access memory (RAM) 792, and can include removable memory
794, such as flash memory, which also communicate with CPU 795 over
the bus 793. Image sensor 600 may be combined with a processor,
such as a CPU, digital signal processor, or microprocessor, with or
without memory storage on a single integrated circuit or on a
different chip than the processor.
[0063] It is again noted that the above description and drawings
are exemplary and illustrate preferred embodiments that achieve the
objects, features and advantages of the present invention. It is
not intended that the present invention be limited to the
illustrated embodiments. Any modification of the present invention
which comes within the spirit and scope of the following claims
should be considered part of the present invention.
* * * * *