U.S. patent application number 10/928057 was filed with the patent office on 2005-11-24 for thin layer semi-conductor structure comprising a heat distribution layer.
Invention is credited to Bruel, Michel, Jaussaud, Claude, Joly, Jean-Pierre.
Application Number | 20050258489 10/928057 |
Document ID | / |
Family ID | 26234440 |
Filed Date | 2005-11-24 |
United States Patent
Application |
20050258489 |
Kind Code |
A9 |
Joly, Jean-Pierre ; et
al. |
November 24, 2005 |
Thin layer semi-conductor structure comprising a heat distribution
layer
Abstract
The invention concerns a thin layer semi-conductor structure
including a semi-conductor surface layer (2) separated from a
support substrate (1) by an intermediate zone (3), the intermediate
zone (3) being a multi-layer electrically insulating the
semi-conductor surface layer from the support substrate. The
intermediate zone has a considered sufficiently good electrical
quality of interface with the semi-conductor surface layer and
includes at least one first layer, of satisfactory thermal
conductivity to provide a considered as correct operation of the
electronic device or devices which are to be elaborated from the
semi-conductor surface layer (2), the intermediate zone including
additionally a second insulating layer of low dielectric constant,
located between the first layer and the support substrate.
Inventors: |
Joly, Jean-Pierre; (Saint
Egreve, FR) ; Bruel, Michel; (Veurey, FR) ;
Jaussaud, Claude; (Meylan, FR) |
Correspondence
Address: |
HUTCHISON & MASON PLLC
PO BOX 31686
RALEIGH
NC
27612
US
|
Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 0029594 A1 |
February 10, 2005 |
|
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Family ID: |
26234440 |
Appl. No.: |
10/928057 |
Filed: |
June 2, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10928057 |
Jun 2, 2004 |
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10093889 |
Mar 11, 2002 |
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10093889 |
Mar 11, 2002 |
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09720672 |
Dec 29, 2000 |
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09720672 |
Dec 29, 2000 |
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PCT/FR99/01659 |
Jul 8, 1999 |
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Current U.S.
Class: |
257/349 ;
257/347; 257/E21.567; 257/E23.106 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 23/3735 20130101; H01L 2924/00
20130101; H01L 21/76251 20130101 |
Class at
Publication: |
257/349 ;
257/347 |
International
Class: |
H01L 027/01; H01L
031/0392; H01L 027/12 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 10, 1998 |
FR |
98 08919 |
Claims
1.-18. (canceled)
19. A thin layer semi-conductor structure including a
semi-conductor surface layer separated from a support substrate by
an intermediate zone, the intermediate zone being a multi-layer
electrically insulating the semi-conductor surface layer from the
support substrate, providing an electrical quality of interface
with the semi-conductor surface layer and including a first layer
providing the thermal conductivity between the semi-conductor
surface layer and the support substrate, the intermediate zone
including additionally a second layer located between the first
layer and the support substrate, the second layer being of an
electric insulating material, of low dielectric constant and
providing bonding by molecular adhesion between the intermediate
zone and the support substrate, the thickness of the first layer
being chosen as a function of the dimension of the thermal
dissipation zones of the electronic device or devices which are to
be made from the semi-conductor surface layer.
20. A semi-conductor structure according to claim 19, wherein the
second layer provides adhesion between the intermediate zone and
the support substrate.
21. A semi-conductor structure according to claim 19, wherein the
intermediate zone includes a third, electrical insulating, layer
between the first layer and the semi-conductor surface layer, said
third-layer providing to the intermediate zone said electrical
quality of interface.
22. A semi-conductor structure according to claim 21, wherein, the
semi-conductor structure being an SOI structure, the third layer is
a layer of silicon oxide.
23. A semi-conductor structure according to claim 22, wherein the
third layer is a layer of thermal silicon oxide.
24. A semi-conductor structure according to claim 19, the
semiconductor structure being an SOI structure, wherein the second
layer is a layer of silicon oxide.
25. A semi-conductor structure according to claim 19, wherein the
first layer is constituted by a material chosen from among
polycrystalline silicon, diamond, alumina, silicon nitride,
aluminum nitride, boron nitride and silicon carbide.
26. A semi-conductor structure according to claim 19, wherein the
first layer is in contact with the semi-conductor surface layer and
provides said electrical quality of interface.
27. A semi-conductor structure according to claim 26, wherein the
semi-conductor structure being an SOI structure, said first layer
is a layer of cubic silicon carbide.
28. A process for manufacturing a semi-conductor structure
according to claim 19, including the following stages: manufacture
of the layers of the intermediate zone on one face of a first
substrate intended to supply said semi-conductor surface layer
and/or on one face of a second substrate intended to supply the
support substrate of the structure, bonding of the first substrate
on the second substrate, said faces being placed opposite each
other, making of said semi-conductor surface layer.
29. A process according to claim 28, wherein making said
semi-conductor surface layer includes reducing the thickness of the
first substrate.
30. A process according to claim 28, wherein bonding the first
substrate onto the second substrate is achieved by molecular
adhesion.
31. A process according to claim 30, wherein the manufacturing
stage of the layers of the intermediate zone includes the
deposition of at least one bonding layer to allow bonding by
molecular adhesion.
32. A process according to claim 31, wherein said bonding layer is
a silicon oxide layer.
33. A process according to claim 28, wherein the first layer is a
layer of a material chosen from among polycrystalline silicon
deposited by LPCVD, diamond deposited by PECVD, alumina deposited
by reactive cathode sputtering, silicon nitride deposited by CVD,
aluminum nitride deposited by CVD, boron nitride deposited by CVD
and silicon carbide deposited by CVD.
34. A process according to claim 29, wherein the reduction in the
thickness of the first substrate is obtained by using one or more
technologies from among: rectification, chemical etching,
polishing, separation following thermal treatment along a cleavage
plane induced by ion implantation.
Description
TECHNICAL FIELD
[0001] The present invention concerns a thin layer semi-conductor
structure and processes for embodying such a structure.
[0002] By thin layer semi-conductor structure is understood a
structure having on the surface a fine semi-conductor layer in
which will be manufactured electronic devices (this layer is called
an active layer) and a substrate performing a mechanical support
role. This substrate is generally electrically insulated form the
surface layer. The substrate is constituted either from a solid
insulating material (a dielectric in the case of the SOS), or from
a conductor or semi-conductor material. In this latter case, it may
be of the same material as that of the surface layer (the case of
SOI), generally insulated form the surface layer by an insulation
layer. In the case of the SOI, the mechanical substrate is usually
constituted by a silicon substrate with a layer of silica on the
surface, but it may also be constituted by a solid substrate of
fused silica (silicon on quartz). Other thin layer semi-conductor
structures are also known like the AsGa on silicon, the SiC on
silicon or the GaN on sapphire etc. These structures are made
either by technologies known as "Wafer Bonding", or by
heteroepitaxy.
STATE OF THE PRIOR ART
[0003] Thin layer semi-conductor structures like for example SOI
structures are increasingly used to make electronic devices. SOI
structures are used in particular to manufacture VLSI logic and
analogue circuits or to manufacture power components. An SOI
structure (or substrate) has several advantages relative to a solid
silicon substrate. One of these advantages is that the insulant
subjacent to the silicon layer makes it possible to reduce the
stray capacitance of devices elaborated in the silicon layer, and
all the more so the thicker this insulant is.
[0004] A now conventional process for making an SOI substrate is
the SIMOX (Separation by IMplanted OXygen) process. According to
this process, the insulant is a buried silicon oxide SiO.sub.2
layer obtained by uniform implantation of oxygen in a silicon
substrate. This technology is now being challenged by other
processes of the type known as "Wafer Bonding" in the
English-speaking world, (and which will be denoted hereinafter by
the term molecular adhesion), for example the BSOI process
(described by J. HAISMA et al., in Jap. J. Appl. Phys., vol. 28,
page L 725, 1989) or the UNIBOND process (described by M. BRUEL in
Electron. Lett., vol. 31, page 1201, 1995).
[0005] SIMOX technology is still widely used. It is based on an
implantation of a very high dose of oxygen. It allows the
manufacture of buried layers of silicon only for thicknesses of
between 100 and 400 nm. The major drawback of this technology is
its cost due to the high dose ion implantation, and the need to
resort to non standard micro-electronic equipment. Technologies of
the molecular adhesion type do not have this drawback and make it
possible additionally, in principle, to modulate the thicknesses of
layers and the nature of the material constituting the insulant.
The UNIBOND process additionally makes possible a lower cost and a
better homogeneity of the silicon layer.
[0006] All current SOI substrates use the amorphous silica SiO2 as
the base material for the buried insulating layer. This material is
a good insulant, is easy to manufacture and gives very good
interfaces with the silicon since it has few fixed charges and
interface states. It has moreover a low dielectric constant, which
is a favourable factor for the rapidity of the components because
of the reduction in stray capacitance.
[0007] Silica has however one great drawback: its very low thermal
conductivity which is of the order of 0.2 W.m.sup.-1.K.sup.-1. This
causes a substantial transitory and localised temperature rise,
altogether problematic for the proper operation of the components.
One way of reducing this rise in temperature is to reduce the
thickness of the buried silica layer. However, the drawbacks of
this reduction in thickness are that on the one hand stray
capacitance is increased (thereby reducing the rapidity of the
components) and, on the other hand, electrical strength is reduced.
Furthermore, the reduction in thickness of the insulating layer is
not easy to obtain in the implementation of processes of the
molecular adhesion type where a good quality of adhesion is
obtained much more easily with layers of thickness exceeding 300
nm.
[0008] The idea has therefore been conceived of replacing the
silica by another insulating material having better thermal
conductivity. Reference may be made on this subject to the
documents EP-A-0 707 338, EP-A-0 570 321, EP-A-0 317 445 and
WO-A-91/11822. The materials proposed (for example diamond) do not
have a good interface with silicon from the electrical point of
view. For this reason, a thin layer of silica is added so as to
achieve the interface with the surface silicon. These solutions are
certainly effective from the thermal point of view, but they are
not easily applicable in association with the technologies of
bonding by molecular adhesion. It is indeed extremely difficult to
bond materials of high thermal conductivity as conceived.
[0009] There are also structures of the SiC type on silicon or AsGa
on silicon with generally an intermediate insulating layer. These
structures are often used to make super high frequency power
components. Because of this, heat dissipation in the component is
substantial and the thermal conductivity of the silicon and/or of
the dielectrics used is insufficient to provide a junction
temperature which is not crippling.
DISCLOSURE OF THE INVENTION
[0010] To overcome this problem, there is proposed, according to
the present invention, a thin layer semi-conductor structure having
several layers between the semi-conductor surface layer, from which
the electronic components will be elaborated, and the support
substrate so as to decouple the functions of thermal conductivity
and electrical insulation. This decoupling makes it possible to
optimise, through a choice of appropriate materials these two
functions, it being well understood that these materials must also
allow a good interface quality (mechanical strength). The material
in contact with the semi-conductor layer must additionally have a
good quality electrical interface. Thus, the layer in contact with
the semi-conductor surface layer may be made by means of an
insulating layer offering good electrical insulation and a good
electrical interface quality. A layer of a material having thermal
conductivity is used to overcome the problem of temperature rise
produced by the electronic components. Another layer may be used to
provide the quality connection with the support substrate if the
layer of good thermal conductivity does not allow it. It may be of
low thermal conductivity. If this layer is insulating, its role may
also be to maintain sufficient thickness of insulant of low
permittivity under the semi-conductor surface layer in order to
retain low stray capacitance for the electronic components and to
allow ease of bonding when using molecular adhesion technology.
[0011] An object of the invention is therefore a thin layer
semi-conductor structure including a semi-conductor surface layer
separated from a support substrate by an intermediate zone, the
intermediate zone being a multi-layer electrically insulating the
semi-conductor surface layer from the support substrate, having an
electrical quality of interface considered as sufficiently good
with the semi-conductor surface layer and including at least one
first layer, of satisfactory thermal conductivity to provide an
operation considered as correct of the electronic device or devices
which are to be elaborated from the semi-conductor surface layer,
characterised in that the intermediate zone additionally includes a
second insulating layer of low dielectric constant, located between
the first layer and the support substrate.
[0012] Advantageously, the thickness of the first layer is selected
as a function of the dimension of the zones of heat dissipation of
the electronic devices. By way of example, as thickness for the
first layer will be chosen advantageously a thickness which is of
the same order of magnitude or greater than the dimension of the
largest zone of thermal dissipation. In the event of a third layer
being used, it must be as thin as possible so as to optimise the
role of the first layer.
[0013] The second layer must be able to provide adhesion considered
as satisfactory between the intermediate zone and the support
substrate. By good adhesion is understood a mechanical adhesion
with as few macroscopic defects (i.e. localised adhesion failures)
as possible.
[0014] The intermediate zone may include a third layer, insulating
between the first layer and the semi-conductor surface layer, said
third layer conferring on the intermediate zone said electrical
quality of interface. If the semi-conductor structure is an SOI
structure, the third layer is advantageously a layer of silicon
oxide obtained for example by thermal oxidation.
[0015] If the semi-conductor structure is an SOI structure, the
second layer may be a layer of silicon oxide.
[0016] The first layer is able not to be insulating. Its thickness
is adjusted as a function of the heat generation zones in the
semi-conductor layer. It may particularly be multi-layer.
[0017] More exactly, for the layer of good thermal conductivity to
play its role effectively in diffusing the heat generated in the
components, its thickness will have to be sufficient. Conversely,
the thickness of possible intermediate layers of relatively low
thermal conductivity between this layer and the semi-conductor
layer will have to be minimised. In practice, the respective
thicknesses of these layers necessary for good thermal operation
will depend on the size of the components and on their operation
(size of the thermal dissipation zones) and on the thermal
conductivities of the different materials (semi-conductor layer,
dissipating layer, sub-layers and substrate). The first layer may
be constituted by a material chosen from among polycrystalline
silicon, diamond, alumina, silicon nitride, aluminium nitride,
boron nitride, silicon carbide.
[0018] The first layer may be in contact with the semi-conductor
surface layer and be able to confer said electrical interface
quality. The semi-conductor structure being an SOI structure, the
first layer may be a layer of cubic silicon carbide.
[0019] Advantageously, the second layer of the intermediate zone
has sufficient thickness of insulant of low dielectric constant for
the stray capacitance present between the semi-conductor surface
layer and the support substrate to be sufficiently low to provide a
considered as correct operation of the electronic device or devices
which are to be elaborated from the semi-conductor surface
layer.
[0020] A further object of the invention is a process for
manufacturing a semi-conductor structure as defined above,
characterised in that it includes the following stages;
[0021] manufacture of the layers of the intermediate zone on one
face of a first substrate intended to supply said semi-conductor
surface layer and/or on one face of a second substrate intended to
supply the support substrate of the structure,
[0022] bonding of the first substrate on the second substrate, said
faces being placed opposite each other,
[0023] making of said semi-conductor surface layer.
[0024] Making said semi-conductor surface layer may include
reducing the thickness of the first substrate.
[0025] Bonding the first substrate onto the second substrate may be
achieved by molecular adhesion. In this case, the manufacturing
stage of the layers of the intermediate zone may include the
deposition of at least one bonding layer to allow bonding by
molecular adhesion. Advantageously, said bonding layer is a silicon
oxide layer.
[0026] The first layer may be a layer of a material chosen from
among polycrystalline silicon deposited by LPCVD, diamond deposited
by PECVD, alumina deposited by reactive cathode sputtering, silicon
nitride deposited by CVD, aluminium nitride deposited by CVD, boron
nitride deposited by CVD and silicon carbide deposited by CVD.
[0027] The reduction in the thickness of the first substrate may be
obtained by using one or more technologies from among:
rectification, chemical attack, polishing, separation following
thermal treatment along a cleavage plane induced by ion
implantation.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The invention will be better understood and other advantages
and particularities will emerge from reading the following
description, given as a non-restrictive example, accompanied by the
appended figures among which:
[0029] FIG. 1 shows, in a transverse view, a semi-conductor
structure with a heat distribution layer according to the present
invention,
[0030] FIGS. 2A to 2D show different stages of a first embodiment
process of a semi-conductor structure according to the present
invention,
[0031] FIGS. 3A and 3B show different stages of a second embodiment
process of a semi-conductor structure according to the present
invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0032] FIG. 1 shows a first example of a semi-conductor structure
according to the invention. This structure comprises a support
substrate 1 for example of silicon, a surface layer 2 of silicon
and an intermediate zone 3. The intermediate zone 3 comprises at
least one layer 4 of good thermal conductivity, an insulating layer
5 conferring good electrical quality of interface with the
semi-conductor surface layer 2 and an insulating layer 6, being
able to be of low thermal conductivity, adhering to the support
substrate 1.
[0033] In the case of an SOI structure implementing the molecular
adhesion process, the layer 6 may in particular be made of silica.
This layer 6 may of course be a multi-layer.
[0034] When the layer 4 of good thermal conductivity makes it
possible to have directly a good electrical interface with the
surface layer of silicon 2, the layer 5 may be omitted.
[0035] The structure according to the invention makes it possible
to retain the materials and thicknesses allowing both ease of
manufacture and good operation of the electronic devices which will
be made on or in the semi-conductor surface layer.
[0036] The layer 4 (or the layers 4) acts as a heat distributor and
makes it possible to reduce the rise in temperature in the heat
emitting device while making it possible to retain the subjacent
layer or layers of low thermal conductivity and of relatively
pronounced thickness.
[0037] The insulating layer 5 may also be an insulating
multi-layer.
[0038] The advantage of the invention from the thermal point of
view may be shown by means of the following example relative to an
SOI structure. A localised temperature rise is pre-supposed of 0.2
.mu.m diameter, corresponding to approximately the temperature rise
created by an advanced generation transistor. The resultant
temperature rise has been calculated by fixing the nature (silica)
and thickness of the order of the dimension of the electronic
device) manufactured in miscellaneous materials of thermal
conductivities, which are different but nonetheless always greater
than those of the silica, makes it possible to approach quite
quickly the temperature rise corresponding to the presence of the
single layer of silica 5 of 0.1 .mu.m thickness.
[0039] From the point of view of rapidity of the electronic device,
it is advantageous to choose for the layer 4 a material which is
insulating and if possible of low dielectric constant. This makes
it possible in fact to reduce dielectric capacities and losses.
[0040] A first process for manufacturing a semi-conductor structure
according to the present invention will now be described in
relation to FIGS. 2A to 2D.
[0041] FIG. 2A shows a first substrate 10 for example of silicon or
of SiC on one face of which has been manufactured a layer 15 of an
insulating material having with the substrate 10 an electrical
interface quality considered as sufficiently good. Preferably, the
layer 15 is a layer of silica obtained by thermal oxidation. Onto
the layer 15 is then deposited a layer 14 having satisfactory
thermal conductivity. Among the materials able to be used may be
cited polycrystalline silicon deposited by LPCVD, diamond deposited
by PECVD, alumina deposited by reactive cathode sputtering from an
aluminium target, silicon nitride, aluminium nitride, and boron
nitride deposited by CVD and SiC deposited by CVD. On a layer 14
may possibly be deposited an insulating layer 16' which also
facilitates bonding, preferably a layer of silica deposited for
example by CVD, except if the layer 14 allows direct bonding with a
second substrate 11.
[0042] The silicon substrate 10 has a layer 17 of micro-cavities
arranged parallel to the face of the substrate on which the
insulating layers 15, 14 and 16' have been obtained. This layer of
micro-cavities 17 delimits in the substrate 10 a layer 12 intended
to become the semi-conductor surface layer of the structure. The
micro-cavities have been obtained by ion implantation of hydrogen
in the conditions described in the document FR-A-2 681 472 so as to
obtain a separation into two parts of the substrate 10 along a
cleavage plane during subsequent thermal treatment. The ion
implantation operation may be carried out before or after the
insulating layers 15, 14 and 16' are obtained or between the
deposition of one of these layers and the deposition of another
layer.
[0043] FIG. 2B shows a second substrate 11 for example of silicon,
serving as a support substrate, on one face of which has been
manufactured a bonding layer 16". This bonding layer is preferably
a silica layer made by thermal oxidation. It is only necessary if
the nature of the substrate 11 does not allow direct bonding with
the layer 16'.
[0044] FIG. 2C shows the bonding stage, by molecular adhesion, of
the two substrates by bringing into contact the free and prepared
faces of the bonding layers 16' and 16".
[0045] Appropriate thermal treatment (see the document FR-A-2 681
472) then makes it possible to obtain the separation into two parts
of the substrate 10 along the layer of micro-cavities 17. The
structure is then obtained which is shown in FIG. 2D, which is an
SOI structure including a support substrate 11 and a surface layer
12 of silicon separated by an intermediate zone 13. The zone 13
includes an electrical interface layer 15, a layer 14 of sufficient
thermal conductivity and a bi-layer 16 (formed of the layers 16'
and 16" of silica) providing good adhesion with the substrate
11.
[0046] The free face of the surface layer 12 may then be
conditioned by polishing and cleaning.
[0047] A second process for manufacturing a semi-conductor
structure according to the present invention will now be described
in relation to FIGS. 3A and 3B.
[0048] FIG. 3A shows a first substrate 20 for example of silicon on
one face of which has been made, for example by epitaxy, a material
of good thermal conductivity so as to obtain a corresponding layer
24. The epitaxial material may be cubic silicon carbide elaborated
according to known techniques. On the layer 24 is then deposited an
insulating layer 26, for example a layer of silica.
[0049] As previously the silicon substrate 20 has a layer 27 of
micro-cavities arranged parallel to the face of the substrate on
which the insulating layers 24 and 26 have been deposited. This
layer of micro-cavities 27 delimits in the substrate 20 a layer 22
intended to become the semi-conductor surface layer of the SOI
structure. As previously, the layer 27 of micro-cavities has been
made in the conditions described in the document FR-A-2 681
472.
[0050] A second substrate 21 for example of silicon, serving as a
support substrate, has been prepared.
[0051] The two substrates are then bonded, by molecular adhesion,
by bringing into contact the free face of the layer 26 (see FIG.
3A) with a free face of the substrate 21. The result obtained is
shown in FIG. 3B.
[0052] An appropriate thermal treatment stage then makes it
possible to obtain the separation into two parts of the substrate
20 along the layer of micro-cavities 27.
[0053] In this embodiment example, it is advantageous to achieve
the ion implantation stage after the epitaxy of the insulating
layer 24. Indeed, the ion implantation of hydrogen in the silicon
carbide, when this material is used, makes the latter perfectly
insulating. This makes it possible to obtain an SOI structure of
the requisite quality.
[0054] It is also noted that, in this embodiment example, there is
no particular layer for obtaining the electrical interface with the
silicon surface layer. Indeed, the layer 24 of good thermal
conductivity being obtained by epitaxy, the interface with the
semi-conductor surface layer is a priori of satisfactory electrical
quality.
* * * * *