U.S. patent application number 10/911142 was filed with the patent office on 2005-11-17 for defect identification system and method for repairing killer defects in semiconductor devices.
Invention is credited to Albers, Bradley J., Brown, Gregory, Patterson, Oliver Desmond, Shuttleworth, David M., Weck, Werner.
Application Number | 20050255611 10/911142 |
Document ID | / |
Family ID | 35309934 |
Filed Date | 2005-11-17 |
United States Patent
Application |
20050255611 |
Kind Code |
A1 |
Patterson, Oliver Desmond ;
et al. |
November 17, 2005 |
Defect identification system and method for repairing killer
defects in semiconductor devices
Abstract
A method for improving semiconductor yield by in-line repair of
defects during manufacturing comprises inspecting dies on a wafer
after a selected layer is formed on the dies, identifying defects
in each of the dies, classifying the identified defects as killer
or non-critical, for each killer defect determining an action to
correct the defect, repairing the defect and returning the wafer to
a next process step. Also disclosed is a method for determining an
efficient repair process by dividing the die into a grid and using
analysis of the grid to find a least invasive repair.
Inventors: |
Patterson, Oliver Desmond;
(Windermere, FL) ; Shuttleworth, David M.;
(Orlando, FL) ; Albers, Bradley J.; (Dallas,
TX) ; Weck, Werner; (Orlando, FL) ; Brown,
Gregory; (Ocoee, FL) |
Correspondence
Address: |
BEUSSE BROWNLEE WOLTER MORA & MAIRE, P. A.
390 NORTH ORANGE AVENUE
SUITE 2500
ORLANDO
FL
32801
US
|
Family ID: |
35309934 |
Appl. No.: |
10/911142 |
Filed: |
August 4, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60571435 |
May 14, 2004 |
|
|
|
Current U.S.
Class: |
438/14 ;
257/E21.525; 257/E21.595 |
Current CPC
Class: |
G01R 31/2894 20130101;
H01L 22/20 20130101; H01L 21/76892 20130101 |
Class at
Publication: |
438/014 |
International
Class: |
H01L 021/66; G01R
031/26 |
Claims
What is claimed is:
1. A method of repairing killer defects in a semiconductor die
prior to completion of semiconductor processing comprising:
identifying a die having a killer defect; determining a location
and action for a minimally invasive repair; implementing the repair
action at the repair location; and continuing processing of the
semiconductor die.
2. The method of claim 1 wherein the step of determining includes:
defining a grid structure overlaying an area of the die containing
the defect; analyzing the grid structure to locate squares in the
grid structure containing portions of the defect; and determining a
minimum number of squares to modify in order to correct the
defect.
3. The method of claim 1 wherein the killer defect comprises a
shorting connection between conductors and the step of repairing
comprises cutting the shorting connection.
4. The method of claim 1 wherein the killer defect comprises an
open conductor space and the step of repairing comprises deposition
of conductor material in the open conductor space.
5. The method of claim 3 wherein the step of cutting comprises one
of focused ion beam etching, laser etching and microchemical
machining.
6. The method of claim 4 wherein the step of deposition comprises
laser assisted chemical deposition.
7. The method of claim 2 wherein the step of determining a minimum
number of squares comprises: defining the grid structure by columns
and rows; computing the number of squares in each column that would
require clearing to remove the defect; identifying a column having
a minimum number of squares requiring clearing; repeating the steps
of computing and identifying squares for each row to locate a row
having a minimum number of squares requiring clearing; comparing
the minimum number of squares in the column to the minimum number
of squares in the row to effect clearing; and selecting the one of
the column and the row having a minimum number of squares requiring
clearing.
8. The method of claim 7 and including the further steps of
determining a minimum width for clearing the defect and clearing
other squares to achieve the minimum width.
9. A method for improving semiconductor yield by in-line repair of
defects during manufacturing comprising: inspecting dies on a wafer
after a selected layer is formed on the dies; identifying defects
in each of the dies; classifying the identified defects as killer
or non-critical; for each killer defect determining an action to
correct the defect; repairing the defect; and returning the wafer
to a next process step.
10. The method of claim 9 wherein the killer defect comprises a
shorting connection between conductors and the step of repair
comprises cutting the connection.
11. The method of claim 10 wherein the step of cutting comprises
one of focused ion beam etching, laser etching and microchemical
machining.
12. The method of claim 9 wherein the defect comprises an open
space in a conductor and the step of repair comprises laser
assisted microchemical deposition.
Description
SPECIFIC DATA RELATED TO THE INVENTION
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/571,435, filed May 14, 2004.
TECHNICAL FIELD OF THE INVENTION
[0002] The present invention is directed, in general, to
semiconductor fabrication and, more specifically, to an in-line
defect identification system and method for repairing killer
defects in semiconductor devices upon detection.
BACKGROUND OF THE INVENTION
[0003] In the realm of semiconductor fabrication, systems and
methods for maximizing chip yield are critical to the success of a
semiconductor manufacturing company. Higher yields allows companies
to distribute the manufacturing costs over a greater quantity of
products, thereby reducing the sales price or increasing the profit
margin.
[0004] Optical, laser-based and SEM inspection tools are key pieces
of equipment for yield maintenance and improvement. They are used
to inspect wafers for defects at numerous points in the production
process. Their data is used for three fundamental purposes:
statistical process control (SPC), identification and
quantification of the defects limiting yield for process
improvement purposes, and yield modeling.
[0005] Inspection data is generally monitored using SPC since the
number of defects is a good indicator of yields. A change in the
distribution of defects can indicate a yield problem. Therefore, by
monitoring inspection data, the yield problem may be detected in a
timely manner. Despite the effectiveness of monitoring data, there
is opportunity for improvement. Many types of defects may arise
during manufacturing. These defects may be classified as either
"killer" or "non-critical" defects. Killer defects cause a
malfunction or failure of the semiconductor device, whereas
non-critical defects do not substantially affect the performance of
the semiconductor device. U.S. Pat. No. 6,047,083 describes one
method of identifying defects in semiconductor products during
their manufacture and for classifying such defects as "killer" or
non-critical. However, once the defect has been identified as
"killer", the only solution is to adjust the manufacturing process
to attempt to prevent future defects. It is not believed that the
industry has addressed the repair of killer defects in order to
salvage what otherwise would be defective products.
[0006] The majority of the yield loss for integrated circuits is
due to killer defects that are a) of sub-micron size, b) short
elements of a single mask level (such as metal or gate-stack
runners) together, or create opens at these same levels, and c) can
be detected using in-line inspection tools such as an inspection
SEM. This invention proposes a method of eliminating these defects
in-line, thereby recovering large amounts of yield.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1A and 1B schematic representations of a metal layer
of a semiconductor device or die illustrating a shorting defect and
its repair;
[0008] FIGS. 2A and 2B are schematic representations of an open
conductor defect in a metal layer and its repair;
[0009] FIG. 3 is a flow chart representation of a process for
defect analysis and repair; and
[0010] FIG. 4 illustrates a parsing process for die repair.
DETAILED DESCRIPTION OF THE INVENTION
[0011] The majority of the yield lost for integrated circuits is
due to defects that are of sub-micron size, short elements of a
single mask level (such as metal or gate stack runners) together or
create opens at the same levels and can be detected using in-line
inspection tools. The shorting mechanisms include metal to metal
shorts in either copper or aluminum technologies, gate-stack to
gate-stack shorts, gate-stack to window shorts and active region to
active region shorts. In-line inspection tools are capable of
detecting and locating most of these shorted conditions. For
example, U.S. Pat. No. 6,047,083 describes a method and apparatus
for pattern inspection that can be used to identify killer defects
on semiconductor dies. Most killer defects create a single short
between two adjacent elements and therefore only need a minor
repair to become non-yield limiting. However, the present invention
contemplates that killer defects that cause shorts between more
than two elements could be repaired by multiple step corrective
action.
[0012] Referring now to FIG. 1A, there is shown a plan view of a
small segment of a semiconductor die and, more particularly, a
representation of a metal layer on a die such as, for example,
metal 3. The metal layer includes a plurality of electrical
conductors 12, 14 and 16. A defect 18 which may be characterized as
a killer defect short circuits conductor 12 to conductor 14. FIG.
2B shows the same die layer after repair of the killer defect by
simply cutting through the defect 18 so that the electrical short
between the conductor elements 12 and 14 has been eliminated.
[0013] FIG. 2A illustrates another form of killer defect in a
semiconductor die layer in which the electrical conductor 20 has an
open or space so that continuity through the conductor element is
lost. As shown in FIG. 2B, the open killer defect indicated at 22
can be repaired by creating an electrically conducting bridge
between the spaced-apart ends of the conductor element 20.
[0014] The process of cutting through a killer defect such as
defect 18 in FIG. 1A can be performed using an in-line focused ion
beam or FIB tool to cut a trench through the shorting conductor.
However, one of the concerns with using the FIB tool is that such
use may result in gallium contamination. However, if gallium
contamination is an issue, a gallium barrier or layer that getters
gallium could be incorporated into the process flow for forming the
semiconductor layer after transistor formation thereby allowing FIB
cuts to be used in interconnect layers. Another possibility for
cutting through such killer defects is to use laser assisted
microchemical machining technology. Revise, Inc. markets a product
under the designation 9850 Silicon Etcher that could be used not
only for cutting through short circuiting defects such as defect 18
but also could be used to create the repair indicated at 24 in FIG.
2B. It is also possible that micromachining using MEMS and nano
technology could be adapted to affect cutting through of these
micron sized defects.
[0015] The actual repair process involves a number of steps that
are illustrated in block diagram form in FIG. 3. In a first step,
block 30, the integrated circuit or die layer needs to be inspected
to identify dies which have defects. Such inspection may be carried
out using optical examination, laser based or even scanning
electron microscope (SEM) inspection tools. The aforementioned U.S.
Pat. No. 6,047,083 describes one form of defect identification
using SEM inspection tools. Once the defects have been located,
further examination of each individual defect is necessary in order
to be able to classify the defect as either a killer or a
non-critical defect. Typically, a SEM inspection tool would be used
to image the area identified as having defects so each individual
defect could be manually examined. Block 32 indicates the step of
classifying and filtering out defects that are non-killer or
non-critical. While the SEM inspection tool is believed to be
currently the best tool choice for the classification task, other
alternative tools such as optical review tools may be suitable for
this application. It is also possible that the classification
process could be converted into an automated process such as is
described in the aforementioned U.S. Pat. No. 6,047,083. Killer
defects may be subdivided into two subclasses, shorts and opens. To
be a short, the defect must bridge two elements in the circuit and
must be conductive material. The composition may be surmised by the
appearance of the defect and/or by composition analysis techniques
such as energy dispersive x-ray spectroscopy EDX. To be an open, a
conductive element must be broken into two separate parts by the
defect and the defect must be non-conductive.
[0016] Once the potentially killer defects have been identified, it
is then necessary to filter out large defects that are not
practical to repair, block 34. Generally small defects that affect
one or two elements will be easier to repair than a defect that
affects three or more elements. First, only a single cut or bridge
is needed and second, the defect is less likely to bridge to
another level. Defects that bridge to another level are not likely
repairable. Other factors in filtering out killer defects may
include the success rate in repairing similar defects and the type
of defect. Once the defects have been classified and filtered, the
next step in the process is to determine what material has to be
removed from the die layer, block 36, in order to repair the die.
After determining what material has to be removed or what material
has to be added in the case of an open conductor, the next step is
to either remove the material, block 38, or deposit new material
and then to return the wafer to the next process step, block 40, to
complete manufacturing of the semiconductor devices.
[0017] The classification and filtering of blocks 32 and 34 can be
done manually using optical or SEM examination of the die layer.
Alternately, the automated identification and classification
procedure described in U.S. Pat. No. 6,047,083 could be applied.
However, once the devices have been sorted into those that can be
repaired, the next step is to determine what material needs to be
removed or which conductors need to have material added in order to
repair open spaces. A brute force method would be to remove all
material from a device layer that differs from the intended
pattern. Such a method would be economically unfeasible both from a
cost and time standpoint. Accordingly, applicants propose an
improved procedure which analyzes the area of the defect and
determines the simplest way to correct the defect without having to
completely remove all of the defective area.
[0018] FIG. 4 shows a diagram of the layout of FIG. 1A in which the
area containing the defect has been broken down into a grid
structure forming a plurality of squares. Preferably, the grid is
the same resolution as the grid used in the original design file
for the die circuit being examined. The grid structure can be
defined by a series of XY coordinants with the X coordinants being
identified by i.sub.1-i.sub.n. The Y coordinants are then defined
by j.sub.1-j.sub.n. For each column l.sub.1-l.sub.n, the number of
squares that would have to be removed in order to clear the
connection between the adjacent conductors is calculated. For
example, in FIG. 4, the defect can be removed by clearing the
squares 42,44 and 46 in column l.sub.4. Each of the columns is
evaluated and the number of squares that would have to be cleared
in order to remove the defect is totaled in order to identify the
column which would require the least number of squares to be
cleared. The same analysis is then applied along the Y axis to
identify the number of rows that must be cleared in order to remove
the defect. Thereafter, the minimals in the rows are compared to
the minimals in the columns to determine which of the rows or
columns would require the least amount of change in order to remove
the defect. Selection of a row or column, for example, a horizontal
or vertical cut, is then based upon which cut would require the
least material to be removed. In the example of FIG. 4, it is
apparent that the least material is removed by selecting the column
i.sub.4. This scenario assumes that removal of a single row or
column of squares provides sufficient resistance to effectively fix
the defect and allow the device to work sufficiently. Possible it
may be necessary to provide multiple square-widths of isolation
between runners. This algorithm may be modified accordingly to
define a minimum acceptable cut width.
[0019] Next for opens, the depth of the cut must be determined. For
full stack extras, the cut should be slightly more than the stack
height. For W puddles, the cut could be a proportion of the
diameter of the W puddle. For shorts, the thickness of the bridge
would be based on the conductivity of the material used and the
composition and line width of the defective runner.
[0020] As discussed above, once the squares in the grid have been
identified for removal of material and the repair thickness
determined, the material removal process can be implemented by
using FIB, laser assisted microchemical machining or some form of
micromaching using MEMS or nano technology. Further, in the case of
an open conductor, the open conductor can be repaired using a laser
assisted chemical deposition technique. It should be noted that in
the case of an open conductor, the analysis of the best way to
correct the defect may not be as complicated since the open occurs
in a conductor and the direction of the conductor will define the
direction and location of the repair.
* * * * *