U.S. patent application number 10/704272 was filed with the patent office on 2005-10-20 for multideposition sacvd reactor.
Invention is credited to Balsan, Christophe, Delarue, Fabrice, Journe, Joel, Raffin, Patrick, Waechter, Jean Marc.
Application Number | 20050229853 10/704272 |
Document ID | / |
Family ID | 8174251 |
Filed Date | 2005-10-20 |
United States Patent
Application |
20050229853 |
Kind Code |
A1 |
Raffin, Patrick ; et
al. |
October 20, 2005 |
Multideposition SACVD reactor
Abstract
There is disclosed a high throughput multideposition SACVD
reactor that enables the rapid thermal deposition of dielectric
materials such as Si.sub.3N.sub.4, SiO.sub.2, and SiON and
non-&electric materials such as polysilicon onto a
semiconductor substrate in the same chamber according to the
desired sequence. Such a reactor has a processing chamber which is
well adapted to single semiconductor wafer processing. The
processing chamber includes an improved susceptor to support the
wafer and a specific gas distribution system adapted to supply the
different gases used in the deposition process and for cleaning.
The improved susceptor consists of a standard carbon plate coated
with a polysilicon film to protect it against said cleaning gases
when they are aggressive to carbon. The present invention also
encompasses a method of fabricating said improved susceptor.
Inventors: |
Raffin, Patrick; (Joinville
Le Pont, FR) ; Delarue, Fabrice; (Paris, FR) ;
Waechter, Jean Marc; (Saint Vincent de Marcuze, FR) ;
Balsan, Christophe; (Vaux Le Penil, FR) ; Journe,
Joel; (Chailly en Biere, FR) |
Correspondence
Address: |
Magaret A. Pepper
International Business Machines Corporation
2070 Route 52, Zip 482
Hopewell Junction
NY
12533
US
|
Family ID: |
8174251 |
Appl. No.: |
10/704272 |
Filed: |
November 7, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10704272 |
Nov 7, 2003 |
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09904424 |
Jul 12, 2001 |
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6770144 |
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Current U.S.
Class: |
118/725 ;
257/E21.165; 257/E21.166; 257/E21.17; 257/E21.268; 257/E21.269;
257/E21.279; 257/E21.293; 427/248.1 |
Current CPC
Class: |
C23C 16/54 20130101;
H01L 21/28518 20130101; C23C 16/4405 20130101; H01L 21/28525
20130101; H01L 21/3144 20130101; C23C 16/45561 20130101; C23C
16/4581 20130101; H01L 21/3185 20130101; C23C 16/45574 20130101;
H01L 21/28556 20130101; H01L 21/3145 20130101; H01L 21/31612
20130101 |
Class at
Publication: |
118/725 ;
427/248.1 |
International
Class: |
C23C 016/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 25, 2000 |
EP |
00480069.4 |
Claims
1-9. (canceled)
10. A method of in-situ conditioning a carbon susceptor in a AME
Centura reactor to render it NF.sub.3 resistant comprising the
steps of: a) placing a standard carbon susceptor in a processing
chamber of said reactor; b) cleaning said chamber interior volume
with HCl; c) purging said interior volume with H.sub.2; d) coating
said susceptor bottom with a film of polysilicon using a DCS
precursor; e) purging said interior volume with H.sub.2; f) coating
said susceptor top with a film of polysilicon using a SiH.sub.4
precursor; and g) purging said interior volume with H.sub.2.
11. The method of claim 10 wherein in the step of coating said
carbon susceptor bottom is performed with a lamp power of 26 kW (#
950.degree. C.), for a duration of 540 s, with a DCS flow of about
0.4 slm, with a H.sub.2 flow of about 19 slm, and at a deposition
rate of about 300 nm/min.
12. The method of claim 11 wherein said bottom polysilicon coating
has a thickness of about 4 .mu.m.
13. The method of claim 10 wherein in the step of coating said
carbon susceptor top is performed at a temperature of about
675.degree. C., with a SiH.sub.4 flow of about 0.5 slm, with a
H.sub.2 flow of about 9.5 slm, for a duration of about 400 s, and
at a deposition rate of about 150 nm/min.
14. The method of claim 13 wherein said top polysilicon coating has
a thickness of about 1.5 .mu.m.
15-16. (canceled)
17. The method of claim 10 wherein said bottom polysilicon coating
has a thickness of about 4 .mu.m and said top polysilicon coating
has a thickness of about 1.5 .mu.m.
18. A method of in-situ conditioning a carbon susceptor in a
sub-atmospheric chemical vapor deposition reactor to render it
NF.sub.3 resistant, the method comprising the steps of: a) placing
said carbon susceptor in a processing chamber of said reactor, said
susceptor having a bottom surface and a top surface; b) cleaning
said chamber interior volume with HCl; c) purging said interior
volume with H.sub.2; d) coating said susceptor bottom surface with
a film of polysilicon using a DCS precursor, said susceptor bottom
film having a first thickness; e) purging said interior volume with
H.sub.2; f) coating said susceptor top surface with a film of
polysilicon using a SiH.sub.4 precursor, said susceptor top film
having a second thickness which is less than said first thickness;
and g) purging said interior volume with H.sub.2.
19. The method of claim 18 wherein said first thickness is about 4
.mu.m and said second thickness is about 1.5 .mu.m.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the manufacture of
semiconductor integrated circuits (ICs) and more particularly to a
multideposition sub-atmospheric chemical vapor deposition (SACVD)
reactor enabling the rapid thermal deposition of dielectric
materials such Si.sub.3N.sub.4, SiO.sub.2, and SiON and of
non-dielectric materials such as polysilicon onto a substrate.
According to the present invention, said dielectric/non-dielectric
materials can be now deposited according to the desired sequence in
the same chamber of the multideposition SACVD reactor,
significantly reducing cycle time, total thermal budget and pattern
factor effects.
BACKGROUND OF TE INVENTION
[0002] Short cycle time and low thermal budget are certainly the
most critical points for Application Specific Integrated Circuit
(ASIC) and Dynamic Random Access Memory (DRAM) products
manufacturing respectively. The continuous technical progress in
the last decades has resulted in the emergence of new techniques to
improve product integration and speed that shows out the necessity
to work deeper on deposition tool to improve their characteristics.
Requirements such as low thermal budget, low pattern factor,
foreign element control and short cycle time are now becoming of
paramount importance. A low thermal budget is essential to keep
IGFET effective channel length (L.sub.eff) within specifications,
to increase the process window and to have low junction contact
resistance. Another important parameter is the pattern factor which
is determining to embed memory cells in a logic chip. Still another
parameter (previously deemed more secondary) is the foreign element
control. Foreign elements that are incorporated into the deposited
films during fabrication also drive device performance, and thus
are becoming more important to date, as devices become more and
more dense and complex. The possibility to control foreign element
presence in deposited films facilitates the tuning of the devices
and the correction or adjustment of some electrical fails such as
junction leakages and the retention time. Finally, short cycle
times which increase the manufacturing throughput are also
worthwhile in terms of cost reduction. All these parameters have
become critical in semiconductor devices particularly when it is
required to deposit dielectric and non-dielectric materials in
sequence according to the Chemical Vapor Deposition (CVD)
technique. It would be highly desirable to perform the maximum
deposition steps in the same equipment without unloading the wafers
in order to improve the manufacturing throughput and to reduce the
cycle time.
[0003] In the course of fabricating IGFETs for a standard DRAM
product, at the stage of the gate conductor formation, it is
required to form a stack (GC stack) comprised of a bottom 10 nm
thick SiO.sub.2 gate layer, then a 80 nm thick doped polysilicon
layer, a 70 nm thick tungsten silicide (WSi.sub.x) layer and
finally a 180 nm thick top protective cap Si.sub.3N.sub.4 layer.
Next, the GC stack is patterned by dry etching to produce the gate
conductor lines (GC lines) and a thin SiO.sub.2 spacer is formed by
thermal oxidation on the exposed sidewalls of the doped polysilicon
material. All these processing steps are performed in a different
tool in the so-called Middle End Of the Line (MEOL) module.
[0004] For instance, the thin SiO.sub.2 bottom gate layer is
obtained by thermal oxidation using an Atmospheric Pressure
Oxidation furnace (APOX) as standard, such as the SVG VTR 7000
(oxidation) vertical furnace sold by SVG-THERMCO, San Jose, Calif.,
USA The deposition of the 80 nm thick doped polysilicon layer and
the 70 nm thick WSi.sub.x layer is performed in two different
chambers of a SACVD Centura HTF reactor, a tool manufactured by
Applied Materials Inc, Santa Clara, Calif., USA using the following
operating conditions:
[0005] Doped Polysilicon Deposition
[0006] Pressure: 80 Torr
[0007] Temperature: 660.degree. C.
[0008] SiH.sub.4flow: 0.3 slm
[0009] PH.sub.3 flow: 0.09 slm
[0010] H.sub.2flow: 9.9 slm
[0011] Dep. rate: 80 nm/min
[0012] wherein "sccm" denotes standard cubic centimers per minute
and "slm" denotes standard liters per minute.
[0013] WSi.sub.x Deposition
[0014] Pressure: 1 Torr
[0015] Temperature: 550.degree. C.
[0016] WF.sub.6 flow: 2.4 sccm
[0017] SiH.sub.2Cl.sub.2 flow: 175 sccm
[0018] Ar flow: 1500 sccm
[0019] Dep. rate: 12 nm/min
[0020] Finally, the Si.sub.3N.sub.4 material is deposited in a
LPCVD batch furnace, such as a TEL Alpha 8s, a tool sold by TOKYO
ELECTRON Ltd, Tokyo, Japan using the operating conditions recited
below.
[0021] Si.sub.3N.sub.4 Deposition
[0022] Step 1
[0023] Pressure: 150 mTorr
[0024] Temperature: 715.degree. C.
[0025] NH.sub.3flow: 250 sccm
[0026] DCS flow: 50 sccm
[0027] Wafer spacing: 0.2 inch
[0028] Dep. rate: 0.7 nm/min
[0029] Dep. time: 40 min
[0030] Step 2
[0031] Pressure: 80 mTorr
[0032] Temperature: 770.degree. C.
[0033] NH.sub.3 flow: 400 sccm
[0034] DCS flow: 80 sccm
[0035] Wafer spacing: 0.2 inch
[0036] Dep. rate: 1.5 nm/min
[0037] Dep. time: 120 min
[0038] The first step must be conducted at a low temperature to
prevent WSi.sub.x oxidation at boat insertion in the furnace. About
100 wafers are processed for a total time (including
loading/unloading operations) of about 375 min.
[0039] TABLE I below summarizes this sequence of deposition steps
that are performed in the MEOL module.
1 TABLE I Materials Deposition process SiO.sub.2 APOX Doped
polysilicon SACVD (chamber 1) WSi.sub.x SACVD (chamber 2)
Si.sub.3N.sub.4 LPCVD
[0040] More generally, if we consider all processing steps that are
performed in the DRAM manufacturing line, the use of LPCVD and APOX
furnaces are substantially limited to the Front End Of the Line
(FEOL) and MEOL modules, as summarized in TABLE II below, for the
deposition for different types of materials.
2 TABLE II Modules FEOL MEOL Temp. 600-950.degree. C.
550-750.degree. C. Time 3-7 H 3-7 H (1); 5 min (2) Si.sub.3N.sub.4
LPCVD LPCVD (1) SiON LPCVD LPCVD (1) SiO.sub.2 APOX APOX (1)
Polysil LPCVD SACVD (2) WSi.sub.x SACVD (2)
[0041] (1) and (2) respectively refer to the duration for
LPCVD/APOX and SACVD processes. There is no breakdown when the
wafer is moved from chamber 1 to chamber 2 of the SACVD tool but
there is a significant breakdown after the wafer is unloaded from
chamber 2 to be loaded in the LPCVD furnace. Because, the LPCVD
tool is of the batch type, there is an important wait time before a
full batch of 100 wafers is loaded. As a consequence, before
inserting the boat in the furnace, the wafers need to be cleaned
for instance in a FSI spray tool (FLUOROWARE SYSTEMS Inc.,
Minneapolis, USA) using a SP/Huang AB cleaning sequence. As a
whole, these operations are time consuming.
[0042] It is not possible to deposit the Si.sub.3N.sub.4 material
in the same AME Centura reactor because processing chambers are
strictly limited to the deposition of polysilicon films or
WSi.sub.x films.
[0043] Applicants have discovered a manner to modify this
conventional SACVD reactor normally exclusively used to perform
polysilicon deposition to add the capacity of depositing dielectric
materials such as Si.sub.3N.sub.4, SiON and SiO.sub.2 in addition
to polysilicon. As a result, multideposition of materials as
different as dielectric and polysilicon in the reactor chamber
according to any desired sequence is now possible without the above
mentioned inconveniences (wait time, cleaning and long cycle
time).
SUMMARY OF THE INVENTION
[0044] It is therefore a primary object of the present invention to
provide a multideposition CVD reactor enabling the rapid thermal
deposition of dielectric materials such as Si.sub.3N.sub.4,
SiO.sub.2, and SiON and non-dielectric materials such as
polysilicon onto a substrate in the same chamber of the
reactor.
[0045] It is another primary object of the present invention to
provide a multideposition CVD reactor provided with multiple
chambers enabling the rapid thermal deposition of dielectric
materials such as Si.sub.3N.sub.4, SiO.sub.2, and SiON and
non-dielectric materials such as polysilicon onto a substrate in
two dedicated chambers of the reactor.
[0046] It is another object of the present invention to provide a
multideposition CVD reactor enabling the rapid thermal deposition
of dielectric materials such as Si.sub.3N.sub.4, SiO.sub.2, and
SiON and non-dielectric materials such as polysilicon onto a
substrate that is particularly adapted to ASIC production (short
cycle times and low thermal budget).
[0047] It is another object of the present invention to provide a
multideposition CVD reactor enabling the rapid thermal deposition
of dielectric materials such as Si.sub.3N.sub.4, SiO.sub.2, and
SiON and non-dielectric materials such as polysilicon onto a
substrate that is provided with an improved susceptor and a gas
distribution system adapted to multiple material deposition.
[0048] It is another object of the present invention to provide a
multideposition CVD reactor enabling the rapid thermal deposition
of dielectric materials such as Si.sub.3N.sub.4, SiO.sub.2, and
SiON and non-dielectric materials such as polysilicon onto a
substrate that allows high throughput.
[0049] It is another object of the present invention to provide a
multideposition CVD reactor enabling the rapid thermal deposition
of dielectric materials such as Si.sub.3N.sub.4, SiO.sub.2, and
SiON and non-dielectric materials such as polysilicon onto a
substrate that can be widely used elsewhere in the manufacturing
line irrespective the module (FEOL/MEOL).
[0050] It is still another object of the present invention to
provide a multideposition CVD reactor enabling the rapid thermal
deposition of dielectric materials such as Si.sub.3N.sub.4,
SiO.sub.2, and SiON and non-dielectric materials such as
polysilicon onto a substrate that is well adapted to the
fabrication of borderless polysilicon contacts in advanced
EDRAM/SDRAM silicon chips.
[0051] It is still another further object of the present invention
to provide a multideposition CVD reactor enabling the rapid thermal
deposition of dielectric materials such as Si.sub.3N.sub.4,
SiO.sub.2, and SiON and non-dielectric materials such as
polysilicon onto a substrate that is well adapted to fully
integrate the GC stack fabrication process in advanced SDRAM
silicon chips.
[0052] According to the present invention there is described a
multideposition sub-atmospheric chemical vapor deposition (SACVD)
reactor comprising: a substrate processing chamber; a carbon
susceptor adapted to hold a substrate in said substrate processing
chamber during a SACVD operation, wherein said carbon susceptor is
coated by a polysilicon film to protect it against said cleaning
gases; a gas distribution system adapted to introduce gases into
said substrate processing chamber and including appropriate valves,
gas supply lines and other equipment necessary to flow gases into
the substrate processing chamber; wherein said gases include
dielectric/non-dielectric forming gases and in-situ cleaning gases
that are aggressive to carbon; a heating system to heat the
susceptor/wafer to the adequate deposition temperature; a
pressurization system adapted to set a pressure level within said
substrate processing chamber; and a controller coupled to said gas
distribution system and pressurization system for directing the
operation of the SACVD reactor.
[0053] When the SACVD Centura reactor is used as the base
deposition tool, the present invention also concerns the method of
coating said carbon plate in the case, the dielectric material to
be deposited is Si.sub.3N.sub.4 to render it NF.sub.3 resistant,
said method comprising the steps of: a) placing the standard carbon
susceptor in the reactor processing chamber; b) cleaning the
chamber interior volume with HCl; c) purging said interior volume
with H.sub.2; d) coating the susceptor bottom with a film of
polysilicon using a DCS precursor; e) purging said interior volume
with H.sub.2; f) coating the susceptor top with a film of
polysilicon using a SiH.sub.4 precursor; and g) purging said
interior volume with H.sub.2.
[0054] A multideposition process is now made possible with tools
that are provided with multiple chambers, such as the AME Centura
HTF reactor, wherein every chamber can be dedicated to the
deposition of a single material (dielectric or polysilicon) for a
totally integrated process (cluster mode).
[0055] The novel features believed to be characteristic of this
invention are set forth in the appended claims. The invention
itself, however, as well as other objects and advantages thereof,
may be best understood by reference to the following detailed
description of an illustrated preferred embodiment to be read in
conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0056] FIG. 1 schematically shows the cross sectional view of a
conventional SACVD reactor, in the instant case, the AME HTF
Centura reactor.
[0057] FIG. 2 is a diagram of the gas distribution system
illustrating the different gas sources and mixes of the AME Centura
reactor once modified according to the present invention.
[0058] FIG. 3 is a flow chart illustrating the main steps of
fabricating the improved susceptor according to the present
invention that is resistant to NF.sub.3 in-situ clean.
[0059] FIG. 4 shows a complex silicon structure represented by the
borderless polysilicon contact wherein substantially all the
deposition steps can be performed in the AME Centura reactor once
modified according to the present invention.
[0060] FIG. 5 shows the variations of the deposition rate versus
the pattern effect factor to demonstrate the limits of conventional
LPCVD techniques in EDRAM chip fabrication in terms of
reproducibility.
[0061] FIG. 6 is a graph showing the variations of the effective
channel length L.sub.eff for POR LPCVD techniques (at two different
temperatures) and the SACVD technique according to the present
invention for different lots of wafers.
[0062] FIG. 7 is a graph showing the variations of the sheet
resistance Rs of diffusion regions in the array area for POR LPCVD
techniques (at two different temperatures) and the SACVD technique
according to the present invention for different lots of
wafers.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0063] Historically, LPCVD processes have been performed in
vertical furnaces. In the past several years, new deposition tools
have become available which overcome the limitations of vertical
furnaces because they are single-wafer processing based systems.
The SACVD Centura HTF reactor is a good example of that new
generation of deposition equipments. However, it is strictly
limited to the deposition of polysilicon films. It is a cold-wall
reactor that uses radiant heating for thermal energy. It operates
at reduced pressure and in a temperature range of 550-1200.degree.
C. (depending upon the type of operation: deposition or cleaning).
FIG. 1 schematically shows the cross-section of the SACVD Centura
reactor with its major elements. Now tuning to FIG. 1, reactor 10
has top and bottom walls (dome), side walls and a bottom wall that
define the internal volume of the processing vacuum chamber 11 into
which a substrate, typically a silicon wafer 12, can be loaded. The
wafer 12 sits on a carbon susceptor 13 which is supported by a
quartz pedestal 14 that can be rotated. A preheat ring 15 surrounds
the susceptor 13. The wafer 12 and susceptor 13 are heated by banks
of lamps 16 located outside above and below the process chamber 11.
The top and bottom walls of the chamber are made of quartz and thus
are transparent to light from external lamps in order to heat the
susceptor, the wafer and the preheat ring. Gas distribution system
17 is provided with a gas input port or inlet 18A connected to a
gas manifold to supply one or a mixture of gases in the process
chamber 11 via a plurality of pipes. The gas concentrations and
flow rate through each of these pipes are selected as standard to
produce reactant gas flows and concentration profiles that optimize
the deposition process. Reactor 10 further includes pressurization
means connected to the gas output port or outlet 18B to produce the
desired vacuum into process chamber 11 and temperature measurement
means, typically a pyrometer 19, as known for those skilled in the
art.
[0064] Due to the particular construction of the AME Centura
reactor, there is no substantial communication between the upper
and lower volumes of the processing chamber 11. Consequently, as
apparent in FIG. 1 (see arrows near inlet 18), certain gases such
as SiH.sub.4, PH.sub.3, DCS, HCl and N.sub.2 are injected in the
upper volume (above wafer 12) while other gases such as DCS,
N.sub.2 and HCl are injected in the lower volume (under susceptor
13). In normal operation, the gases flow from the gas inlet 18A
across the preheat ring 15 (where the gases are warmed-up) then
across the surface of the wafer 12 in the direction of the outlet
18B to perform the polysilicon film deposition. The process gases
flow horizontally over the wafer in a laminar flow pattern from the
gas inlet across the preheat ring and the wafer to the outlet where
they exhaust.
[0065] Some important modifications have been made to adapt the
reactor 10 of FIG. 1 to allow the multideposition feature according
to the present invention.
[0066] The original gas distribution system 17 has been modified
according to the present invention. Now turning to FIG. 2, new gas
lines and valves have been added (shown in grey) to transport
NF.sub.3, NH.sub.3 and N.sub.2O now required according to the
present invention as it will be described in due course.
[0067] In the equipment sold by APPLIED MATERIALS, there is
abaratron gauge mounted at the reactor outlet 18B that is used to
perform the pressure measurements. Now, still according to the
present invention, it is heated to about 150.degree. C. to prevent
any Si.sub.3N.sub.4 deposition on its membrane that would be
damaged accordingly.
[0068] Before the AME Centura reactor is used for the first
dielectric material deposition, typically Si.sub.3N.sub.4, the
original carbon susceptor is submitted in-situ to the sequence of
steps that will be now described by reference to flow-chart 20
illustrated in FIG. 3. The polysilicon coating procedure described
below is relatively complex because of the particular construction
of the AME Centura reactor and its resident software. A specific
conditioning of the susceptor is required because it is made of
carbon. NF.sub.3 which is the preferred cleaning chemical compound
to remove the Si.sub.3N.sub.4 material deposited on the reactor
walls and the susceptor is known to be very aggressive to carbon
(other fluorinated compounds, e.g. ClF.sub.3, are adequate as
well). The carbon susceptor protection against NF.sub.3 chemical is
first ensured by a coating of polysilicon (about 4 .mu.M thick)
performed on the susceptor bottom with a SiH.sub.2Cl.sub.2 (DCS)
chemistry. In fact, this polysilicon coating plays a double role:
it not only protects the susceptor bottom, it also allows
determination of the susceptor temperature by a measure of its
emissivity. Then, another polysilicon coating (about 1.5 .mu.m
thick) is performed on the susceptor top with a SiH.sub.4
chemistry.
[0069] Now turning to FIG. 3, the carbon susceptor is first cleaned
(box 21) using the following operating conditions:
[0070] HCl Clean
[0071] Lamp power: 43 kW (# 1200.degree. C.)
[0072] Pressure: 660 Torr
[0073] HCl flow: 9.9 slm
[0074] H.sub.2flow: 5 slm
[0075] After HCl cleaning, the chamber is cooled down to
950.degree. C. and the pressure is reduced down to 80 Torr.
[0076] After pressure and temperature stabilization, DCS is flowed
in the lower volume of the chamber and the susceptor bottom is now
coated with polysilicon (box 22). Operating conditions are recited
below:
[0077] Polysilicon Coating (Susceptor Bottom)
[0078] Lamp power: 26 kW (# 950.degree. C.)
[0079] Duration: 540 s
[0080] DCS flow: 0.4 slm
[0081] H.sub.2 flow: 19 slm
[0082] Dep. rate: 300 nm/min
[0083] The temperature is not monitored during the bottom coating
but is rather set by the lamp power. This is because the pyrometer
19 reading fluctuates during the coating operation. To ensure a
good emissivity of the bottom polysilicon coating, it is important
to get the right thickness of the polysilicon film. A thickness of
about 4 .mu.m is adequate for protection and accurate temperature
measurement. In this case, with a deposition between 300 nm/mn and
350 nm/mn, only a few minutes are required. The power setpoint is
adjusted to obtain this rate. DCS is preferred because it has a
faster deposition rate than SiH4 at this elevated temperature
(950.degree. C.). In addition, it produces polysilicon with a
thinner grain than with SiH.sub.4, increasing thereby its
emissivity and in turn the accuracy of the temperature measurement
by the optical pyrometer 19.
[0084] Finally, the susceptor top is coated with polysilicon using
a SiH.sub.4 precursor (step 23). The chamber is first cooled down
to 675.degree. C., then the top coating is performed with the
following operating conditions:
[0085] Polysilicon Coating (Susceptor Top)
[0086] Temp.: 675.degree. C.
[0087] SiH.sub.4 flow: 0.5 slm
[0088] H.sub.2 flow: 9.5 slm
[0089] Duration: 400 s
[0090] Dep. rate: 150 nm/min
[0091] Note that the top polysilicon coating can be performed using
either SiH.sub.4 and PH.sub.3 to deposit doped polysilicon or
SiH.sub.4 only to deposit intrinsic polysilicon as described above.
The thickness of the top coating is important for subsequent
dielectric/polysilicon deposition steps in the processing chamber
to ensure a sufficient protection of the carbon susceptor. Since
the top coating now is accurately controlled by the temperature,
the pyrometer 19 must be correctly set up.
[0092] Note that there is an H.sub.2 purge performed after each
polysilicon coating step such as described below:
[0093] H.sub.2 Purge
[0094] H.sub.2flow: 10 slm
[0095] Lamp power: 43 kW
[0096] Duration: 60 s
[0097] As such, the carbon susceptor is now ready for the
deposition of dielectric materials, typically Si.sub.3N.sub.4, in
the AME Centura tool.
[0098] When a great number of wafers have been processed, it is
necessary to perform a total cleaning of the reactor walls and the
susceptor using NF.sub.3 to remove all the Si.sub.3N.sub.4 material
deposited thereon, then with HCl to remove the polysilicon coating
the susceptor that has been damaged using the operating conditions
given below:
[0099] NF.sub.3 Clean
[0100] Pressure: 500 Torr
[0101] Temp.: 850.degree. C.
[0102] NF.sub.3 flow: 250 sccm
[0103] N.sub.2 flow: 2 sccm
[0104] Si.sub.3N.sub.4 etch rate: 1 .mu.m/mn
[0105] Poly. etch rate: 0.3 .mu.m/mn
[0106] HCl Clean
[0107] Lamp power: 43 kW
[0108] Pressure: 660 Torr
[0109] HCl flow: 9.9 slm
[0110] H.sub.2 flow: 5 slm
[0111] Temp.: 1200.degree. C.
[0112] Poly. etch rate: 2 .mu.m/mn
[0113] As a matter of fact, the processing chamber needs to be
cleaned and the susceptor reconditioned after 15 .mu.m of
Si.sub.3N.sub.4 material have been deposited, i.e. after about 6000
wafers have been processed. The susceptor is reconditioned as
described above by reference to FIG. 3. The chamber will be then
ready for running again a great number of dielectric/non-dielectric
deposition steps.
[0114] Deposition of Dielectric Materials
[0115] Si.sub.3N.sub.4 deposition
[0116] Pressure: 80-150 Torr
[0117] Temperature: 600-950.degree. C,
[0118] NH.sub.3 flow: 3.2 slm
[0119] SiH.sub.4 flow: 30 sccm
[0120] N.sub.2flow: 5 slm
[0121] SiO.sub.2 Deposition
[0122] Pressure: 50-100 Torr
[0123] Temperature: 600-950.degree. C.
[0124] SiH.sub.4 flow: 60 sccm
[0125] N.sub.2O flow: 2.8 slm
[0126] N.sub.2 flow: 9.2 slm
[0127] Presence of hydrogen atoms is not a problem in the formation
of SiO.sub.2 spacers, but the above deposition process cannot be
used to deposit the SiO.sub.2 gate layer, because, in this case the
SiO.sub.2 material must be totally pure and not contaminated.
[0128] The SACVD reactor such as modified according to the present
invention can be generalized to the deposition of more complex
dielectric materials, such as SiON using the following operating
conditions.
[0129] SiON Deposition
[0130] Pressure: 80-150 Torr
[0131] Temperature: 600-950.degree. C.
[0132] NH.sub.3 flow: 1 slm
[0133] DCS flow: 200 sccm
[0134] N.sub.2O flow: 2.8 slm
[0135] N.sub.2 flow: 5 slm
[0136] When placed in the AME Centura reactor, the
polysilicon-coated carbon susceptor still allows polysilicon
deposition but is adequate to the deposition of other materials
such as metal when the cleaning gases that are used are aggressive
to carbon.
[0137] Deposition of Non-dielectric Materials
[0138] Deposition of Doped Polysilicon
[0139] Pressure: 80-160 Torr
[0140] Temperature: 600-700.degree. C.
[0141] SiH.sub.4 flow: 0.3 slm
[0142] H.sub.2 flow: 9.9 slm
[0143] PH.sub.3 flow: 0.09 slm
[0144] Deposition of Intrinsic Polysilicon
[0145] Pressure: 80-160 Torr
[0146] Temperature: 650-750.degree. C.
[0147] SiH.sub.4 flow: 0.3 slm
[0148] H.sub.2 flow: 9.9 slm
[0149] Let us consider again the GC stack formation described above
in the Background of the Invention section of this patent
application. Using the AME Centura tool modified according to the
teachings of the present invention, the new sequence of deposition
steps becomes:
[0150] Doped Polysilicon Deposition
[0151] Pressure: 80 Torr
[0152] Temperature: 660.degree. C.
[0153] SiH.sub.4 flow: 0.3 slm
[0154] H.sub.2 flow: 9.9 slm
[0155] PH.sub.3 flow: 0.09 slm
[0156] Dep. rate: 80 nm/min
[0157] Cycle time: 4 mn
[0158] WSi.sub.x Deposition
[0159] Pressure: 1 Torr
[0160] Temperature: 550.degree. C.
[0161] WF.sub.6 flow: 2.4 sccm
[0162] DCS flow: 175 sccm
[0163] Ar flow: 1500 sccm
[0164] Dep. rate: 12 nm/min
[0165] Cycle time: 5 mn
[0166] Si.sub.3N.sub.4 Deposition
[0167] Pressure: 100 Torr
[0168] Temperature: 785.degree. C.
[0169] NH.sub.3 flow: 3.2 slm
[0170] SiH.sub.4 flow: 30 sccm
[0171] N.sub.2 flow: 5 slm
[0172] Dep. rate: 35 nm/mn
[0173] Cycle time: 6 min
[0174] The deposition of the doped polysilicon and Si.sub.3N.sub.4
materials is performed in a first chamber of the AME Centura
reactor while the deposition of the WSi.sub.x material is performed
in another chamber, as it is made apparent in the TABLE III
below:
3 TABLE III Materials Deposition process SiO.sub.2 APOX Doped
polysilicon SACVD (Chamber 1) WSi.sub.x SACVD (Chamber 2)
Si.sub.3N.sub.4 SACVD (Chamber 1)
[0175] As a result it is a fully integrated process (cluster mode).
The total cycle time to process one wafer is now very short (about
15 min), a major advantage for ASICs. Other advantages include a
reduced contamination, less loading/unloading operations, no wait
time and elimination of a cleaning step. Finally, the throughput is
increased.
[0176] FIG. 4 shows a conventional borderless polysilicon contact
structure referenced 24. Now turning to FIG. 4, there is shown a
silicon substrate 25 having a thin SiO.sub.2 gate layer 26 formed
thereon that is provided with an opening to expose a diffusion
region 27. The gate conductor stack comprised of a bottom doped
polysilicon/WSi.sub.x layer 28 and its top Si.sub.3N.sub.4 capping
layer 29. It is formed onto the SiO.sub.2 gate layer 26 as
standard. The borderless doped polysilicon plug 30 con tacts the
diffusion region 27 and is isolated from the GC stack by a
composite insulating layer. Said composite insulating layer
comprises sidewall SiO.sub.2 spacer 31, Si.sub.3N.sub.4 spacer 32
and Si.sub.3N.sub.4 barrier 33. The structure 24 further includes
BPSG and TEOS planarizing/insulating layers 34 and 35 respectively.
With such a structure, the multi-deposition SACVD reactor of the
present invention is able to perform the deposition of all the
materials mentioned above except the BPSG material, because it
contains a P type dopant (boron), it would detrimentally impact the
N type doped polysilicon contact plug 30.
[0177] The TABLE IV below indicates to a person skilled in the art,
the recommended working conditions when two materials of different
type (dielectric/non-dielectric) are successively deposited in the
same chamber of the AME Centura reactor.
4 TABLE IV 1st material 2nd material Conditions Polysilicon
Si.sub.3N.sub.4 direct pass Polysilicon SiON direct pass
Si.sub.3N.sub.4 SiON direct pass Si.sub.3N.sub.4 Polysilicon poly
coating(1) Si.sub.3N.sub.4 SiO.sub.2 NF.sub.3 clean + poly
coating(2) SiON Si.sub.3N.sub.4 direct pass SiON SiO.sub.2 direct
pass SiO.sub.2 Si.sub.3N.sub.4 NF.sub.3 clean + poly coating(2)
SiO.sub.2 SiON direct pass SiON Polysilicon poly coating(1)
[0178] (1): this step is identical to the step of coating the
susceptor top described above but with a lower thickness (0.2
.mu.m). It is required to facilitate polysilicon nucleation on the
Si.sub.3N.sub.4 material deposited on the susceptor.
[0179] (2): after the NF.sub.3 cleaning, the polysilicon coating
the susceptor top is damaged, so that a new coating has to be done
using the same operating conditions as described above (see box 23
in FIG. 3).
[0180] The optimum would be to dedicate two chambers of the AME
Centura tool (which is a multi-chamber equipment), one to the
polysilicon and another to Si.sub.3N.sub.4 for successive
depositions without unloading the wafer from the tool. In this
case, the first chamber would use the original carbon susceptor for
polysilicon deposition while the second chamber would be provided
with the polysilicon coated carbon susceptor of the present
invention Such an arrangement would allow the fastest cycle
time.
[0181] With the multi-deposition SACVD reactor of the present
invention, above described TABLE II can be re-written as below:
5 TABLE V Module FEOL/MEOL Temp. 550-950.degree. C. Cycle time 3-6
min SiN SACVD SiON SACVD SiO.sub.2 SACVD Polysilicon SACVD
[0182] Comparison between TABLES II and V clearly shows the
significant improvements brought up by the present invention. New
configurations of ICs manufacturing lines can now be
envisioned.
[0183] FIG. 5 shows the variations of the deposition rate (in
nm/mn) as a function of the pattern factor. The pattern factor is
calculated as the ratio between the etched and un-etched surfaces
across a wafer. Experiments have been conducted to deposit
Si.sub.3N.sub.4 in deep trenches for different capacitor cell
densities at 700.degree. C. for LPCVD (curves 36, 37 and 38) and at
785.degree. C. for SACVD (curve 39) for lots of wafers of different
capacity (the SACVD deposition rate has been divided by 4 to fit
Y-axis scale). A brief comparison between the profiles of curves
36/37/38 and 39 clearly shows that the deposition rate across a
LPCVD batch forbids the use of this technique for every step where
thickness control is critical. The LPCVD deposition rate varies as
a function of the pattern factor even more the number of wafers in
the batch is high, while the SACVD deposition rate is constant As
apparent in FIG. 5, the reproducibility of conventional LPCVD
techniques in EDRAM/SDRAM chip fabrication is clearly limited. In
this case, the SACVD single wafer tool is by far preferred to
insure wafer to wafer thickness uniformity control.
[0184] The deposition temperature is quite critical to the device
performance and strongly influences the thermal budget as it will
be now made apparent in FIGS. 6 and 7.
[0185] FIG. 6 is a graph showing the variations of the effective
channel length L.sub.eff (in .mu.m) around the desired nominal
value L.sub.eff=0.28 .mu.m for POR LPCVD techniques (at two
different temperatures) and the SACVD technique according to the
present invention for two lots of wafers each. Wafers were prosed
at 700.degree. C. for the two lots LP1 and at a temperature of
650.degree. C. for the two lots LP2 for approximately the same time
(3 H) using the LPCVD technique. Wafers of two lots SA1 were
processed at 785.degree. C. during 5 min using the SACVD technique.
As apparent in FIG. 6, in the latter case, the L.sub.eff variations
around the nominal value and within a lot are more limited. As
known for those skilled in the art, a reduction of the L.sub.eff
value has detrimental consequences on the device (IGFET)
reliability.
[0186] FIG. 7 is a graph showing the variations of the sheet
resistance Rs (in Ohm/square) of diffusion regions in the array
area around the desired nominal value Rs=3400 Ohm/square for POR
LPCVD techniques (at two different temperatures) and the SACVD
technique according to the present invention using the same
operating conditions as described above by reference to FIG. 6. The
sheet resistance of the two lots SA1 processed with the SACVD
technique varies much less and is more centered around the nominal
value when compared to the sheet resistance of lots LP1 and LP2
processed with the LPCVD technique.
[0187] FIGS. 6 and 7 clearly demonstrates that the role of the
thermal budget (temperature/time couple) is essential.
[0188] The new design of the multi-deposition SACVD reactor
described above significantly improves the process window and the
thermal budget required for advanced EDRAM/SDRAM silicon chips with
reduced scale, i.e. beyond 0.20 .mu.m. Moreover, the cycle time of
depositing dielectric materials with such a reactor is
significantly shortened, compared to LPCVD furnaces. It has become
an important technology parameter to date to quickly adapt a DRAM
memory manufacturing line to the fabrication of ASIC products at
reduced cost. ASIC market competitiveness depends strongly upon
short cycle times, customer satisfaction and the ability to exploit
new business opportunities in a very competitive OEM
environement.
[0189] While the invention has been particularly described with
respect a preferred embodiment thereof it should be understood by
one skilled in the art that the foregoing and other changes in form
and details may be made therein without departing from the spirit
and scope of the invention.
* * * * *