U.S. patent application number 10/982165 was filed with the patent office on 2005-10-13 for internal voltage generation circuit of semiconductor memory device.
This patent application is currently assigned to HYNIX SEMICONDUCTOR INC.. Invention is credited to Im, Jae-Hyuk, Lee, Jae-Jin.
Application Number | 20050225379 10/982165 |
Document ID | / |
Family ID | 35059992 |
Filed Date | 2005-10-13 |
United States Patent
Application |
20050225379 |
Kind Code |
A1 |
Im, Jae-Hyuk ; et
al. |
October 13, 2005 |
Internal voltage generation circuit of semiconductor memory
device
Abstract
Disclosed herein is an internal voltage generation circuit of a
semiconductor memory device which is capable of supplying voltages
of different levels to a column path & control logic and data
path & control logic in the memory device according to
different operation modes of the memory device. The column path
& control logic and data path & control logic are applied
with a normal operating voltage when they are involved in the
current operation mode of the memory device, whereas with a lower
voltage when they are not involved. Therefore, the present
invention has the effect of efficiently managing internal voltages
of the semiconductor memory device and reducing current leakage of
the memory device and, in turn, unnecessary power consumption
thereof.
Inventors: |
Im, Jae-Hyuk; (Gyunggi-do,
KR) ; Lee, Jae-Jin; (Gyunggi-do, KR) |
Correspondence
Address: |
MARSHALL, GERSTEIN & BORUN LLP
233 S. WACKER DRIVE, SUITE 6300
SEARS TOWER
CHICAGO
IL
60606
US
|
Assignee: |
HYNIX SEMICONDUCTOR INC.
Kyungki-Do
KR
|
Family ID: |
35059992 |
Appl. No.: |
10/982165 |
Filed: |
November 5, 2004 |
Current U.S.
Class: |
327/540 |
Current CPC
Class: |
G11C 11/406 20130101;
G11C 11/4074 20130101; G11C 5/14 20130101; G11C 2211/4068
20130101 |
Class at
Publication: |
327/540 |
International
Class: |
H03L 005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 12, 2004 |
KR |
2004-25060 |
Claims
What is claimed is:
1. An internal voltage generation circuit of a semiconductor memory
device comprising: reference voltage generation means for
generating a reference voltage as a control signal for internal
voltage supply; first internal voltage generation means for
generating a first internal voltage of a desired level in response
to said reference voltage from said reference voltage generation
means; and second internal voltage generation means responsive to
an enable signal resulting from a logical operation of an active
control signal indicative of an active mode and a refresh control
signal indicative of a refresh mode and said reference voltage from
said reference voltage generation means, for generating a second
internal voltage of the same level as that of said first internal
voltage when said memory device is in said active mode and a third
internal voltage of a level lower than that of said first internal
voltage when said memory device is in any other mode including said
refresh mode.
2. The internal voltage generation circuit as set forth in claim 1,
wherein said first internal voltage is supplied to a row path &
control logic in said memory device and said second and third
internal voltages are supplied to a column path & control logic
and a data path & control logic in said memory device.
3. The internal voltage generation circuit as set forth in claim 1,
wherein said first internal voltage generation means includes:
current mirror amplification means for comparing said first
internal voltage with said reference voltage to obtain a difference
therebetween and amplifying the obtained difference; and pull-up
means for raising the level of said first internal voltage to that
of said reference voltage if it becomes lower than the level of
said reference voltage.
4. The internal voltage generation circuit as set forth in claim 1,
wherein said second internal voltage generation means includes:
current mirror amplification means responsive to said enable signal
for, only when said memory device is in said active mode, comparing
said second internal voltage with said reference voltage to obtain
a difference therebetween and amplifying the obtained difference;
pull-up means for raising the level of said second internal voltage
to that of said reference voltage if it becomes lower than the
level of said reference voltage; and a MOS (Metal-Oxide
Semiconductor) diode for generating said third internal voltage of
the level lower than that of said first internal voltage at an
output terminal of said second internal voltage generation means
when said memory device is in any other mode including said refresh
mode.
5. The internal voltage generation circuit as set forth in claim 1,
wherein: said first internal voltage generation means includes:
first current mirror amplification means for comparing said first
internal voltage with said reference voltage to obtain a difference
therebetween and amplifying the obtained difference; and first
pull-up means for raising the level of said first internal voltage
to that of said reference voltage if it becomes lower than the
level of said reference voltage; and said second internal voltage
generation means includes: second current mirror amplification
means responsive to said enable signal for, only when said memory
device is in said active mode, comparing said second internal
voltage with said reference voltage to obtain a difference
therebetween and amplifying the obtained difference; second pull-up
means for raising the level of said second internal voltage to that
of said reference voltage if it becomes lower than the level of
said reference voltage; and a MOS diode for generating said third
internal voltage of the level lower than that of said first
internal voltage at an output terminal of said second internal
voltage generation means when said memory device is in any other
mode including said refresh mode.
6. An internal voltage generation circuit of a semiconductor memory
device comprising: reference voltage generation means for
generating a first reference voltage and a second reference voltage
as control signals for internal voltage supply, first internal
voltage generation means for generating a first internal voltage of
a desired level in response to said first reference voltage from
said reference voltage generation means; reference voltage transfer
means responsive to an enable signal resulting from a logical
operation of an active control signal indicative of an active mode
and a refresh control signal indicative of a refresh mode and said
first and second reference voltages from said reference voltage
generation means, for transferring said first reference voltage
when said memory device is in said active mode and said second
reference voltage when said memory device is in any other mode
including said refresh mode; and second internal voltage generation
means responsive to an output voltage from said reference voltage
transfer means for generating a second internal voltage of the same
level as that of said first internal voltage if the output voltage
is said first reference voltage and a third internal voltage of a
level lower than that of said first internal voltage if the output
voltage is said second reference voltage.
7. The internal voltage generation circuit as set forth in claim 6,
wherein said first internal voltage is supplied to a row path &
control logic in said memory device and said second and third
internal voltages are supplied to a column path & control logic
and a data path & control logic in said memory device.
8. The internal voltage generation circuit as set forth in claim 6,
wherein said first internal voltage generation means includes:
current mirror amplification means for comparing said first
internal voltage with said first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
pull-up means for raising the level of said first internal voltage
to that of said first reference voltage if it becomes lower than
the level of said first reference voltage.
9. The internal voltage generation circuit as set forth in claim 6,
wherein said second internal voltage generation means includes:
current mirror amplification means for comparing said second (or
third) internal voltage with said first (or second) reference
voltage to obtain a difference therebetween and amplifying the
obtained difference; and pull-up means for raising the level of
said second (or third) internal voltage to that of said first (or
second) reference voltage if it becomes lower than the level of
said first (or second) reference voltage.
10. The internal voltage generation circuit as set forth in claim
6, wherein: said first internal voltage generation means includes:
first current mirror amplification means for comparing said first
internal voltage with said first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
first pull-up means for raising the level of said first internal
voltage to that of said first reference voltage if it becomes lower
than the level of said first reference voltage; and said second
internal voltage generation means includes: second current mirror
amplification means for comparing said second (or third) internal
voltage with said first (or second) reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
second pull-up means for raising the level of said second (or
third) internal voltage to that of said first (or second) reference
voltage if it becomes lower than the level of said first (or
second) reference voltage.
11. An internal voltage generation circuit of a semiconductor
memory device comprising: reference voltage generation means for
generating a first reference voltage and a second reference voltage
as control signals for internal voltage supply; first internal
voltage generation means for generating a first internal voltage of
a desired level in response to said first reference voltage from
said reference voltage generation means; internal voltage transfer
means responsive to an enable signal resulting from a logical
operation of an active control signal indicative of an active mode
and a refresh control signal indicative of a refresh mode for, when
said memory device is in said active mode, receiving said first
internal voltage from an output terminal of said first internal
voltage generation means and outputting a second internal voltage
of the same level as that of said first internal voltage to an
output terminal of second internal voltage generation means; and
said second internal voltage generation means responsive to said
enable signal and said second reference voltage from said reference
voltage generation means for generating a third internal voltage of
a level lower than that of said first internal voltage when said
memory device is in any other mode including said refresh mode.
12. The internal voltage generation circuit as set forth in claim
11, wherein said first internal voltage is supplied to a row path
& control logic in said memory device and said second and third
internal voltages are supplied to a column path & control logic
and a data path & control logic in said memory device.
13. The internal voltage generation circuit as set forth in claim
11, wherein said first internal voltage generation means includes:
current mirror amplification means for comparing said first
internal voltage with said first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
pull-up means for raising the level of said first internal voltage
to that of said first reference voltage if it becomes lower than
the level of said first reference voltage.
14. The internal voltage generation circuit as set forth in claim
11, wherein said second internal voltage generation means includes:
current mirror amplification means responsive to said enable signal
for, only when said memory device is in any other mode including
said refresh mode, comparing said third internal voltage with said
second reference voltage to obtain a difference therebetween and
amplifying the obtained difference; and pull-up means for raising
the level of said third internal voltage to that of said second
reference voltage if it becomes lower than the level of said second
reference voltage.
15. The internal voltage generation circuit as set forth in claim
11, wherein: said first internal voltage generation means includes:
first current mirror amplification means for comparing said first
internal voltage with said first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
first pull-up means for raising the level of said first internal
voltage to that of said first reference voltage if it becomes lower
than the level of said first reference voltage; and said second
internal voltage generation means includes: second current mirror
amplification means responsive to said enable signal for, only when
said memory device is in any other mode including said refresh
mode, comparing said third internal voltage with said second
reference voltage to obtain a difference therebetween and
amplifying the obtained difference; and second pull-up means for
raising the level of said third internal voltage to that of said
second reference voltage if it becomes lower than the level of said
second reference voltage.
16. An internal voltage generation circuit of a semiconductor
memory device comprising: internal voltage generation means for
supplying a first internal voltage of a desired level to a row path
& control logic; and internal voltage transfer means for
receiving said first internal voltage from said internal voltage
generation means and, in response to an enable signal resulting
from a logical operation of an active control signal indicative of
an active mode and a refresh control signal indicative of a refresh
mode, supplying a second internal voltage of the same level as that
of said first internal voltage to a column path & control logic
and a data path & control logic when said memory device is in
said active mode and a third internal voltage of a level lower than
that of said first internal voltage to said column path &
control logic and data path & control logic when said memory
device is in any other mode including said refresh mode, wherein
said internal voltage transfer means includes: a MOS transistor for
supplying said second internal voltage of the same level as that of
said first internal voltage in response to said enable signal; and
a MOS diode for dropping said first internal voltage by a
predetermined threshold voltage thereof and supplying the resulting
voltage as said third internal voltage.
17. The internal voltage generation circuit as set forth in claim
16, wherein said MOS transistor is a PMOS (P-channel Metal-Oxide
Semiconductor) transistor, said PMOS transistor being turned on
when said active control signal goes high in level and said refresh
control signal goes low in level.
18. The internal voltage generation circuit as set forth in claim
16, wherein said MOS diode is an NMOS (N-channel Metal-Oxide
Semiconductor) diode.
Description
[0001] This application relies for priority upon Korean Patent
Application No. 2004-0025060 filed on Apr. 12, 2004, the contents
of which are herein incorporated by reference in their
entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to an internal voltage
generation circuit of a semiconductor memory device, and more
particularly to an internal voltage generation circuit for
supplying voltages of different levels to a specific area in a
semiconductor memory device according to whether the specific area
is involved in the current operation mode of the memory device, so
as to reduce current leakage and power consumption of the memory
device.
[0004] 2. Description of the Related Art
[0005] FIG. 1 is a general conceptual diagram of a semiconductor
memory device. As shown in this drawing, the semiconductor memory
device basically comprises a cell array, a row path & control
logic 11, a column path & control logic 15, and a data path
& control logic 14. Among these, the row path & control
logic 11, the column path & control logic 15 and the data path
& control logic 14 are typically called a peri area in the
gross.
[0006] FIG. 2 is a conceptual diagram of an internal voltage
generation circuit of a conventional semiconductor memory device.
As shown in this drawing, if an external voltage Vcc is applied to
the memory device, then internal voltages necessary for the
operation of the memory device are internally generated in the
memory device. These internal voltages may be, for example, a high
voltage Vpp to a word line, a voltage Vcore to a cell and bit line
sense amplifier, a high voltage source Vperi to a peri area,
etc.
[0007] In the conventional memory device, once the internally
generated voltage Vperi is determined in level, it is applied in
common to all components in the peri area That is, once being
generated, the voltage Vperi of the same level is applied to all of
a row path & control logic, column path & control logic and
data path & control logic in the peri area
[0008] Recently, in a semiconductor memory device, the external
voltage Vcc has gradually become lower in level as the memory
device has become higher in speed and lower in power. As a result,
the internal voltages for the internal operation of the memory
device have become lower in level, too, resulting in there being a
need to reduce a threshold voltage Vt of a transistor so as to
secure the operation margin of the memory device. However, as the
threshold voltage has become lower in level, the memory device has
increased in current leakage and, in turn, in power consumption For
this reason, there has been a need to reduce the current leakage
resulting from the fact that the external voltage Vcc is lower in
level.
[0009] However, in the conventional semiconductor memory device, as
mentioned above, the voltage of the same level is supplied to the
entire peri area irrespective of the operation mode of the memory
device, thereby making it impossible to control the voltage level
based on the operation mode of the memory device. For this reason,
there is no room to reduce power consumption of the memory device
by preventing unnecessary current leakage thereof.
[0010] In detail, in a semiconductor memory device, when the memory
device is in an active mode, all components of a peri area are
involved in the active mode. However, when the memory device is in
a standby mode including a refresh mode, only a row path &
control logic in the peri area is involved in the standby mode, but
the other components in the peri ea, or a column path & control
logic and a datapath & control logic, are not involved therein
Accordingly, in order to reduce unnecessary current leakage of the
memory device, it is required to supply a voltage of a desired
level to only the involved components and a voltage of a lower
level to the other components, respectively. However, the
conventional semiconductor memory device is designed to supply the
voltage of the same level to the entire peri area regardless of the
operation mode thereof resulting in inevitable occurrence of
unnecessary current leakage as mentioned above.
SUMMARY OF THE INVENTION
[0011] Therefore, the present invention has been made in view of
the above problems and it is an object of the present invention to
provide an internal voltage generation circuit of a semiconductor
memory device which is capable of, according to the current
operation mode of the memory device, supplying a voltage of a
desired level to components in a peri area, involved in the
operation mode, and a voltage of a lower level to the other
components in the peri area, not involved in the operation mode,
respectively, thereby reducing current leakage and power
consumption of the memory device.
[0012] In accordance with an aspect of the present invention, the
above and other objects can be accomplished by the provision of an
internal voltage generation circuit of a semiconductor memory
device comprising: reference voltage generation means for
generating a reference voltage as a control signal for internal
voltage supply; fast internal voltage generation means for
generating a first internal voltage of a desired level in response
to the reference voltage from the reference voltage generation
means; and second internal voltage generation means responsive to
an enable signal resulting from a logical operation of an active
control signal indicative of an active mode and a refresh control
signal indicative of a refresh mode and the reference voltage from
the reference voltage generation means, for generating a second
internal voltage of the same level as that of the first internal
voltage when the memory device is in the active mode and a third
internal voltage of a level lower than that of the fist internal
voltage when the memory device is in any other mode including the
refresh mode.
[0013] Preferably, the first internal voltage is supplied to a row
path & control logic in the memory device and the second and
third internal voltages are supplied to a column path & control
logic and a data path & control logic in the memory device.
[0014] Preferably, the fist internal voltage generation means
includes: current mirror amplification means for comparing the
first internal voltage with the reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
pull-up means for raising the level of the first internal voltage
to that of the reference voltage if it becomes lower than the level
of the reference voltage.
[0015] Preferably, the second internal voltage generation means
includes: current minor amplification means responsive to the
enable signal for, only when the memory device is in the active
mode, comparing the second internal voltage with the reference
voltage to obtain a difference therebetween and amplifying the
obtained difference; pull-up means for raising the level of the
second internal voltage to that of the reference voltage if it
becomes lower than the level of the reference voltage; and a MOS
(Metal-Oxide Semiconductor) diode for generating the third internal
voltage of the level lower than that of the first internal voltage
at an output terminal of the second internal voltage generation
means when the memory device is in any other mode including the
refresh mode.
[0016] The first internal voltage generation means may include:
first current mirror amplification means for comparing the first
internal voltage with the reference voltage to obtain a difference
therebetween and amplifying the obtained difference; and first
pull-up means for rising the level of the first internal voltage to
that of the reference voltage if it becomes lower than the level of
the reference voltage; and the second internal voltage generation
means may include: second current minor amplification means
responsive to the enable signal for, only when the memory device is
in the active mode, comparing the second internal voltage with the
reference voltage to obtain a difference therebetween and
amplifying the obtained difference; second pull-up means for
raising the level of the second internal voltage to that of the
reference voltage if it becomes lower than the level of the
reference voltage; and a MOS diode for generating the third
internal voltage of the level lower than that of the first internal
voltage at an output terminal of the second internal voltage
generation means when the memory device is in any other mode
including the refresh mode.
[0017] In accordance with another aspect of the present invention,
there is provided an internal voltage generation circuit of a
semiconductor memory device comprising: reference voltage
generation means for generating a first reference voltage and a
second reference voltage as control signals for internal voltage
supply, first internal voltage generation means for generating a
first internal voltage of a desired level in response to the first
reference voltage from the reference voltage generation means;
reference voltage transfer means responsive to an enable signal
resulting from a logical operation of an active control signal
indicative of an active mode and a refresh control signal
indicative of a refresh mode and the first and second reference
voltages from the reference voltage generation means, for
transferring the first reference voltage when the memory device is
in the active mode and the second reference voltage when the memory
device is in any other mode including the refresh mode; and second
internal voltage generation means responsive to an output voltage
from the reference voltage transfer means for generating a second
internal voltage of the same level as that of the first internal
voltage if the output voltage is the first reference voltage and a
third internal voltage of a level lower than that of the first
internal voltage if the output voltage is the second reference
voltage.
[0018] Preferably, the first internal voltage is supplied to a row
path & control logic in the memory device and the second and
third internal voltages are supplied to a column path & control
logic and a data path & control logic in the memory device.
[0019] Preferably, the first internal voltage generation means
includes: current mirror amplification means for comparing the
first internal voltage with the first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
pull-up means for raising the level of the first internal voltage
to that of the first reference voltage if it becomes lower than the
level of the first reference voltage.
[0020] Preferably, the second internal voltage generation means
includes: current minor amplification means for comparing the
second (or third) internal voltage with the first (or second)
reference voltage to obtain a difference therebetween and
amplifying the obtained difference; and pull-up means for raising
the level of the second (or third) internal voltage to that of the
first (or second) reference voltage if it becomes lower than the
level of the first (or second) reference voltage.
[0021] The first internal voltage generation means may include:
first current mirror amplification means for comparing the fist
internal voltage with the first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
first pull-up means for raising the level of the first internal
voltage to that of the first reference voltage if it becomes lower
than the level of the first reference voltage; and the second
internal voltage generation means may include: second current
mirror amplification means for comparing the second (or third)
internal voltage with the first (or second) reference voltage to
obtain a difference therebetween and amplifying the obtained
difference; and second pull-up means for raising the level of the
second (or third) internal voltage to that of the first (or second)
reference voltage if it becomes lower than the level of the first
(or second) reference voltage.
[0022] In accordance with a further aspect of the present
invention, there is provided an internal voltage generation circuit
of a semiconductor memory device comprising: reference voltage
generation means for generating a first reference voltage and a
second reference voltage as control signals for internal voltage
supply, first internal voltage generation means for generating a
first internal voltage of a desired level in response to the first
reference voltage from the reference voltage generation means;
internal voltage transfer means responsive to an enable signal
resulting from a logical operation of an active control signal
indicative of an active mode and a refresh control signal
indicative of a refresh mode for, when the memory device is in the
active mode, receiving the first internal voltage from an output
terminal of the first internal voltage generation means and
outputting a second internal voltage of the same level as that of
the first internal voltage to an output terminal of second internal
voltage generation means; and the second internal voltage
generation means responsive to the enable signal and the second
reference voltage from the reference voltage generation means for
generating a third internal voltage of a level lower than that of
the first internal voltage when the memory device is in any other
mode including the refresh mode.
[0023] Preferably, the first internal voltage is supplied to a row
path & control logic in the memory device and the second and
third internal voltages are supplied to a column path & control
logic and a data path & control logic in the memory device.
[0024] Preferably, the first internal voltage generation means
includes: current mirror amplification means for comparing the
first internal voltage with the first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
pull-up means for raising the level of the first internal voltage
to that of the first reference voltage if it becomes lower than the
level of the first reference voltage.
[0025] Preferably, the second internal voltage generation means
includes: current mirror amplification means responsive to the
enable signal for, only when the memory device is in any other mode
including the refresh mode, comparing the third internal voltage
with the second reference voltage to obtain a difference
therebetween and amplifying the obtained difference; and pull-up
means for raising the level of the third internal voltage to that
of the second reference voltage if it becomes lower than the level
of the second reference voltage.
[0026] The first internal voltage generation means may include:
first current mirror amplification means for comparing the first
internal voltage with the first reference voltage to obtain a
difference therebetween and amplifying the obtained difference; and
first pull-up means for raising the level of the first internal
voltage to that of the first reference voltage if it becomes lower
than the level of the first reference voltage; and the second
internal voltage generation means may include: second current
mirror amplification means responsive to the enable signal for,
only when the memory device is in any other mode including the
refresh mode, comparing the third internal voltage with the second
reference voltage to obtain a difference therebetween and
amplifying the obtained difference; and second pull-up means for
raising the level of the third internal voltage to that of the
second reference voltage if it becomes lower than the level of the
second reference voltage.
[0027] In accordance with yet another aspect of the present
invention, there is provided an internal voltage generation circuit
of a semiconductor memory device comprising: internal voltage
generation means for supplying a fist internal voltage of a desired
level to a row path & control logic; and internal voltage
transfer means for receiving the first internal voltage from the
internal voltage generation means and, in response to an enable
signal resulting from a logical operation of an active control
signal indicative of an active mode and a refresh control signal
indicative of a refresh mode, supplying a second internal voltage
of the same level as that of the first internal voltage to a column
path & control logic and a data path & control logic when
the memory device is in the active mode and a third internal
voltage of a level lower than that of the first internal voltage to
the column path & control logic and data path & control
logic when the memory device is in any other mode including the
refresh mode, wherein the internal voltage transfer means includes:
a MOS transistor for supplying the second internal voltage of the
same level as that of the first internal voltage in response to the
enable signal; and a MOS diode for dropping the first internal
voltage by a predetermined threshold voltage thereof and supplying
the resulting voltage as the third internal voltage.
[0028] Preferably, the MOS transistor is a PMOS (P-channel Metal
Oxide Semiconductor) transistor, which is turned on when the active
control signal goes high in level and the refresh control signal
goes low in level.
[0029] The MOS diode maybe an NMOS (N-channel Metal Oxide
Semiconductor) diode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above and other objects, features and other advantages
of the present invention will be more clearly understood from the
following detailed description taken in conjunction with the
accompanying drawings, in which:
[0031] FIG. 1 is a general conceptual diagram of a semiconductor
memory device;
[0032] FIG. 2 is a conceptual diagram of an internal voltage
generation circuit of a conventional semiconductor memory
device;
[0033] FIG. 3 is a conceptual diagram of an internal voltage
generation circuit of a semiconductor memory device according to
the present invention;
[0034] FIG. 4A is a circuit diagram showing the configuration of a
first embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention;
[0035] FIG. 4B is a circuit diagram showing the configuration of a
second embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention;
[0036] FIG. 4C is a circuit diagram showing the configuration of a
third embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention;
and
[0037] FIG. 5 is a circuit diagram showing the configuration of a
fourth embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0038] FIG. 3 is a conceptual diagram of an internal voltage
generation circuit of a semiconductor memory device according to
the present invention. As shown in this drawing, the internal
voltage generation circuit according to the present invention
comprises a first Vperi generator 31 for generating an internal
voltage Vperi_1 to a row path & control logic in response to an
external voltage Vcc applied thereto. The internal voltage Vperi_1
from the first Vperi generator 31 is always applied to the row path
& control logic since an operating voltage is always necessary
therefor. The internal voltage generation circuit according to the
present invention further comprises a second Vperi generator 32 for
generating an internal voltage to a column path & control logic
and a data path & control logic in response to the external
voltage Vcc applied thereto. The column path & control logic
and the data path & control logic are selectively applied with
the internal voltage from the second Vperi generator 32 since
whether they are involved in the current operation mode of the
memory device or not is determined according to the operation
mode.
[0039] Preferably, the second Vperi generator 32 determines the
level of its output voltage in response to an active control signal
Active and a refresh control signal Refresh inputted thereto. That
is, where the memory device is in an active mode, the second Vperi
generator 32 outputs an internal voltage Vperi_2 of the same level
as that of the internal voltage Vperi_1. However, in the case where
the memory device is in a standby mode including a refresh mode in
which the column path & control logic and the data path &
control logic are not involved in the operation of the memory
device, the second Vperi generator 32 outputs an internal voltage
Vperi_3 of a level lower than that of the internal voltage
Vperi_1.
[0040] FIG. 4A is a circuit diagram showing the configuration of a
first embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention. As
shown in this drawing, the internal voltage generation circuit
according to the first embodiment comprises a reference voltage
generator 100 for generating a reference voltage Vr1 to be used as
a control signal for internal voltage supply, a first Vperi
generator 110 for generating an internal voltage Vperi_1 of a
constant level in response to the reference voltage Vr1 from the
reference voltage generator 100, and a second Vperi generator 120
responsive to an enable signal resulting from a logical operation
of an active control signal Active indicative of an active mode and
a refresh control signal Refresh indicative of a refresh mode and
the reference voltage Vr1 from the reference voltage generator 100,
for generating an internal voltage Vperi_2 of the same level as
that of the internal voltage Vperi_1 when the memory device is in
the active mode and an internal voltage Vperi_3 of a level lower by
a predetermined value than that of the internal voltage Vperi_1
when the memory device is in any other mode including the refresh
mode.
[0041] A detailed description will hereinafter be given of the
operation of the internal voltage generation circuit with the
above-stated configuration according to the first embodiment.
[0042] First, the reference voltage Vr1 for the internal voltage
Vperi_1 is generated by the reference voltage generator 100 and
applied to a gate of an NMOS (N-channel Metal-Oxide Semiconductor)
transistor N11 of a first current minor amplifier 111 in the first
Vperi generator 110. At this time, since an NMOS transistor N15 is
always applied with an external voltage Vcc at its gate, it is
always kept ON, thereby allowing the first current minor amplifier
111 to be always operated. As a result, the internal voltage
Vperi_1 of the constant level is outputted at a gate of an NMOS
transistor N12, or an output terminal of the first Vperi generator
110, according to the reference voltage Vr1. This internal voltage
Vperi_1 is applied as a high voltage source to a row path &
control logic.
[0043] The first current mirror amplifier 111 is operated in the
following manner. If the reference voltage Vr1 is applied to the
gate of the NMOS transistor N11 under the condition that the NMOS
transistor N15 remains ON, then the internal voltage Vperi_1 of the
constant level is outputted at the gate of the NMOS transistor N12.
At this time, if the internal voltage Vperi_1 becomes lower in
level than the reference voltage Vr1, a node B becomes relatively
higher in voltage level than a node A. In this case, because two
PMOS (P-channel Metal-oxide Semiconductor) transistors P11 and P12
are connected in common to the node B at their gates, they increase
in resistance, thereby causing the voltage level at the node A to
become lower than the previous one. As a result, a PMOS transistor
P15 becomes lower in gate voltage level, thereby causing a larger
amount of current to flow from the external voltage Vcc so as to
raise the level of the internal voltage Vperi_1. On the contrary,
if the internal voltage Vperi_1 becomes higher in level than the
reference voltage Vr1, the node B becomes relatively lower in
voltage level than the node A. In this case, the two PMOS
transistors P11 and P12 decrease in resistance, so the voltage
level at the node A becomes higher than the previous one. As a
result, the PMOS transistor P15 becomes higher in gate voltage
level, thereby causing a smaller amount of current to flow from the
external voltage Vcc, which leads to a reduction in the level of
the internal voltage Vperi_1. Consequently, the internal voltage
Vperi_1 of the constant level is generated and outputted at the
output terminal of the first Vperi generator 110.
[0044] On the other hand, the second Vperi generator 120 includes a
second current mirror amplifier 121 designed in such a manner that
a PMOS transistor P17 and an NMOS transistor N16 thereof are
controlled by a control signal from an inverter IV12. The active
control signal Active goes high in level in a read/write mode or
the refresh mode to select one word line in the memory device. The
refresh control signal Refresh goes high in level when the refresh
mode is executed in response to an auto-refresh command, a
self-refresh command or an external command.
[0045] As shown in FIG. 4A, an inverted version of the refresh
control signal Refresh and the active control signal Active are
inputted to the input of a NAND gate ND10. The NAND gate ND10
outputs a low-level signal when the inputted signals are both high
in level. In this regard, only when the memory device is in the
active mode, the output of the NAND gate ND10 is kept low in level.
As a result, only when the memory device is in the active mode, the
output of the inverter IV12 goes high in level to turn the PMOS
transistor P17 on and the NMOS transistor N16 off, thereby allowing
the second current minor amplifier 121 to be normally operated.
Consequently, in this case, the second current minor amplifier 121
is operated in the same manner as the first current mirror
amplifier 111 to output the internal voltage Vperi_2 of the same
level as that of the internal voltage Vperi_1 at an output terminal
of the second Vperi generator 120. This internal voltage Vperi_2 is
supplied to a column path & control logic and a data path &
control logic.
[0046] On the other hand, in the case where the memory device is in
any other mode including the refresh mode, for example, a standby
mode, the output of the inverter IV12 goes low in level to turn the
PMOS transistor P17 on and the NMOS transistor N16 off, so the
second current minor amplifier 121 is not operated However, the
internal voltage Vperi_1 generated by the first Vperi generator 110
is inputted to a MOS (Metal-Oxide Semiconductor) diode D10 so that
the internal voltage Vperi_3 can be outputted at the output
terminal of the second Vperi generator 120. Namely, the internal
voltage Vperi_1 is inputted to the MOS diode D10 and then outputted
as the internal voltage Vperi_3. At this time, the internal voltage
Vperi_3 has a level lower by a threshold voltage Vt of the MOS
diode D10 than that of the internal voltage Vperi_1 inputted to the
MOS diode D10. Accordingly, by adjusting the threshold voltage Vt
of the diode D10, an internal voltage Vperi_3 of a desired level
can be generated and supplied to the column path & control
logic and the data path & control logic in the standby
mode.
[0047] In brief, the internal voltage generation circuit according
to the first embodiment as described above always supplies an
internal voltage Vperi_1 of a constant level to the row path &
control logic, and supplies an internal voltage Vperi_2 of the same
level as that of the internal voltage Vperi_1 to the column path
& control logic and the data path & control logic when the
memory device is in the active mode and an internal voltage Vperi_3
of a level lower by a predetermined threshold voltage Vt than that
of the internal voltage Vperi_1 to the column path & control
logic and the data path & control logic when the memory device
is in the standby mode including the refresh mode. Therefore, the
internal voltage generation circuit according to the first
embodiment can reduce unnecessary current leakage and power
consumption of the memory device by adjusting the supply level of a
specific internal voltage according to the operation mode of the
memory device.
[0048] FIG. 4B is a circuit diagram showing the configuration of a
second embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention. As
shown in this drawing, the internal voltage generation circuit
according to the second embodiment comprises a reference voltage
generator 200 for generating a reference voltage Vr1 and a
reference voltage Vr2 to be used as control signals for internal
voltage supply, a first Vperi generator 210 for generating an
internal voltage Vperi_1 of a constant level in response to the
reference voltage Vr1 from the reference voltage generator 200, a
reference voltage transfer circuit 203 responsive to an enable
signal resulting from a logical operation of an active control
signal Active and a refresh control signal Refresh and the
reference Voltages Vr1 and Vr2 from the reference voltage generator
200, for transferring the reference voltage Vr1 when the memory
device is in an active mode and the reference voltage Vr2 when the
memory device is in any other mode including a refresh mode, and a
second Vperi generator 220 responsive to an output voltage from the
reference voltage transfer circuit 203 for generating an internal
voltage Vperi_2 of the same level as that of the internal voltage
Vperi_1 if the output voltage is the reference voltage Vr1 and an
internal voltage Vperi_3 of a level lower by a predetermined value
than that of the internal voltage Vperi_1 if the output voltage is
the reference voltage Vr2. Here, the active control signal Active
and the refresh control signal Refresh are the same as those used
in the first embodiment
[0049] A detailed description will hereinafter be given of the
operation of the internal voltage generation circuit with the
above-stated configuration according to the second embodiment
[0050] First, the reference voltage Vr1 for the internal voltage
Vperi_1 is generated by the reference voltage generator 200 and
applied to a gate of an NMOS transistor N21 of a first current
minor amplifier 211 in the first Vperi generator 210. Then, the
first current mirror amplifier 211 is operated in the same manner
as the first current minor amplifier 111 in the first embodiment to
output the internal voltage Vperi_1 of the constant level at an
output terminal of the first Vperi generator 210 according to the
reference voltage Vr1. This internal voltage Vperi_1 is applied as
a high voltage source to a row path & control logic.
[0051] On the other hand, the second Vperi generator 220 includes a
second current mirror amplifier 221 designed in such a manner that
it is controlled by the active control signal Active and refresh
control signal Refresh applied to the reference voltage transfer
circuit 203, in order to supply a specific internal voltage to a
column path & control logic and a data path & control
logic. That is, since an NMOS transistor N26 is always applied with
an external voltage Vcc at its gate, it is always kept ON, thereby
allowing the second current mirror amplifier 221 to be always
operated. However, a voltage to a gate of an NMOS transistor N23 is
controlled by the active control signal Active and the refresh
control signal Refresh.
[0052] In a similar manner to in the first embodiment, only when
the memory device is in the active mode, the output of a NAND gate
ND20 goes low in level and the output of an inverter IV22 thus goes
high in level. In this case, a transfer gate T21 is turned on and a
transfer gate T22 is turned off, thereby causing the reference
voltage Vr1 to be applied to the gate of the NMOS transistor N23.
As a result, the second current mirror amplifier 221 is operated in
the same manner as the first current mirror amplifier 211 to output
the internal voltage Vperi_2 of the same level as that of the
internal voltage Vperi_1 at an output terminal of the second Vperi
generator 220. This internal voltage Vperi_2 is supplied to the
column path & control logic and the data path & control
logic.
[0053] On the other hand, in the case where the memory device is in
any other mode including the refresh mode, for example, a standby
mode, the output of the NAND gate ND20 goes high in level and the
output of the inverter IV22 thus goes low in level. In this case,
the transfer gate T21 is turned off and the transfer gate T22 is
turned on, thereby causing the reference voltage Vr2 to be applied
to the gate of the NMOS transistor N23. As a result, the second
current minor amplifier 221 is operated to output the internal
voltage Vperi_3 of the level lower by the predetermined value than
that of the internal voltage Vperi_1 at the output terminal of the
second Vperi generator 220 according to the reference voltage Vr2.
This internal, voltage Vperi_3 is supplied to the column path &
control logic and the data path & control logic.
[0054] In brief, similarly to the first embodiment, the internal
voltage generation circuit according to the second embodiment as
described above can reduce unnecessary current leakage and power
consumption of the memory device by adjusting the supply level of a
specific internal voltage according to the operation mode of the
memory device.
[0055] FIG. 4C is a circuit diagram showing the configuration of a
third embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention. As
shown in this drawing, the internal voltage generation circuit
according to the third embodiment comprises a reference voltage
generator 300 for generating a reference voltage Vr1 and a
reference voltage Vr2 to be used as control signals for internal
voltage supply, a first Vperi generator 310 for generating an
internal voltage Vperi_1 of a constant level in response to the
reference voltage Vr1 from the reference voltage generator 300, and
an internal voltage transfer circuit 330 responsive to an enable
signal resulting from a logical operation of an active control
signal Active and a refresh control signal Refresh for, when the
memory device is in an active mode, receiving the internal voltage
Vperi_1 from an output terminal of the first Vperi generator 310
and outputting an internal voltage Vperi_2 of the same level as
that of the internal voltage Vperi_1 to an output terminal of a
second Vperi generator 320. The second Vperi generator 320 is
responsive to the enable signal and the reference, voltage Vr2 from
the reference voltage generator 300 to generate an internal voltage
Vperi_3 of a level lower by a predetermined value than that of the
internal voltage Vperi_1 when the memory device is in any other
mode including a refresh mode. Here, the active control signal
Active and the refresh control signal Refresh are the same as those
used in the first embodiment.
[0056] A detailed description will hereinafter be given of the
operation of the internal voltage generation circuit with the
above-stated configuration according to the third embodiment First,
the reference voltage Vr1 for the internal voltage Vperi_1 is
generated by the reference voltage generator 300 and applied to a
gate of an NMOS transistor N31 of a first current mirror amplifier
311 in the fist Vperi generator 310. Then, the first current minor
amplifier 311 is operated in the same manner as the first current
minor amplifier 111 in the first embodiment to output the internal
voltage Vperi_1 of the constant level at the output terminal of the
first Vperi generator 310 according to the reference voltage Vr1.
This internal voltage Vperi_1 is applied as a high voltage source
to a row path & control logic.
[0057] On the other hand, in order to supply a specific internal
voltage to a column path & control logic and a data path &
control logic, a second current mirror amplifier 321 in the second
Vperi generator 320 and the internal voltage transfer circuit 330
are controlled by the active control signal Active and refresh
control signal Refresh which are the same as those in the first
embodiment. Namely, only when the memory device is in the active
mode, the output of a NAND gate ND30 goes low in level. In this
case, a PMOS transistor P37 is turned on and an NMOS transistor N36
is turned off, so the second current minor amplifier 321 is not
operated. However, a transfer gate T30 of the internal voltage
transfer circuit 330 is turned on to output the internal voltage
Vperi_2 of the same level as that of the internal voltage Vperi_1
at the output terminal of the second Vperi generator 320. This
internal voltage Vperi_2 is supplied to the column path &
control logic and the data path & control logic.
[0058] On the other hand, when the memory device is in any other
mode including the refresh mode, for example, a standby mode, the
output of the NAND gate ND20 goes high in level. In this case, the
transfer gate T31 is turned off, the PMOS transistor P37 is turned
off and the NMOS transistor N36 is turned on, so the second current
minor amplifier 321 is normally operated. As a result, since the
reference voltage Vr2 is applied to a gate of an NMOS transistor
N33, the second current mirror amplifier 221 is operated to output
the internal voltage Vperi_3 of the level lower by the
predetermined value than that of the internal voltage Vperi_1 at
the output terminal of the second Vperi generator 220 according to
the reference voltage Vr2. This internal voltage Vperi_3 is
supplied to the column path & control logic and the data path
& control logic.
[0059] Therefore, similarly to the first and second embodiments,
the internal voltage generation circuit according to the third
embodiment as described above can reduce unnecessary current
leakage and power consumption of the memory device by adjusting the
supply level of a specific internal voltage according to the
operation mode of the memory device.
[0060] FIG. 5 is a circuit diagram showing the configuration of a
fourth embodiment of the internal voltage generation circuit of the
semiconductor memory device according to the present invention. As
shown in this drawing, the internal voltage generation circuit
according to the fourth embodiment comprises a Vperi generator 510
for supplying an internal voltage Vperi_1 of a constant level to a
row path & control logic, and an internal voltage transfer
circuit 520 for receiving the internal voltage Vperi_1 from the
Vperi generator 510 and, in response to an enable signal resulting
from a logical operation of an active control signal Active and a
refresh control signal Refresh, supplying an internal voltage
Vperi_2 of the same level as that of the internal voltage Vperi_1
to a column path & control logic and a data path & control
logic when the memory device is in an active mode and an internal
voltage Vperi_3 of a level lower by a predetermined value than that
of the internal voltage Vperi_1 to the column path & control
logic and data path & control logic when the memory device is
in any other mode including a refresh mode. The internal voltage
transfer circuit 520 includes a PMOS transistor P50 for supplying
the internal voltage Vperi_2 in response to the enable signal, and
a MOS diode D50 for dropping the internal voltage Vperi_1 by a
predetermined threshold voltage Vt thereof and supplying the
resulting voltage as the internal voltage Vperi_3. Here, the active
control signal Active and the refresh control signal Refresh are
the same as those used in the first embodiment.
[0061] A detailed description will hereinafter be given of the
operation of the internal voltage generation circuit with the
above-stated configuration according to the fourth embodiment. As
shown in FIG. 5, in a different manner from the first to third
embodiments, the fourth embodiment employs only one internal
voltage generator, or the Vperi generator 510.
[0062] First, the internal voltage Vperi_1 is supplied as a high
voltage source to the row path & control logic that must be
applied with a constant operating voltage irrespective of the
operation mode of the memory device. On the other hand, when the
memory device is in the active mode, the active control signal
Active goes high in level and the refresh control signal Refresh
goes low in level, thereby causing the output of a NAND gate ND50
to become low in level. As a result, the PMOS transistor P50 is
turned on to supply the internal voltage Vperi_2 of the same level
as that of the internal voltage Vperi_1 to the column path &
control logic and the data path & control logic. On the
contrary, when the memory device is in any other mode including the
refresh mode, for example, a standby mode, the output of the NAND
gate ND50 becomes high in level and the PMOS transistor P50 is thus
turned off. As a result, the internal voltage Vperi_3 of the level
that is lower by the threshold voltage Vt of the MOS diode D50 than
that of the internal voltage Vperi_1 is supplied to the column path
& control logic and the data path & control logic.
[0063] Therefore, through the use of only one internal voltage
generator, the internal voltage generation circuit according to the
fourth embodiment as described above can reduce unnecessary current
leakage and power consumption of the memory device by adjusting the
supply level of a specific internal voltage according to the
operation mode of the memory device, similarly to the first to
third embodiments.
[0064] As apparent from the above description, the present
invention provides an internal voltage generation circuit of a
semiconductor memory device which is capable of supplying voltages
of different levels to a column path & control logic and data
path & control logic in the memory device according to
different operation modes of the memory device. The column path
& control logic and data path & control logic are applied
with a normal operating voltage when they are involved in the
current operation mode of the memory device, whereas with a lower
voltage when they are not involved. Therefore, the present
invention has the effect of efficiently managing internal voltages
of the semiconductor memory device and reducing current leakage of
the memory device and, in turn, unnecessary power consumption
thereof.
[0065] Although the preferred embodiments of the present invention
have been disclosed for illustrative purposes, those skilled in the
art will appreciate tat various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying
claims.
* * * * *