U.S. patent application number 11/141124 was filed with the patent office on 2005-10-06 for high precision analog to digital converter.
Invention is credited to Li, Guoxing, Liu, Liusheng.
Application Number | 20050219105 11/141124 |
Document ID | / |
Family ID | 29399917 |
Filed Date | 2005-10-06 |
United States Patent
Application |
20050219105 |
Kind Code |
A1 |
Liu, Liusheng ; et
al. |
October 6, 2005 |
High precision analog to digital converter
Abstract
An analog to digital converter may include an input switch array
configured to alternately sample a first and a second input signal
to a first and a second input capacitor during two different sample
time intervals, an integrator having a first and second integration
capacitor, and a cross switch array coupled to the input switch
array and the integrator. The cross switch array may be configured
to alternately transfer charges from the first and second input
capacitors to the first and second integration capacitors during
two different transfer time intervals. A system including an analog
to digital converter consistent with an embodiment and an
associated method of sampling and transferring charges in an analog
to digital converter are also provided.
Inventors: |
Liu, Liusheng; (San Jose,
CA) ; Li, Guoxing; (Sunnyvale, CA) |
Correspondence
Address: |
GROSSMAN, TUCKER, PERREAULT & PFLEGER, PLLC
55 SOUTH COMMERICAL STREET
MANCHESTER
NH
03101
US
|
Family ID: |
29399917 |
Appl. No.: |
11/141124 |
Filed: |
May 31, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11141124 |
May 31, 2005 |
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10838563 |
May 4, 2004 |
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10838563 |
May 4, 2004 |
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10142503 |
May 10, 2002 |
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6744394 |
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Current U.S.
Class: |
341/155 |
Current CPC
Class: |
H03M 3/456 20130101;
H03M 3/34 20130101; H03M 3/43 20130101 |
Class at
Publication: |
341/155 |
International
Class: |
H03M 001/12 |
Claims
What is claimed is:
1. An analog to digital converter comprising: an input switch array
configured to alternately sample a first and a second input signal
to a first and a second input capacitor during two different sample
time intervals; an integrator having a first and second integration
capacitor; and a cross switch array coupled to said input switch
array and said integrator, said cross switch array configured to
alternately transfer charges from said first and second input
capacitors to said first and second integration capacitors during
two different transfer time intervals.
2. The analog to digital converter of claim 1, wherein a first
transfer time interval of said two different transfer time
intervals occurs after a first sample time interval of said two
different sample time intervals, and a second transfer time
interval of said two different transfer time intervals occurs after
a second sample time interval of said two different sample time
intervals.
3. The analog to digital converter of claim 2, wherein said input
switch array is configured to provide a first sample path to said
first input capacitor from said first input signal and a second
sample path to said second input capacitor from said second input
signal during said first sample time interval.
4. The analog to digital converter of claim 3, wherein said input
switch array is further configured to provide a third sample path
to said second input capacitor from said first input signal and a
fourth sample path to said first input capacitor from said second
input signal during said second sample time interval.
5. The analog to digital converter of claim 2, wherein said cross
switch array is configured to provide a first transfer path to said
first integration capacitor from said first input capacitor and a
second transfer path to said second integration capacitor from said
second input capacitor during said first transfer time
interval.
6. The analog to digital converter of claim 5, wherein said cross
switch array is further configured to provide a third transfer path
to said second integration capacitor from said first input
capacitor and a fourth transfer path to said first integration
capacitor from said second input capacitor during said second
transfer time interval.
7. The analog to digital converter of claim 2, wherein said second
transfer time interval is after said second sample time interval,
and said second sample time interval is after said first transfer
time interval, and said first transfer time interval is after said
first sample time interval, and said first and second sample time
intervals and said first and second transfer time interval are
non-overlapping.
8. A system comprising: a battery; a sensor configured to sense a
current to or from said battery and provide a first and second
analog signal representative of said current; an analog to digital
converter configured to accept said first and second analog signals
and provide a digital signal representative of a difference between
said first and second analog signals, said analog to digital
converter comprising: an input switch array configured to
alternately sample said first and second analog signals to a first
and a second input capacitor during two different sample time
intervals; an integrator having a first and second integration
capacitor; and a cross switch array coupled to said input switch
array and said integrator, said cross switch array configured to
alternately transfer charges from said first and second input
capacitors to said first and second integration capacitors during
two different transfer time intervals.
9. The system of claim 8, wherein a first transfer time interval of
said two different transfer time intervals occurs after a first
sample time interval of said two different sample time intervals,
and a second transfer time interval of said two different transfer
time intervals occurs after a second sample time interval of said
two different sample time intervals.
10. The system of claim 9, wherein said input switch array is
configured to provide a first sample path to said first input
capacitor from said first analog signal and a second sample path to
said second input capacitor from said second analog signal during
said first sample time interval.
11. The system of claim 10, wherein said input switch array is
further configured to provide a third sample path to said second
input capacitor from said first analog signal and a fourth sample
path to said first input capacitor from said second analog signal
during said second sample time interval.
12. The system of claim 9, wherein said cross switch array is
configured to provide a first transfer path to said first
integration capacitor from said first input capacitor and a second
transfer path to said second integration capacitor from said second
input capacitor during said first transfer time interval.
13. The system of claim 12, wherein said cross switch array is
further configured to provide a third transfer path to said second
integration capacitor from said first input capacitor and a fourth
transfer path to said first integration capacitor from said second
input capacitor during said second transfer time interval.
14. The system of claim 9, wherein said second transfer time
interval is after said second sample time interval, and said second
sample time interval is after said first transfer time interval,
and said first transfer time interval is after said first sample
time interval, and said first and second sample time intervals and
said first and second transfer time interval are
non-overlapping.
15. A method comprising: alternately sampling a first and second
input signal to a first and second input capacitor of an analog to
digital converter during two different sampling time intervals; and
alternately transferring charges sampled during said two different
sampling time intervals to a first and second integration capacitor
of an integrator of said analog to digital converter during two
different transfer time intervals.
16. The method of claim 15, wherein a first transfer time interval
of said two different transfer time intervals occurs after a first
sample time interval of said two different sample time-intervals,
and a second transfer time interval of said two different transfer
time intervals occurs after a second sample time interval of said
two different sample time intervals.
17. The method of claim 16, further comprising: providing a first
sample path to said first input capacitor from said first input
signal during said first sample time interval; and providing a
second sample path to said second input capacitor from said second
input signal during said first sample time interval.
18. The method of claim 17, further comprising: providing a third
sample path to said second input capacitor from said first input
signal during said second sample time interval; and providing a
fourth sample path to said first input capacitor from said second
input signal during said second sample time interval.
19. The method of claim 16, further comprising: providing a first
transfer path to said first integration capacitor from said first
input capacitor during said first transfer time interval; and
providing a second transfer path to said second integration
capacitor from said second input capacitor during said first
transfer time interval.
20. The method of claim 19, further comprising: providing a third
transfer path to said second integration capacitor from said first
input capacitor during said second transfer time interval; and
providing a fourth transfer path to said first integration
capacitor from said second input capacitor during said second
transfer time interval, wherein said second transfer time interval
occurs after said second sample time interval, and said second
sample time interval occurs after said first transfer time
interval, and said first transfer time interval occurs after said
first sample time interval, and said first and second sample time
intervals and said first and second transfer time interval are all
non-overlapping.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of
application Ser. No. 10/838,563 filed May 4, 2004, which itself is
a continuation application of application Ser. No. 10/142,503 filed
May 10, 2002, now U.S. Pat. No. 6,744,394, both the teachings of
which are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] This invention relates to analog to digital converters, and
more particularly to a high precision analog to digital converter
(ADC) compensating for capacitor mismatch errors in a switched
capacitor ADC.
BACKGROUND OF THE INVENTION
[0003] Analog to digital converters (ADCs) convert analog input
signals into digital signals. Such ADCs are used in many
applications such as video, audio, and signal sensing applications.
One type of ADC is sigma-delta converter utilizing over-sampling
techniques. Such an ADC generally includes an analog modulator
portion and digital filtering and decimation portion. The analog
modulator portion essentially digitizes an analog input signal at
very high sampling rates, i.e., sampling rates greater than the
Nyquist rate, in order to perform a noise shaping function. Then,
the digital filtering portion allows the ADC to achieve a high
resolution. Decimation is thereafter used to reduce the effective
sampling rate back to the Nyquist rate.
[0004] It is known that the analog modulator portion may generally
include a feed forward path including a summing circuit, a filter,
and a single bit A/D converter. A feed back path may further
include a single bit digital to analog converter (DAC) coupled to
the output of the single bit A/D converter and the summation
circuit to provide a negative feed back signal to the summation
circuit. Besides accepting the feed back signal from the DAC, the
summation circuit also accepts an input analog signal for
conversion.
[0005] In a switched capacitor ADC having a pair of input terminals
to accept an input analog signal, an input switch array including a
pair of input capacitors coupled to associated input terminals may
be provided. In addition, an integrator having a pair of
integration capacitors may act as the filter. The integrator may be
further coupled to a comparator which functions as the A/D
converter.
[0006] Ideally, the pair of input capacitors is matched with each
other and the pair of integration capacitors is matched with each
other. However, some capacitor mismatch is generally inevitable
resulting in mismatched gain and offset. This can cause
unacceptable non-linearity and offset problems where a high
precision ADC is required.
[0007] Accordingly, there is a need for an apparatus and method
that overcomes the above deficiencies-in the prior art to allow for
ADC with improved precision performance in the presence of
capacitor mismatching.
BRIEF SUMMARY OF THE INVENTION
[0008] According to one aspect of the invention, there is provided
an analog to digital converter. The analog to digital converter may
include an input switch array configured to alternately sample a
first and a second input signal to a first and a second input
capacitor during two different sample time intervals, an integrator
having a first and second integration capacitor, and a cross switch
array coupled to the input switch array and the integrator. The
cross switch array may be configured to alternately transfer
charges from the first and second input capacitors to the first and
second integration capacitors during two different transfer time
intervals.
[0009] According to another aspect of the invention, there is
provided a system. The system may include a battery, a sensor
configured to sense a current to or from the battery and provide a
first and second analog signal representative of the current, and
an analog to digital converter configured to accept the first and
second analog signals and provide a digital signal representative
of a difference between the first and second analog signal. The
analog to digital converter may include an input switch array
configured to alternately sample the first and and second analog
signals to a first and a second input capacitor during two
different sample time. intervals, an integrator having a first and
second integration capacitor, and a cross switch array coupled to
the input switch array and the integrator. The cross switch array
may be configured to alternately transfer charges from the first
and second input capacitors to the first and second integration
capacitors during two different transfer time intervals.
[0010] According to yet another aspect of the invention there is
provided a method. The method may include alternately sampling a
first and second input signal to a first and second input capacitor
of an analog to digital converter during two different sampling
time intervals, and alternately transferring charges sampled during
the two different sampling time intervals to a first and second
integration capacitor of an integrator of the analog to digital
converter during two different transfer time intervals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] For a better understanding of the present invention,
together with other objects, features and advantages, reference
should be made to the following detailed description which should
be read in conjunction with the following figures wherein like
numerals represent like parts:
[0012] FIG. 1 is a block diagram of one exemplary application of an
ADC consistent with the invention;
[0013] FIG. 2 is a block diagram illustrating an ADC consistent
with the invention having an analog modulator and digital filter
portion;
[0014] FIG. 3A is a circuit diagram of the analog modulator portion
of an ADC consistent with the present invention; and
[0015] FIG. 3B is a timing diagram for the circuit of FIG. 3A.
DETAILED DESCRIPTION
[0016] Turning to FIG. 1, an exemplary sensing system 100 including
a sense resistor 102 and an ADC 108 consistent with the invention
is illustrated. Those skilled in the art will recognize a variety
of systems and sensing systems for accepting a variety of input
analog signals, e.g., voltage or current signals, where an ADC 108
consistent with the invention may be utilized. In the exemplary
system 100 of FIG. 1, a current sensor, e.g., the sense resistor
102, is in series with a power source such as the rechargeable
battery 106, e.g., lithium, nickel-cadmium, or nickel-metal hydride
battery. The sense resistor 102 may be used to sense charging and
discharging current from the battery 106 by providing a pair of
input analog signals to the ADC 108 at input terminals 107,
109.
[0017] The charging and discharging current from the battery 106 is
indirectly sensed by measuring the voltage across the sense
resistor 102 since the charging or discharging current level is
equal to the measured voltage level across terminals 110, 112
divided by the resistance value of the sense resistor 102. In order
to decrease the power wasted by the sense resistor 102, many
applications utilize a sense resistor having a small predetermined
value, e.g., about 10 m.OMEGA.. Accordingly, the voltage across the
sense resistor 102 input to the ADC 108 is also quite small, e.g.,
about 20 mV. Therefore, it is desirable to have a high precision
ADC 108 consistent with the invention for accepting and accurately
converting such small analog input signals into a digital
signal.
[0018] In addition, an ADC 108 consistent with the invention may
also have the ability to detect such low voltage analog signals
just above and below ground level. This is because the negative
battery terminal 111 is typically system ground such that when
charging the battery 106, the charging current flows in a direction
from terminal 110 to terminal 112 as illustrated in FIG. 1.
Therefore, the voltage across the sense resistor 102 in this
instance is positive, e.g., V=(Vsense+)-(Vsense-), where
(Vsense+)>(Vsense-). In contrast, discharging current flows in
an opposite direction such that the voltage across the sense
resistor 102 is negative, e.g., V=(Vsense+)-(Vsense-), where
(Vsense+)<(Vsense-).
[0019] Turning to FIG. 2, a block diagram of an exemplary ADC 208
is illustrated. The exemplary ADC 208 is a sigma-delta oversampling
ADC including an analog modulator portion 202 and a digital filter
portion 204. In general, the analog modulator portion 202 receives
an input analog signal and provides a high frequency 1-bit data
stream to the digital filter portion 204. The input analog signal
may be any variety of analog signals, e.g., current or voltage
signals. For instance, in one of many examples, the analog signal
may be a voltage signal such as that obtained from the voltage
across the sense resistor 102 of FIG. 1.
[0020] The analog modulator portion 202 samples the input analog
signal at a high sampling frequency equal to Fs.times.OSR, where Fs
is the Nyquist Frequency and OSR is the over sampling ratio to the
Nyquist Frequency. For a given analog input signal having a highest
frequency component equal to fmax, the Nyquist Frequency is 2fmax
or twice the highest analog frequency component. The analog
modulator 202 converts the input analog signal into a continuous
stream of 1s and 0s at a rate determined by the sampling frequency
rate or Fs.times.OSR. The analog modulator portion may include a
low pass filter 206, a comparator 211, and a 1-bit DAC 210 in a
negative feedback loop to a summation circuit 212.
[0021] The high quantization noise of the comparator 211, having
just 1-bit resolution, in the signal band (<Fs/2) may be
suppressed by the high gain of the low pass filter 206 at low
frequency. The noise at high frequency levels may not be suppressed
by the low pass filter 206, but is typically outside of the signal
band of interest and can be filtered out by the digital low pass
filter 212. The digital low pass filter 212 accepts the high
frequency 1-bit data from the analog modulator portion 202 and
processes and low pass filters such signal to output a very high
resolution, e.g., more than 14-bits, output at a normal Nyquist
frequency Fs.
[0022] Depending on the order of the low pass filter 206, the
analog modulator 202 may function as a first order modulator,
second order modulator, etc. Theoretically, the higher the OSR the
higher resolution that can be obtained, and the higher the
modulator order the higher resolution that can be obtained. In a
power source sensing system application as illustrated in FIG. 1,
the input analog signal, or the voltage across the sense resistor
102 in this instance, is typically a low frequency voltage signal.
As such a very high OSR, e.g., OSR=4096 or OSR=8192, may be chosen
for such an application. For this type of application, even a first
order analog modulator can achieve a high precision result of
greater than 14-bit resolution. Therefore, a first order modulator
consistent with the invention is detailed herein with reference to
FIGS. 3A and 3B. Those skilled in the art will recognize that other
applications may require various order analog modulators and OSR
values to achieve the desired precision for the particular
application of interest.
[0023] Turning to FIG. 3A, a circuit diagram of a first order
analog modulator portion 302 of a high precision ADC consistent
with the invention is illustrated. FIG. 3B illustrates a timing
diagram for the circuit of FIG. 3A. The analog modulator 302
generally includes an input switch array 319, a cross switch array
324, an integrator 306, a comparator 308, a 1-bit DAC 310, and a
DAC switch array 312. The input switch array further includes a
pair of input terminals 322, 324 to receive input analog signals,
e.g., Vsense+ and Vsense- from the exemplary application
illustrated in FIG. 1. Those skilled in the art will recognize that
any variety of input analog signals may be input to the input
terminals 322, 324. Such input analog signal may also be a
differential input pair.
[0024] The input switch array 319 may further include a pair of
input capacitors C1A, C1B for sampling the input analog signals
during various sampling times as later detailed herein.
Advantageously, the cross switch array 324 is coupled between the
input switch array 319 and the integrator 306 in order to
alternately transfer charges from the pair of input capacitors C1A,
C1B to the pair of integration capacitors CF1A, CF1B as further
detailed herein with reference to the timing diagram of FIG. 3B.
The negative feedback may be furnished by a feedback switch array
312 which is controlled, in part, by the one-bit data stream Y from
the comparator 308.
[0025] The various switches of the various switch arrays 319, 324,
312 and other switches of FIG. 3 are responsive to various control
signals .phi.1, .phi.2, .phi.1P, .phi.2P, .phi.21, and .phi.22 as
shown in the timing diagram of FIG. 3B and all such control signals
are non-overlapping. As such, the various switches S1 through S20
of FIG. 3 are each labeled with an associated control signal
.phi.1, .phi.2, .phi.1P, .phi.2P, .phi.21, or .phi.22. The control
signals .phi.1, .phi.2, .phi.1P, .phi.2P, .phi.21, and .phi.22 are
provided by a timing circuit 326. The timing circuit 326 may be any
variety of configurations as understood by those skilled in the art
for providing the appropriate control signals .phi.1, .phi.2,
.phi.1P, .phi.2P, .phi.21, and .phi.22. In general, when an
associated control signal for an associated switch is "high" the
switch is closed and accordingly conducts current. In contrast,
when an associated control signal for an associated switch is "low"
the switch is open and accordingly does not conduct electricity.
Those skilled in the art will also recognize other switch and
control signal configurations where alternative switches may be
responsive to alternative control signals in an ADC consistent with
the present invention.
[0026] The input switch array 319 may include a plurality of
switches S1, S2, S3, and S4. Such switches may be any variety of
switches known to those skilled in the art, e.g., CMOS transistors
may provide such a switching function. The cross switch array 324
may also include a plurality of switches S7, S8, S19, and S20. The
feedback switch array 312 may also include a plurality of switches
S15, S16, S17, and S18. Finally, the one-bit DAC 310 may also
include a plurality of switches S9, S10, S11, S12, S13, and
S14.
[0027] Operation of the exemplary first order analog modulator
portion 302 of a high precision ADC consistent with the invention,
including operation of the various switches detailed above, will be
described herein with reference to the timing diagram of FIG. 3B.
First, during time interval T1, control signals .phi.1, .phi.1P,
and .phi.comp are high, while all other control signals are low. As
such, those switches responsive to these control signals .phi.1,
.phi.1P close, while the other switches remain open. As such,
switches S9, S12, S13, and S14 of the one-bit DAC 310 are closed
during time interval T1. In addition, switches S1 and S2 of the
input switch array 319 are also closed during time interval T1. In
addition, switches S5 and S6 are closed during time interval
T1.
[0028] Accordingly, the input capacitor C1A pre-samples an input
analog signal input, e.g., Vsense+, from one input terminal 322
through closed switch S1, while another input capacitor C1B
pre-samples an input analog signal through closed switch S2, e.g.,
Vsense-, at another input terminal 324. A reference capacitor CR1A
of the DAC 310 samples a reference signal, e.g., a reference
voltage Vref through closed switch S9, while another reference
capacitor CR1B is discharged to ground through closed switches S12
and S14. The reference signal may be any type of reference signal
such as a voltage or current signal. The reference voltage signals
Vref of FIG. 3A may be provided from any variety of available
sources depending on the application.
[0029] During time interval T2, control signals .phi.2, .phi.2P,
and .phi.21 are high, while other control signals are low. As such,
switches S3 and S4 of the input switch array 319 are closed during
time interval T2 while switches S1 and S2 are open. Switches S7 and
S8 of the cross switch array 324 are closed and switches S10 and
S11 of the DAC 310 are closed during time interval T2. Accordingly,
the input capacitor C1A transfers its pre-sampled charges
accumulated during time interval T1 to the integration capacitor
CF1A, and the input capacitor C1B transfers its pre-sampled charges
accumulated during interval T1 to the integration capacitor
CF1B.
[0030] Advantageously, because switch S4 is closed and switch S1 is
open during time interval T2, the input capacitor C1A is coupled to
the input voltage terminal 324 instead of ground. This permits a
predetermined capacitor value for the capacitor C1A to be half that
it would otherwise be if it was coupled to ground in this instance
since the transfer charges are effectively doubled. Similarly,
because the switch S3 is closed and the switch S2 is open, the
other input capacitor C1B is coupled to the input voltage terminal
322 instead of ground. Accordingly, a predetermined value of the
input capacitor C1B can also be half that it would otherwise be if
coupled to ground during this time interval. The smaller capacitor
values for input capacitors C1A, C1B permit area savings on an
integrated circuit (IC) which is always a premium on today's
ICs.
[0031] Also during time interval T2, switch S10 and S11 are closed,
so a negative reference signal, e.g., -Vref, is generated at node C
and a positive reference signal, e.g., +Vref, is generated at node
D. Depending on the binary feedback signal Y, the feedback switch
array 312 array will couple node C with node A and node D with B,
or node C with node B and node D with node A depending on if Y is 0
or 1. For instance, if Y=1, switches S15 and S16 are closed while
switches S17 and S18 are open. Accordingly, node C is coupled to
node A through closed switch S15, and node D is coupled to node B
through closed switch S16. Alternatively, if the feedback signal
Y=0, switches S15 and S16 are open while switches S17 and S18 are
closed. Accordingly, node C is coupled to node B through closed
switch S17, and node D is coupled to node A through closed switch
S18.
[0032] During time interval T3, clock signals .phi.1 and .phi.2P
are high, while all other clock signals are low. As such, the
switches S3 and S4 are closed, while switches S1 and S2 are open
during time interval T3. Switches S5 and S6 are also closed.
Accordingly, the input capacitor C1A pre-samples the input analog
signal at the input terminal 324 through closed switch S4 and the
other input capacitor C1B pre-samples the input analog signal at
other input terminal 322 through closed switch S3. In addition
during time interval T3, switches S10, S11, S13, and S14 of the DAC
310 are closed while switches S9 and S12 of the DAC are open.
Accordingly, the reference capacitor CR1A of the one-bit DAC 310 is
discharged to ground through closed switches S11 and S13, while the
other reference capacitor CR1B pre-samples the reference signal,
e.g., reference voltage Vref, through closed switch S10.
[0033] Since control signals .phi.21 and .phi.22 are low during
time interval T3, switches S7, S8, S19, and S20 of the cross switch
array 324 are open and hence no charges are transferred from the
input capacitors C1A, C1B to the integration capacitors CF1A, CF1B
during the sampling time interval T3.
[0034] During time interval T4, control signals .phi.2, .phi.1P and
.phi.22 are high while the remaining clock signals are low.
Accordingly, switches S1 and S2 are closed while switches S3 and S4
are open. In addition, switches S19 and S20 of the cross switch
array 324 are closed while switches S7 and S8 are open. Therefore,
the input capacitor C1A advantageously transfers its pre-sampled
charges accumulated during time interval T3 to the integration
capacitor CF1B through closed switch S19. In addition, the other
input capacitor C1B transfers its pre-sampled charges, accumulated
during time interval T3 to the integration capacitor CF1A through
the closed switch S20. In this way, the cross switch array 324 is
configured to transfer charges from the input capacitor C1A to the
integration capacitor CF1A and from the input capacitor C1B to the
integration capacitor CF1B during one time interval T2, and then to
alternately transfer charges from the input capacitor C1A to the
integration capacitor CF1B and from the input capacitor C1B to the
integration capacitor CF1A during another time interval T4. As
such, the cross switch array 324 cross couples the input capacitors
C1A, C1B to the integration capacitors CF1A, CF1B.
[0035] Similarly to time interval T2, the input capacitor C1A is
coupled to the input terminal 322 through closed switch S1 and the
input capacitor C1B is coupled to the other input terminal 324
through closed switch S2 during time interval T4. If the input
terminal 322 receives Vsense+ from the sense resistor 102 of FIG. 1
and the second input terminal 324 receives Vsense- from the sense
resistor 102, the input capacitors C1A, C1B are connected to such
terminals and not grounded. This thereby effectively doubles the
transfer charges and enables the value of the input capacitors C1A,
C1B to be half a value they would otherwise be if grounded in such
an instance.
[0036] Also during time interval T4, switches S9 and S12 are
closed, while the other switches on the one bit DAC 310 are open.
As such, -Vref is generated at node D and +Vref is generated at
node C. Depending on signal Y, the feedback switch array 312 array
will couple node C with node A and node D with B, or node C with
node B and node D with node A depending on the binary value of Y as
earlier detailed with reference to time interval T2. As can be seen
therefore, through appropriate timing control, +Vref is generated
at node D through capacitor CR1B and -Vref is generated at node C
through capacitor CR1A during one time interval T2, and then
alternately +Vref is generated at node C through capacitor CR1A and
-Vref is generated at node D through capacitor CR1B during another
time interval T4. As such, +Vref and -Vref are alternately
generated at node C and node D through capacitors CR1A and
CR1B.
[0037] Time interval T5 is similar to time interval T1 where
control signals .phi.1, .phi.1P and .phi.comp are high while the
remaining clock signals are low. As such during time interval T5,
the comparator 308 accepts the integration results from the
integrator 306 and generates a one-bit data output stream Y at a
rate OSR.times.Fs. Thus, the comparator 308 functions as a one-bit
ADC.
[0038] The analog modulator portion 302 of an ADC consistent with
the invention has several advantages. First, the input switch array
319 enables cross sampling of the input signal at alternating input
terminals 322, 324 during charge transfer time intervals, e.g.,
time intervals T2 and T4. This thereby effectively doubles the
transfer charges and enables the value of input capacitors C1A, C1B
to be half a value they would otherwise be if grounded in such
instances.
[0039] In addition, the cross switch array 324 is configured to
permit the input capacitor C1A to transfer its charges to the
integration capacitor CF1A during one time interval, e.g., time
interval T2, and then to alternately transfer charges to the other
integration capacitor CF1B during another time interval, e.g., time
interval T4. Similarly, the cross switch array 324 is configured to
permit the other input capacitor C1B to transfer its charges to the
integration capacitor CF1B during one time interval, e.g., time
interval T2, and then to alternately transfer charges to the other
integration capacitor CF1A during another time interval, e.g., time
interval T4. Advantageously therefore, the nonlinearity and offset
caused by a mismatch between input capacitors C1A, C1B and
integration capacitors CF1A, CF1B is effectively eliminated. In
addition, the perfect symmetry of the input analog signals, e.g.,
Vsense+ and Vsense-, is also not required. Absent such a
configuration, a gain mismatch between CF1A/C1A and CF1B/C1B may
occur resulting in an unacceptable result for applications
requiring a high precision ADC.
[0040] Yet another advantage of the present invention is that for
the one-bit DAC 310, +Vref and -Vref are alternately generated at
node C and node D given the various switches S9, S10, S11, S12,
S13, and S14 of the DAC 310 as controlled by the control signals
illustrated in the timing diagram of FIG. 3B. Advantageously
therefore, the nonlinearity and offset caused by a mismatch between
one reference capacitor CR1A and the other reference capacitor CR1B
is also effectively eliminated.
[0041] In addition, since there are two transfer or integration
phases, e.g., time interval T2 and time interval T4, between a
first comparison phase, e.g., time interval T1 and a second
comparison phase, e.g., time interval T5, the effects of noise in
the reference source signal, e.g., the Vref signal, is greatly
eliminated. This enables one to lessen the noise requirements for a
reference source. For example, the low frequency noise integrated
during time interval T2 will be greatly diminished during time
interval T4. Theoretically, this effect is equivalent to a
first-order high pass filtering of the Vref noise. A simulation
using a voltage reference source revealed that because of such a
double sampling arrangement, the low frequency noise of Vref
received a 12 dB suppression. Accordingly, the noise requirements
for such a reference voltage source are greatly diminished.
[0042] In addition, the offset and low frequency noise of the
operational amplifier 350 can be alleviated or eliminated by
chopper-stabilized technology as illustrated in FIG. 3a or
correlated double sampling (CDS) technology or auto-zeroing
technology. Such chopper-stabilized technology, CDS technology, and
auto-zeroing technology are known by those skilled in the art and
are accordingly not discussed herein.
[0043] The embodiments that have been described herein, however,
are but some of the several which utilize this invention and are
set forth here by way of illustration but not of limitation. It is
obvious that many other embodiments, which will be readily apparent
to those skilled in the art, may be made without departing
materially from the spirit and scope of the invention.
* * * * *