U.S. patent application number 11/082712 was filed with the patent office on 2005-09-29 for multi-processor system and memory accessing method.
This patent application is currently assigned to NEC CORPORATION. Invention is credited to Kawaguchi, Eiichiro.
Application Number | 20050216696 11/082712 |
Document ID | / |
Family ID | 34991534 |
Filed Date | 2005-09-29 |
United States Patent
Application |
20050216696 |
Kind Code |
A1 |
Kawaguchi, Eiichiro |
September 29, 2005 |
Multi-processor system and memory accessing method
Abstract
A multiprocessor system includes a plurality of microprocessors
configured to operate on a plurality of operating systems,
respectively, and a memory section configured to have a plurality
of memory spaces respectively allocated to the plurality of
microprocessors. Each of the plurality of microprocessors may
include a translation look-aside buffer (TLB) and a page table
register. The TLB stores a copy of at least a part of data of one
of the plurality of memory spaces corresponding to the
microprocessor, and the copy includes a relation of each of virtual
addresses of a virtual address space and a corresponding physical
address of a physical address space as the memory space. The page
table register refers to the TLB in response to an execution
virtual address generated based on an application program to be
executed by the microprocessor to determine an execution physical
address corresponding to the execution virtual address. The
microprocessor accesses the memory space based on the execution
physical address.
Inventors: |
Kawaguchi, Eiichiro; (Tokyo,
JP) |
Correspondence
Address: |
FOLEY AND LARDNER
SUITE 500
3000 K STREET NW
WASHINGTON
DC
20007
US
|
Assignee: |
NEC CORPORATION
|
Family ID: |
34991534 |
Appl. No.: |
11/082712 |
Filed: |
March 18, 2005 |
Current U.S.
Class: |
711/206 ;
711/207; 711/209; 711/E12.065 |
Current CPC
Class: |
G06F 11/004 20130101;
G06F 12/1036 20130101 |
Class at
Publication: |
711/206 ;
711/207; 711/209 |
International
Class: |
G06F 012/08 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 23, 2004 |
JP |
2004-085673 |
Claims
What is claimed is:
1. A multiprocessor system comprising: a plurality of
microprocessors configured to operate on a plurality of operating
systems, respectively; and a memory section configured to have a
plurality of memory spaces respectively allocated to said plurality
of microprocessors.
2. The multiprocessor system according to claim 1, wherein each of
said plurality of microprocessors comprises: a translation
look-aside buffer (TLB) configured to store a copy of at least a
part of data of one of said plurality of memory spaces
corresponding to said microprocessor, said copy including a
relation of each of virtual addresses of a virtual address space
and a corresponding physical address of a physical address space as
said memory space; and a page table register configured to refer to
said TLB in response to an execution virtual address generated
based on an application program to be executed by said
microprocessor to determine an execution physical address
corresponding to said execution virtual address, and said
microprocessor accesses said memory space based on said execution
physical address.
3. The multiprocessor system according to claim 2, wherein a page
table is provided for said memory space to store the relation of
the virtual addresses and the corresponding physical address, and
said TLB stores the copy of said page table.
4. The multiprocessor system according to claim 3, wherein said
page table further stores an identifier to identify said operating
system, and said page table register of said microprocessor refers
to said TLB to determine whether the stored identifier and said
identifier held said microprocessor are coincident with each other,
and refers to said TLB for translation of said execution virtual
address into said execution physical address, when the stored
identifier and said identifier held said microprocessor are
coincident with each other.
5. The multiprocessor system according to claim 2, wherein said
microprocessor further comprises: an address check circuit
configured to generates a determination result to indicate whether
or not said execution physical address meets a predetermined
condition, and when said determination result indicates that said
execution physical address meets said predetermined condition, said
microprocessor accesses said memory space based on said execution
physical address.
6. The multiprocessor system according to claim 5, wherein said
predetermined condition is whether said execution physical address
is in a range from an upper limit physical address to a lower limit
physical address in said memory space.
7. The multiprocessor system according to claim 6, wherein said
microprocessor further comprises: an upper limit & lower limit
physical address storage section configured to store said upper
limit physical address and said lower limit physical address.
8. A memory access method comprising: providing a plurality of
microprocessors configured to operate on a plurality of operating
systems, respectively, and a memory section configured to have a
plurality of memory spaces allocated to said plurality of
microprocessors; and accessing an allocated memory space of said
plurality of memory spaces by one of said plurality of
microprocessors.
9. The memory access method according to claim 8, wherein virtual
addresses and physical addresses are allocated to each of said
plurality of memory spaces, respectively, said memory space has a
page table configured to store a relation of each of said virtual
addresses and a corresponding one of said physical addresses, and
said accessing comprises: referring to said page table in said
memory space in response to an execution virtual address to
determine execution physical address corresponding to said
execution virtual address; and accessing said memory space based on
said execution physical address.
10. The memory access method according to claim 8, wherein said
page table in said memory space stores an identifier to identify
said memory space, and said accessing comprises: referring to said
page table in the said memory space to determine whether the stored
identifier and said identifier held said microprocessor are
coincident with each other; and when the stored identifier and said
identifier held said microprocessor are coincident with each other,
determining said execution physical address.
11. The memory access method according to claim 9, wherein said
microprocessor further comprises an address check circuit, and said
accessing comprises: when said execution physical address is
determined, generating a determination result from said address
checking circuit to indicate whether or not said execution physical
address meets a predetermined condition; and when said
determination result indicates that said execution physical address
meets said predetermined condition, accessing said memory space
based on said execution physical address.
12. The memory access method according to claim 11, wherein said
condition is a range from an upper limit physical address of said
physical addresses allocated to said memory space to a lower limit
physical address of said physical addresses, and said accessing
comprises: when said execution physical address is determined,
generating a determination result indicating whether or not said
execution physical address is contained in said range; and when
said determination result indicates that said execution physical
address is contained in said range, accessing said memory space
based on said execution physical address.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a multi-processor system
and a memory accessing method.
[0003] 2. Description of the Related Art
[0004] In recent years, a multi-processor system including a
plurality of processors has been developed in order to improve
processing performance.
[0005] FIG. 1 shows a schematic diagram of a multi-processor system
of a first conventional example. The conventional multi-processor
system includes an operating system (OS), a plurality of MPUs
(Micro Processing Units) operating on the operating system (OS),
and a main memory. The plurality of MPUs share the main memory. The
multi-processor system further has input/output (I/O) units (not
shown). The plurality of MPUs share the I/O units. In such a
conventional multi-processor system, when a trouble such as
abnormality or fault has occurred in a part of the resource such as
the main memory and the I/O units shared by the plurality of MPUs,
there is a possibility that the trouble influences on the entire
system.
[0006] From the viewpoint of the plurality of operating systems
running on a single computer system, a virtual machine (VM) system
is known as a second conventional example. FIG. 2 shows a schematic
diagram of the virtual machine (VM) system. The virtual machine
system includes a host operating system (OS) running on the
computer, and a plurality of guest operating systems running on the
virtual machine. In the virtual machine system, the host operating
system (OS) is first started on the computer to operate the virtual
machine. The plurality of guest operating systems run on the
virtual machine generated on the host operating system (OS).
However, in the virtual machine system, when a trouble such as
abnormality or fault has occurred in a hardware resource in
association with the host operating system (OS), or when the
trouble has occurred in the host operating system (OS), the
plurality of guest operating systems running on the virtual machine
receive the influence of the trouble. Thus, the trouble has
influence on the entire system.
[0007] Moreover, a logic dividing system is known as a third
conventional example. FIG. 3 shows a schematic diagram of the logic
dividing method. The logic dividing system includes an MPU and a
plurality of operating systems running on the MPU. In the logic
dividing system, a host operating system (OS) is not needed unlike
the virtual machine system, but the plurality of operating systems
run on the same computer. However, in the logic dividing system,
since the plurality of operating systems run on the single MPU, the
plurality of operating systems receive the influence of a trouble,
when the trouble has occurred in the MPU. Hence, the trouble has
influence on the entire system.
[0008] In conjunction with the above description, Japanese Laid
Open Patent Application (JP-A-Heisei 5-204760) discloses a control
system of a virtual machine system. The virtual computer system of
this conventional example is provided with a plurality of operating
systems and a management program for managing the plurality of
operating systems. Under the control of this management program,
the plurality of operating systems run on a single computer system.
A control system of a virtual computer system includes a virtual
address--real address converting section and a real
address--absolute address converting section. The virtual
address--real address converting section assigns a plurality of
continuous spaces on a main memory to the plurality of operating
systems, and has an address management table. The virtual
address--real address converting section uses an address conversion
table in the operating system to convert a virtual address into a
real address. The real address--absolute address converting section
converts the real address obtained by this virtual address--real
address converting section to a physical address of the main memory
by using the address management table.
[0009] Also, Japanese Laid Open Patent Application (JP-A-Heisei
2-96833) discloses a job control system. An information processing
apparatus for the job control system of this conventional example
includes a central processing unit, a main memory, an input/output
processor and peripheral units connected to the input/output
processor. The control of information processing to be carried out
by the information processing apparatus is based on a
general-purpose control section stored in a memory region of the
main memory. In the job control system, the general-purpose control
section has a section for starting a job of a model control section
operating under a control of the general-purpose control section,
and a section for reserving continuous memory regions different
from a memory management region for the general-purpose control
section in the main memory when starting the job. The reserved
memory region stores sub jobs to be executed under the control of
the model control section, a job memory management section of the
model control section, a job task management section of the model
control section, and a job interruption control section of the
different model control section.
[0010] Also, Japanese Laid Open Patent Application
(JP-P2001-101032A) discloses an operating system (OS) monitoring
system for control between different operating systems. The
operating system monitoring system of this conventional example
detects an occurrence of a software trouble in a computer system on
which a plurality of operating systems run. The operating system
(OS) monitoring system has a function of separating hardware
resources for the plurality of operating systems by using a virtual
hardware which has a function of distributing interruptions from
the hardware or the processing time of a CPU. Also, the operating
system (OS) monitoring system has a function of permitting data to
be read and written between the plurality of operating systems. The
operating system monitoring system monitors the operations of the
operating systems by periodically checking the writing of the data
and the written data and carries out re-loading of the operating
systems when detecting the trouble.
[0011] Also, Japanese Laid Open Patent Application
(JP-P2001-101034A) discloses a trouble recovering system for
control between different operating systems. The trouble recovering
system of this conventional example uses a computer system in which
a plurality of operating systems run simultaneously. The trouble
recovering system has first to fourth units. The first unit assigns
hardware resources to the plurality of operating systems. The first
unit also attains, by using a software technique, a firewall as a
virtual wall for isolating software and hardware such that a
trouble of the hardware or the operating system has no influence on
the execution of the other operating systems. Also, the first unit
transmits information between the respective operating systems. The
second unit monitors the operation states of the operating systems
and an application program from an isolated operation environment
and detects a trouble, stop and an operation impossible state of
either of the operating systems. The third unit normally or
forcedly stops the troubled operating system (OS). The fourth unit
re-starts the operating systems. Thus, the trouble recovering
system recovers the system automatically at the time of the trouble
occurrence by combining them.
[0012] Also, Japanese Laid Open Patent Application (JP-A-Heisei
11-85547) discloses a virtual cluster configuring method. The
virtual cluster configuring method of this conventional example has
a virtual cluster configuring unit and an inter-virtual-cluster
communicating unit. The virtual cluster configuring unit has
dedicated hardware resources such as a processor, a physical
memory, and an external device, and configures a plurality of
virtual clusters, on which an operating system run on a single
computer. In the inter-virtual-cluster communicating unit,
processes on the different virtual clusters communicate with each
other.
SUMMARY OF THE INVENTION
[0013] An object of the present invention is to provide a
multi-processor system that can restrict influence of a trouble to
a minimum, and a memory accessing method.
[0014] In an aspect of the present invention, a multiprocessor
system includes a plurality of microprocessors configured to
operate on a plurality of operating systems, respectively, and a
memory section configured to have a plurality of memory spaces
respectively allocated to the plurality of microprocessors.
[0015] Here, each of the plurality of microprocessors may include a
translation look-aside buffer (TLB) and a page table register. The
TLB stores a copy of at least a part of data of one of the
plurality of memory spaces corresponding to the microprocessor, and
the copy includes a relation of each of virtual addresses of a
virtual address space and a corresponding physical address of a
physical address space as the memory space. The page table register
refers to the TLB in response to an execution virtual address
generated based on an application program to be executed by the
microprocessor to determine an execution physical address
corresponding to the execution virtual address. The microprocessor
accesses the memory space based on the execution physical
address.
[0016] In this case, a page table may be provided for the memory
space to store the relation of the virtual addresses and the
corresponding physical address. The TLB stores the copy of the page
table.
[0017] Also, the page table may further store an identifier to
identify the operating system. The page table register of the
microprocessor may refer to the TLB to determine whether the stored
identifier and the identifier held the microprocessor are
coincident with each other, and refer to the TLB for translation of
the execution virtual address into the execution physical address,
when the stored identifier and the identifier held the
microprocessor are coincident with each other.
[0018] Also, the microprocessor may further include an address
check circuit configured to generate a determination result to
indicate whether or not the execution physical address meets a
predetermined condition. When the determination result indicates
that the execution physical address meets the predetermined
condition, the microprocessor accesses the memory space based on
the execution physical address. In this case, the predetermined
condition may be whether the execution physical address is in a
range from an upper limit physical address to a lower limit
physical address in the memory space. The microprocessor may
further include an upper limit & lower limit physical address
storage section configured to store the upper limit physical
address and the lower limit physical address.
[0019] In another aspect of the present invention, a memory access
method is achieved by providing a plurality of microprocessors
configured to operate on a plurality of operating systems,
respectively, and a memory section configured to have a plurality
of memory spaces allocated to the plurality of microprocessors; and
by accessing an allocated memory space of the plurality of memory
spaces by one of the plurality of microprocessors.
[0020] Here, when virtual addresses and physical addresses are
allocated to each of the plurality of memory spaces, respectively,
the memory space may have a page table configured to store a
relation of each of the virtual addresses and a corresponding one
of the physical addresses. The accessing may be achieved by
referring to the page table in the memory space in response to an
execution virtual address to determine execution physical address
corresponding to the execution virtual address; and by accessing
the memory space based on the execution physical address.
[0021] Also, when the page table in the memory space stores an
identifier to identify the memory space, the accessing may be
achieved by referring to the page table in the memory space to
determine whether the stored identifier and the identifier held the
microprocessor are coincident with each other; and by when the
stored identifier and the identifier held the microprocessor are
coincident with each other, determining the execution physical
address.
[0022] Also, when the microprocessor further includes an address
check circuit, the accessing may be achieved by generating a
determination result from the address checking circuit to indicate
whether or not the execution physical address meets a predetermined
condition when the execution physical address is determined; and by
accessing the memory space based on the execution physical address
when the determination result indicates that the execution physical
address meets the predetermined condition.
[0023] Also, when the condition is a range from an upper limit
physical address of the physical addresses allocated to the memory
space to a lower limit physical address of the physical addresses,
the accessing may be achieved by generating a determination result
indicating whether or not the execution physical address is
contained in the range when the execution physical address is
determined; and by accessing the memory space based on the
execution physical address when the determination result indicates
that the execution physical address is contained in the range.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1 is a schematic diagram showing a multi-processor
system of a first conventional example;
[0025] FIG. 2 is a schematic diagram showing a virtual machine (VM)
system of a second conventional example;
[0026] FIG. 3 is a schematic diagram showing a logic dividing
system of a third conventional example;
[0027] FIG. 4 is a schematic diagram showing the hardware
configuration of a multi-processor system according to a first
embodiment of the present invention;
[0028] FIG. 5 is a diagram showing assignment of the whole memory
space of a main memory to MPUs in the multi-processor system of the
present invention;
[0029] FIG. 6 is a diagram showing a page table in the
multi-processor system of the present invention;
[0030] FIG. 7 is a flowchart showing the operation of the
multi-processor system according to the first embodiment of the
present invention;
[0031] FIG. 8 is a schematic diagram showing the MPUs and a main
memory in the multi-processor system according to a second
embodiment of the present invention;
[0032] FIG. 9 is a diagram showing an upper limit & lower limit
physical address storing unit in the multi-processor system of the
second embodiment;
[0033] FIG. 10 is a diagram showing the page table in the
multi-processor system according to the second embodiment of the
present invention; and
[0034] FIG. 11 is a flowchart showing the operation of the
multi-processor system according to the second embodiment of the
present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0035] Hereinafter, a multi-processor system according to the
present invention will be described in detail with reference to the
attached drawings.
[0036] FIG. 4 shows a schematic diagram of the hardware
configuration of the multi-processor system according to the first
embodiment of the present invention. The multi-processor system 10
of the present invention includes a plurality of operating systems
11.sub.0 to 11.sub.n (n is an integer of 1 or more), a plurality of
MPUs (Micro Processor Units) 12.sub.0 to 12.sub.n, a chip set 13, a
main memory 14, an input/output device controller (PCI/PCI-X) 15
and a plurality of input/output device groups (PCI device groups)
16.sub.0 to 16.sub.n. The plurality of MPUs 12.sub.0 to 12.sub.n
are microprocessors for supporting virtual addresses. The chip set
13 is a controller for linking a symmetrical type multi-processor
system (SMP) and is connected to the plurality of MPUs 12.sub.0, to
12.sub.n, the main memory 14 and the input/output device controller
15. The main memory 14 has a plurality of memory spaces (MEM
spaces) 14.sub.0 to 14.sub.n and a table for managing a system
configuration. The input/output device controller (PCI/PCI-X) 15 is
a controller to control the PCI device groups 16.sub.0 to
16.sub.n.
[0037] The plurality of MPUs 12.sub.0 to 12.sub.n operate on the
plurality of operating systems 11.sub.0 to 11.sub.n, respectively.
That is, the first MPU 12.sub.0 of the plurality of MPUs 12.sub.0
to 12.sub.n operates the first operating system (OS) 11.sub.1 of
the plurality of operating systems 11.sub.0 to 11.sub.n. The second
MPU 12.sub.1 of the plurality of MPUs 120 to 12n operates the
second operating system (OS) 11.sub.1 of the plurality of operating
system (OS)s 11.sub.0 to 11.sub.n. The j-th (j=0, 1, 2 to n) MPU
12.sub.j of the plurality of MPUs 12.sub.0 to 12.sub.n operates the
j-th operating system (OS) 11.sub.j of the plurality of operating
systems 11.sub.0 to 11.sub.n.
[0038] The plurality of memory spaces (MEMs) 14.sub.0 to 14.sub.n
are assigned to the plurality of MPUs 12.sub.0 to 12.sub.n,
respectively. That is, the memory (MEM) 14.sub.0 of the plurality
of memories (MEMs) 14.sub.0 to 14.sub.n is assigned to the MPU
12.sub.0. The memory (MEM) 14.sub.1 of the plurality of memories
(MEMs) 14.sub.0 to 14.sub.n is assigned to the MPU 12.sub.1. The
memory (MEM) 14.sub.j of the plurality of memories (MEMs) 14.sub.0
to 14.sub.n is assigned to the MPU 12.sub.j. It is not always
necessary that the memory spaces (MEMs) 14.sub.0 to 14.sub.n are
fixedly assigned to the MPUs 12.sub.0 to 12.sub.n, respectively. In
short, the memory space (MEM) 14.sub.1 may be used by the MPU
12.sub.0, and the memory space (MEM) 14.sub.0 may be used by the
MPU 12.sub.1. Which of the memory spaces is allocated to either of
the MPUs 12.sub.0 to 12.sub.n is determined by referring to the
system configuration management table set by a user. In this
embodiment, it is assumed that the plurality of memories (MEMs)
14.sub.0 to 14.sub.n are assigned to the plurality of MPUs 12.sub.0
to 12.sub.n, respectively, in an order from the number 1 to in the
number n.
[0039] The PCI device groups 16.sub.0 to 16.sub.n are assigned to
the plurality of MPUs 12.sub.0 to 12.sub.n, respectively. That is,
the PCI device group 16.sub.0 of the plurality of PCI device groups
16.sub.0 to 16.sub.n is assigned to the MPU 12.sub.0. The PCI
device group 16.sub.0 of the plurality of PCI device groups
16.sub.0 to 16.sub.n is assigned to the MPU 12.sub.1. The PCI
device group 16.sub.j of the plurality of PCI device groups
16.sub.0 to 16.sub.n is assigned to the MPU 12.sub.j. The number of
the PCI devices is not limited to n, and may exceed n. For example,
when the PCI device group 16.sub.0 may include three PCI devices,
the three PCI devices may be assigned to the MPU 12.sub.0. Also,
when the PCI device 16.sub.1 may include five PCI devices, and the
five PCI devices may be assigned to the MPU 12.sub.1. Which of the
PCI device groups is allocated to either of the MPUs is determined
by referring to the system configuration management table.
[0040] FIG. 5 shows a diagram of assignment of the whole memory
space of the main memory 14 to the MPUs 12.sub.0 to 12.sub.n in the
multi-processor system 10 of the present invention. It should be
noted that the system configuration management table is not shown.
The memory space (MEM) 14.sub.j has a page table 4.sub.j used to
convert a virtual address into a physical address. The MPU 12.sub.j
has a page table register 1.sub.j for referring to the page table
4.sub.j. The MPU 12.sub.j further has a translation look-aside
buffer (TLB) 2.sub.j for serving as a cache for data of the memory
space 14.sub.j including the page table 4.sub.j as an address
translation table. The contents of the TLB 2.sub.j is updated in
accordance with the progress of the execution of the application
program by the MPU 12.sub.j. If the page table register 1.sub.j
cannot acquire necessary data when accessing to the TLB 2.sub.j,
the page table register 1.sub.j directly refers to the page table
4.sub.j to acquire the necessary data.
[0041] When the plurality of operating systems run, the memory
space is allocated by using the page table provided in the main
memory space for every MPU. Usually, a virtual address is used to
efficiently share the memory space between a plurality of programs
and to cope with the limit of the capacity of the main memory 14.
In this embodiment, the page tables are used for the plurality of
operating systems. Virtual addresses and physical addresses are
assigned to the memory space 14.sub.j of the main memory 14. The
virtual address assigned to the memory space (MEM) 14.sub.j
includes a virtual page number and an in-page offset. The physical
address assigned to the memory space (MEM) 14.sub.j includes a
physical page number and the in-page offset.
[0042] FIG. 6 shows the page table 4.sub.j in the multi-processor
system 10 of the present invention. The page table 4.sub.j stores a
relation of the virtual page number of each virtual address and the
physical page number of the physical address corresponding to the
virtual address.
[0043] FIG. 7 is a flowchart showing the operation of the
multi-processor system 10 of the present invention. Each of the
MPUs 12.sub.0 to 12.sub.n is started by firmware by referring to
the system configuration management table. At this time, the memory
spaces 14.sub.0 to 14.sub.n are allocated to the MPUs 12.sub.0 to
12.sub.n, respectively.
[0044] While executing a program, the MPU 12.sub.j executes a
command containing a virtual address. At this time, the page table
register 1.sub.j of the MPU 12.sub.j refers to the page table
4.sub.j of the allocated memory space (MEM) 14.sub.j in response to
the virtual address (Step S1). The MPU 12.sub.j refers to the TLB
to convert the virtual address into a physical address of the
memory space (MEM) 14.sub.j of the main memory 14 (Step S2). Then,
the MPU 12.sub.j accesses the memory (MEM) 14.sub.j based on the
physical address (Step S3).
[0045] According to the multi-processor system 10 of the present
invention, the plurality of memory spaces (MEMs) 14.sub.0 to
14.sub.n are assigned to the plurality of MPUs 12.sub.0 to
12.sub.n, respectively, and each of the plurality of PCI devices
16.sub.0 to 16.sub.n is assigned to either of the MPUs 12.sub.0 to
12.sub.n. For this reason, according to the multi-processor system
10 of the present invention, even if a trouble such as abnormality
or fault has occurred in the MPU 12.sub.0 among the MPUs 12.sub.0
to 12.sub.n, the MPUs 12.sub.1 to 12.sub.n do not receive the
influence of the trouble, and the resource/software of the
operating systems 11.sub.0 to 11.sub.n, the memory spaces (MEMs)
14.sub.0 to 14.sub.n, and the PCI devices 16.sub.0 to 16.sub.n do
not receive the influence of the trouble at all.
[0046] Also, according to the multi-processor system 10 of the
present invention, even when the trouble has occurred in the memory
space (MEM) 14.sub.0 or the PCI device 16.sub.0, or a trouble has
occurred in the operating system (OS) 11.sub.0 as well as the
trouble in the MPU 12.sub.0, the MPUs 12.sub.1 to 12.sub.n do not
receive the influence of the trouble, and the resource/software
assigned to the MPUs 12.sub.1 to 12.sub.n do not receive the
influence of the trouble at all.
[0047] In addition, according to the multi-processor system 10 of
the present invention, a user can duplicate an important process,
triplicate or more. For example, the same virtual address space may
be assigned to the different physical memory spaces (MEMs) 14.sub.0
and 14.sub.1, and the MPUs 12.sub.0 and 12.sub.1 may operate on the
same operating systems based on same application programs,
respectively. In this case, even if the trouble has occurred in the
MPU 12.sub.0, the MPU 12.sub.1 operates without receiving the
influence of the trouble in the MPU 12.sub.0.
[0048] In this way, according to the multi-processor system 10 of
the present invention, even if the trouble such as abnormality or
defect has occurred, the influence of the trouble can be restricted
to the minimum.
[0049] Next, the multi-processor system 10 according to the second
embodiment of the present invention will be described below. The
multi-processor system 10 according to the second embodiment of the
present invention can further restrict the influence of the
trouble. The same description of the multi-processor system 10
according to the second embodiment of the present invention as that
of the first embodiment is omitted.
[0050] FIG. 8 shows a schematic diagram showing the MPUs 12.sub.0
to 12.sub.n and the main memory 14 in the multi-processor system 10
according to the second embodiment of the present invention. The
MPU 12.sub.j has an upper limit & lower limit physical address
storing unit 5.sub.j and an address check circuit 6.sub.j in
addition to the page table register 1.sub.j and the TLB
2.sub.j.
[0051] FIG. 9 shows the upper limit & lower limit physical
address storing unit 5.sub.j in the multi-processor system 10 of
the second embodiment. The upper limit & lower limit physical
address storing unit 5.sub.j of the MPU 12.sub.j stores an upper
limit physical address of the memory space 14.sub.j assigned to the
MPU 12.sub.j and a lower limit physical address of the memory space
(MEM) 14.sub.j. The address check circuit 6.sub.1 of the MPU
12.sub.j refers to the upper limit & lower limit physical
address storing unit 5.sub.j to determine whether the physical
address corresponding to the virtual address is in a range from the
upper limit physical address to the lower limit physical address in
the memory space (MEM) 14.sub.j, and generates a determination
result. Therefore, the above-mentioned range is a condition.
[0052] FIG. 10 shows the page table 4.sub.j in the multi-processor
system 10 according to the second embodiment of the present
invention. The page table 4.sub.j stores a relation of the virtual
page number in the virtual address space and a physical page number
in the physical address space corresponding to the memory space
14.sub.j and an operating system (OS) number 8.sub.j as an entry.
The MPU 12.sub.j recognizes and holds the operating system (OS)
number 8.sub.j for the memory space 14.sub.j stored in the page
table 4.sub.j.
[0053] The operating system (OS) number 8.sub.j is an identifier
for uniquely identifying the operating system allocated to the
memory space 14.sub.j. In order to add this entry to each of the
page tables 4.sub.0 to 4.sub.n, N bits (the number of operating
systems satisfies a relation of (N.ltoreq.2.sup.N) Under assumption
that different operating systems are assigned to the respective
MPUs, N is desired to satisfy (the number of
MPUs).ltoreq.2.sup.N.
[0054] FIG. 11 is a flowchart showing the operation of the
multi-processor system 10 according to the second embodiment of the
present invention.
[0055] The page table register 1.sub.j of the MPU 12.sub.j refers
to the TLB 2.sub.j or the page table 4.sub.j of the memory space
14.sub.j in response to the virtual address (Step S1).
Subsequently, the page table register 1.sub.j of the MPU 12.sub.j
checks whether or not the operating system (OS) number 8.sub.j set
and held based on the system configuration management table is
coincident with the operating system (OS) number 8.sub.j stored in
the page table 4.sub.j of the memory space 14.sub.j (Step S11). As
the check result, when the operating system (OS) number 8.sub.j
held by the MPU 12.sub.j and the operating system (OS) number
8.sub.j stored in the page table 4.sub.j of the memory space (MEM)
14.sub.j are not coincident with each other, that is, when the
virtual address is not the appropriate memory space 14.sub.j (Step
S11--NO), the MPU 12.sub.j does not access the memory space
14.sub.j. On the other hand, as the checked result, the operating
system (OS) number 8.sub.j held by the MPU 12.sub.j and the
operating system (OS) number 8.sub.j stored in the page table
4.sub.j of the memory space (MEM) 14.sub.j are coincident with each
other, that is, it is the appropriate memory space 14.sub.j (Step
S11--YES), the page table register 1.sub.j of the MPU 12.sub.j
refers to the TLB 2.sub.j or the page table 4.sub.j to convert the
virtual address into the physical address. That is, the MPU
12.sub.j converts the virtual address into the physical address
(Step S2). Then, the address check circuit 6.sub.j of the MPU
12.sub.j refers to the upper limit & lower limit physical
address storing unit 5.sub.j based on the physical address and
generates the determination result indicating whether or not the
physical address obtained at the step S2 satisfies the
above-mentioned condition (Step S12). This determination result
indicates whether or not the physical address is included in the
range between the upper limit physical address and the lower limit
physical address. For example, when the determination result
indicates that the physical address is not included in the
above-mentioned range, that is, when the physical address obtained
at the step S2 does not satisfy the above-mentioned condition, the
physical address is not adequate (Step S13--NO). In this case, the
MPU 12.sub.j does not access the memory space 14.sub.j. Also, when
the determination result indicates that the physical address is
included in the above-mentioned range, that is, when the physical
address obtained at the step S2 satisfies the above-mentioned
condition, the physical address is suitable (Step S13--YES). In
this case, the MPU 12.sub.j accesses the memory space 14.sub.j
(Step S3).
[0056] According to the multi-processor system 10 in the second
embodiment, the MPU 12.sub.j can avoid the illegal access to
another memory space different from the memory space 14.sub.j to be
accessed. The page table 4.sub.j may have an identifier of the MPU
12.sub.j or memory space 14.sub.j in place of the operating system
number. In either case, the relation between them can be confirmed.
Therefore, even if a trouble such as abnormality or defect has
occurred in the MPU 12.sub.0 of the MPUs 12.sub.0 to 12.sub.n, the
MPUs 12.sub.1 to 12.sub.n do not receive the influence of the
trouble. Also, the resource/software such as the operating systems
11.sub.1 to 11.sub.n, the memory spaces 14.sub.1 to 14.sub.n, and
the PCI devices 16.sub.1 to 16.sub.n assigned to the MPUs 12.sub.1
to 12.sub.n do not receive the influence of the trouble at all.
[0057] In this way, with the multi-processor system 10 in the
second embodiment, the influence of the trouble can be restricted
to the further minimum.
* * * * *