U.S. patent application number 10/806624 was filed with the patent office on 2005-09-29 for leakage current reduction method.
Invention is credited to Dang, Luan A., Deng, Xiaowei, Jamison, George B., Mair, Hugh, Scott, David B., Tran, Tam M., Yang, Shyh-Horng.
Application Number | 20050212554 10/806624 |
Document ID | / |
Family ID | 34989065 |
Filed Date | 2005-09-29 |
United States Patent
Application |
20050212554 |
Kind Code |
A1 |
Mair, Hugh ; et al. |
September 29, 2005 |
LEAKAGE CURRENT REDUCTION METHOD
Abstract
The method for powering down a circuit for a data retention mode
includes: changing a supply voltage node from an active power
voltage level to an inactive power level; coupling a source of a P
channel device to the supply voltage node; providing a retaining
power supply voltage level to a back gate of the P channel device;
changing a drain voltage of the P channel device to a reference
voltage level, wherein the reference voltage level is different
from the retaining power supply voltage level; and changing a gate
voltage of the P channel device to the reference voltage level.
Inventors: |
Mair, Hugh; (Fairview,
TX) ; Dang, Luan A.; (Richardson, TX) ; Deng,
Xiaowei; (Plano, TX) ; Jamison, George B.;
(Murphy, TX) ; Tran, Tam M.; (Austin, TX) ;
Yang, Shyh-Horng; (Plano, TX) ; Scott, David B.;
(Plano, TX) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
|
Family ID: |
34989065 |
Appl. No.: |
10/806624 |
Filed: |
March 23, 2004 |
Current U.S.
Class: |
326/33 |
Current CPC
Class: |
H03K 19/00361 20130101;
H03K 19/0016 20130101 |
Class at
Publication: |
326/033 |
International
Class: |
H03K 019/003 |
Claims
What is claimed is:
1. A method for powering down a circuit for a data retention mode
comprising: changing a supply voltage node from an active power
voltage level to an inactive power level; coupling a source of a P
channel device to the supply voltage node; providing a retaining
power supply voltage level to a back gate of the P channel device;
changing a drain voltage of the P channel device to a reference
voltage level, wherein the reference voltage level is different
from the retaining power supply voltage level; and changing a gate
voltage of the P channel device to the reference voltage level.
2. The method of claim 1 wherein the reference voltage level is
less than the retaining power supply voltage level.
3. The method of claim 1 wherein the reference voltage level is
less than half the retaining power supply voltage level.
4. The method of claim 1 wherein the P channel device is in a
wordline circuit.
5. The method of claim 1 further comprising: coupling a second P
channel device in series with the first P channel device; coupling
a first N channel device in series with the second P channel
device; and coupling a second N channel device in series with the
first N channel device.
6. The method of claim 5 further comprising: providing the
retaining power supply voltage level to a source of the second N
channel device; changing a drain of the N channel device to the
reference voltage level; and changing a gate voltage of the N
channel device to the reference voltage level.
7. The method of claim 1 wherein the retaining power supply voltage
level is the same as the active power voltage level.
8. The method of claim 1 wherein the active power voltage level is
1.3V, the inactive power level is 0V, the reference voltage level
is 0.6V, the retaining power supply voltage level is 1.3V.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to electronic circuitry and,
in particular, to a leakage current reduction method.
BACKGROUND OF THE INVENTION
[0002] In a prior approach for powering down a circuit system, when
the system goes into sleep/data retention mode, the main power
supply VDD goes from 1.3V (in active mode) to near 0V, a retaining
power supply VRET remains unchanged at, for example, 1.3V, a retain
signal RET goes from 0V to VRET (1.3V) level, and some internal
nodes of the system are raised to a reference voltage VBB level
(for example 0.6V).
[0003] For circuits whose data needs to be retained when the system
goes into sleep/data retention mode, the typical way of turning off
the P Channel (PCH) device is shown below:
[0004] Vdrain=VBB (0V-->0.6V, for example)
[0005] Vgate=RET (0-->1.3V, for example)
[0006] Vsource=VDD (1.3V-->0V, for example)
[0007] Vbulk=VRET (1.3V, for example)
[0008] This is demonstrated in the wordline circuit shown in FIG.
1. This circuit has a P channel device 20 as a header. The circuit
also includes P channel device 22, N channel device 24, and N
channel device 26. When this circuit goes into sleep/data retention
mode, source voltage Vsource goes from the active level power
supply level VDD (for example 1.3V) to 0V; the drain voltage Vdrain
goes to the reference voltage VBB (for example 0.6V); the gate
voltage Vgate goes to the retain signal RET, which goes from 0V to
retaining power supply VRET (1.3V, for example); and the back gate
Vbulk goes to the retaining power supply VRET.
[0009] The problem with this prior art solution is that large
voltage differences between the gate (1.3V) and the source
(0V)/drain (0.6V) exist which results in large gate tunneling
leakage, which dominates the P channel device leakage at room
temperature since the sub-threshold leakage is suppressed by the
deep back-gate bias. This leads to high standby power
consumption.
SUMMARY OF THE INVENTION
[0010] A method for powering down a circuit for a data retention
mode includes: changing a supply voltage node from an active power
voltage level to an inactive power level; coupling a source of a P
channel device to the supply voltage node; providing a retaining
power supply voltage level to a back gate of the P channel device;
changing a drain voltage of the P channel device to a reference
voltage level, wherein the reference voltage level is different
from the retaining power supply voltage level; and changing a gate
voltage of the P channel device to the reference voltage level.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In the drawings:
[0012] The DRAWING is a diagram of a wordline circuit with a P
channel device as header.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0013] The preferred embodiment solution to this problem is to
raise the gate of the P channel device 20 to reference voltage VBB
(0.6V, for example), instead of retain signal RET (1.3V, for
example) when the system goes into sleep/data retention mode, as
shown below:
[0014] Vdrain=VBB (0V-->0.6V)
[0015] Vgate=VBB (0-->0.6V)
[0016] Vsource=VDD (1.3V-->0V)
[0017] Vbulk=VRET (1.3V)
[0018] Since the voltage differences between the gate (0.6V) and
the source (0V)/drain (0.6V) are greatly reduced, the gate
tunneling leakage and standby power consumption are also greatly
reduced. In fact, the leakage from the reference voltage node VBB
does not contribute to any power consumption, since it is provided
by the leakage from other parts of the system such as retention
SRAM arrays.
[0019] A similar method can be applied to turn off the N channel
device if e.g. the source is raised from 0V to 1.3V (retaining
voltage), drain is raised from 0V to 0.6V (reference voltage VBB),
and bulk remains at 0V when the system goes into sleep/data
retention mode. In such a case, the gate can be raised to reference
voltage VBB instead of kept at 0V.
[0020] One advantage of the preferred embodiment circuit is that it
saves large gate leakage that helps meet leakage budget
requirements when the circuit is in power down mode. Another
advantage is that the leakage from the reference voltage source VBB
does not contribute to any power consumption, since it is provided
by the leakage from other parts of the system such as retention
SRAM arrays.
[0021] While this invention has been described with reference to an
illustrative embodiment, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiment, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. It is therefore
intended that the appended claims encompass any such modifications
or embodiments.
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