U.S. patent application number 11/133266 was filed with the patent office on 2005-09-29 for semiconductor device and manufacturing method thereof.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Izumi, Kazutoshi, Nagai, Kouichi, Saigoh, Kaoru, Saito, Hitoshi, Sashida, Naoya.
Application Number | 20050212020 11/133266 |
Document ID | / |
Family ID | 34988745 |
Filed Date | 2005-09-29 |
United States Patent
Application |
20050212020 |
Kind Code |
A1 |
Izumi, Kazutoshi ; et
al. |
September 29, 2005 |
Semiconductor device and manufacturing method thereof
Abstract
An insulation film (24) having a gradual inclination of a
surface is formed by a high density plasma CVD method, an
atmospheric pressure CVD method or the like, after a ferroelectric
capacitor (23) is formed. Thereafter, an alumina film (25) is
formed on the insulation film (24). According to the method, low
coverage of the alumina film (25) does not become a problem, and
the ferroelectric capacitor (23) is reliably protected.
Inventors: |
Izumi, Kazutoshi; (Kawasaki,
JP) ; Saito, Hitoshi; (Kawasaki, JP) ;
Sashida, Naoya; (Kawasaki, JP) ; Saigoh, Kaoru;
(Kawasaki, JP) ; Nagai, Kouichi; (Kawasaki,
JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW
SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
34988745 |
Appl. No.: |
11/133266 |
Filed: |
May 20, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11133266 |
May 20, 2005 |
|
|
|
PCT/JP03/05223 |
Apr 24, 2003 |
|
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Current U.S.
Class: |
257/295 ;
257/E21.664; 257/E27.104 |
Current CPC
Class: |
H01L 27/11507 20130101;
H01L 2924/19041 20130101; H01L 27/11502 20130101 |
Class at
Publication: |
257/295 |
International
Class: |
H01L 029/76 |
Claims
What is claimed is:
1. A semiconductor device, comprising: a semiconductor substrate; a
ferroelectric capacitor formed above said semiconductor substrate;
an insulation film directly covering said ferroelectric capacitor
and having an inclination of its surface more gradual than an
inclination of a surface of said ferroelectric capacitor; and a
hydrogen diffusion prevention film formed on said insulation film
and preventing diffusion of hydrogen to said ferroelectric
capacitor.
2. The semiconductor device according to claim 1, wherein said
insulation film is formed by a high density plasma CVD method.
3. The semiconductor device according to claim 1, wherein said
insulation film is one selected from a group consisting of a
silicon oxide film doped with no impurity, a silicon oxynitride
film, a silicon oxide film doped with fluorine, a silicon oxide
film doped with phosphorus and a silicon oxide film doped with
boron and phosphorus.
4. The semiconductor device according to claim 1, wherein said
hydrogen diffusion prevention film is one selected from a group
consisting of an aluminum oxide film, an aluminum oxynitride film,
a tantalum oxide film and a titanium oxide film.
5. The semiconductor device according to claim 1, wherein thickness
of said hydrogen diffusion prevention film is 10 nm to 100 nm.
6. The semiconductor device according to claim 1, further
comprising: a semiconductor element formed on said semiconductor
substrate; a pad formed above said semiconductor substrate and
connected to said semiconductor element; one wiring layer or two or
more wiring layers formed between said semiconductor element and
said pad; and a water permeation prevention film formed between an
uppermost wiring layer located at an uppermost position of said one
wiring layer or two or more wiring layers, and preventing
permeation of water to a lower layer side thereof.
7. The semiconductor device according to claim 6, wherein said
water permeation prevention film is one selected from a group
consisting of an aluminum oxide film, a silicon nitride film and a
silicon oxynitride film.
8. A semiconductor device, comprising: a semiconductor substrate; a
semiconductor element formed on said semiconductor substrate; a pad
formed above said semiconductor substrate and connected to said
semiconductor element; one wiring layer or two or more wiring
layers formed between said semiconductor element and said pad; and
a water permeation prevention film formed between an uppermost
wiring layer located at an uppermost position of said one wiring
layer or two or more wiring layers, and preventing permeation of
water to a lower layer side thereof.
9. The semiconductor device according to claim 8, further
comprising an insulation film formed to cover said uppermost wiring
layer by a high density plasma CVD method.
10. The semiconductor device according to claim 8, wherein said
water permeation prevention film is one selected from a group
consisting of an aluminum oxide film, a silicon nitride film and a
silicon oxynitride film.
11. The semiconductor device according to claim 8, wherein
thickness of said water permeation prevention film is 10 nm to 100
nm.
12. The semiconductor device according to claim 8, further
comprising a ferroelectric capacitor formed at any layer between
said semiconductor substrate and said uppermost wiring layer.
13. A manufacturing method of a semiconductor device, comprising
the steps of: forming a ferroelectric capacitor above a
semiconductor substrate; forming an insulation film directly
covering the ferroelectric capacitor and having an inclination of
its surface more gradual than an inclination of a surface of the
ferroelectric capacitor; and forming a hydrogen diffusion
prevention film preventing diffusion of hydrogen to the
ferroelectric capacitor on the insulation film.
14. The manufacturing method of the semiconductor device according
to claim 13, wherein the insulation film is formed by a high
density plasma CVD method.
15. The manufacturing method of the semiconductor device according
to claim 14, wherein temperature of the semiconductor substrate on
forming the insulation film is set at 175.degree. C. to 350.degree.
C.
16. The manufacturing method of the semiconductor device according
to claim 13, wherein one selected from a group consisting of a
silicon oxide film doped with no impurity, a silicon oxynitride
film, a silicon oxide film doped with fluorine, a silicon oxide
film doped with phosphorus, and a silicon oxide film doped with
boron and phosphorus is formed as the insulation film.
17. The manufacturing method of the semiconductor device according
to claim 13, wherein one selected from a group consisting of an
aluminum oxide film, an aluminum oxynitride film, a tantalum oxide
film and a titanium oxide film is formed as the hydrogen diffusion
prevention film.
18. The manufacturing method of the semiconductor device according
to claim 13, wherein thickness of the hydrogen diffusion prevention
film is made 10 nm to 100 nm.
19. The manufacturing method of the semiconductor device according
to claim 13, wherein the insulation film is formed by an
atmospheric pressure CVD method or a plasma CVD method with
tetra-ethyl ortho-silicate as a raw material.
20. The manufacturing method of a semiconductor device according to
claim 19, further comprising the step of performing plasma
treatment using plasma of N.sub.2 (nitrogen) or N.sub.2O
(dinitrogen monoxide) for the insulation film, after said step of
forming the insulation film.
21. The manufacturing method of the semiconductor device according
to claim 20, wherein in said step of performing the plasma
treatment, temperature of an inside of a treatment chamber is set
at 200.degree. C. to 450.degree. C.
22. The manufacturing method of the semiconductor device according
to claim 17, wherein the aluminum oxide film is formed by a
physical vapor deposition method, an MOCVD method or a hydrolysis
method.
23. The manufacturing method of the semiconductor device according
to claim 22, wherein a silicon oxide film or a silicon oxynitride
film by a high density plasma CVD method or a plasma CVD
method.
24. The manufacturing method of the semiconductor device according
to claim 13, wherein said step of forming the insulation film
comprises the steps of: forming a silicon oxide film or a silicon
oxynitride film by a plasma CVD method, and forming a silicon oxide
film doped with no impurity is formed by an atmospheric pressure
CVD method with tetra-ethyl ortho-silicate as a raw material.
25. The manufacturing method of the semiconductor device according
to claim 13, further comprising the step of forming a semiconductor
element on the semiconductor substrate before said step of forming
the ferroelectric capacitor, and further comprising the steps of,
after said step of forming the hydrogen diffusion prevention film:
forming one wiring layer or two or more wiring layers above the
ferroelectric capacitor; forming a water permeation prevention film
preventing permeation of water to a lower layer side above an
uppermost wiring layer located at an uppermost position of the one
wiring layer or two or more wiring layers; and forming a pad
connected to the semiconductor element above the water permeation
prevention film.
26. The manufacturing method of the semiconductor device according
to claim 25, wherein one selected from a group consisting of an
aluminum oxide film, a silicon nitride film and a silicon
oxynitride film is formed as the water permeation prevention
film.
27. The manufacturing method of the semiconductor device according
to claim 13, further comprising the steps of, after said step of
forming the hydrogen diffusion prevention film: forming an
interlayer insulation film on the hydrogen diffusion prevention
film; flattening the interlayer insulation film; forming a contact
hole reaching a part of the ferroelectric capacitor in the
interlayer insulation film, the hydrogen diffusion prevention film
and the insulation film; performing annealing at 400.degree. C. to
600.degree. C. in atmosphere containing at least one kind of gas
selected from a group consisting of oxygen and nitrogen for the
ferroelectric capacitor; and forming a wiring connected to the
ferroelectric capacitor via the contact hole.
28. A manufacturing method of a semiconductor device, comprising
the steps of: forming a semiconductor element on a semiconductor
substrate; forming one wiring layer or two or more wiring layers
above the semiconductor element; forming a water permeation
prevention film preventing permeation of water to a lower layer
side above an uppermost wiring layer located at an uppermost
position of the one wiring layer or two or more wiring layers; and
forming a pad connected to the semiconductor element above the
water permeation prevention film.
29. The manufacturing method of the semiconductor device according
to claim 28, further comprising the step of forming an insulation
film covering the uppermost wiring layer by a high density plasma
CVD method, before said step of forming the water permeation
prevention film.
30. The manufacturing method of the semiconductor device according
to claim 28, wherein one selected from a group consisting of an
aluminum oxide film, a silicon nitride film and a silicon
oxynitride film is formed, as the water permeation prevention
film.
31. The manufacturing method of the semiconductor device according
to claim 28, wherein thickness of the water permeation prevention
film is made 10 nm to 100 nm.
32. The manufacturing method of the semiconductor device according
to claim 28, further comprising the step of forming an insulation
film covering the uppermost wiring layer by a plasma CVD method
with tetra-ethyl ortho-silicate as a raw material, before said step
of forming the water permeation prevention film.
33. The manufacturing method of a semiconductor device according to
claim 28, further comprising the steps of, before said step of
forming the water permeation prevention film: forming a first
insulation film covering the uppermost wiring layer by a plasma CVD
method with tetra-ethyl ortho-silicate as a raw material;
flattening the first insulation film; performing plasma treatment
using plasma of N.sub.2O (dinitrogen monoxide) for the first
insulation film; forming a second insulation film on the first
insulation film by a plasma CVD method with tetra-ethyl
ortho-silicate as a raw material; and performing plasma treatment
using plasma of N.sub.2O (dinitrogen monoxide) for the second
insulation film, and further comprising the steps of, before said
step of forming the pad: forming a third insulation film on the
water permeation prevention film by a plasma CVD method with
tetra-ethyl ortho-silicate as a raw material; and performing plasma
treatment using plasma of N.sub.2O (dinitrogen monoxide) for the
third insulation film.
34. The manufacturing method of the semiconductor device according
to claim 28, further comprising the step of forming a ferroelectric
capacitor above the semiconductor substrate in parallel with said
step of forming the one wiring layer or two or more wiring layers
above the semiconductor element.
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor device
enhanced in endurance against permeation of hydrogen and water from
outside and a manufacturing method thereof.
BACKGROUND ART
[0002] A wiring rule in a ferroelectric memory (FeRAM) is 0.35
.mu.m recently, and in formation of an interlayer insulation film,
a plasma CVD method is mainly adopted.
[0003] In order to prevent hydrogen diffusion into a ferroelectric
capacitor, an alumina film directly covering the ferroelectric
capacitor is formed as a hydrogen diffusion prevention film in a
ferroelectric memory.
[0004] However, miniaturization is also highly demanded of a
ferroelectric memory recently, and with miniaturization, the
specifications of the ferroelectric capacitor and wiring become
rigid. Meanwhile, coverage of an alumina film is comparatively low.
For the above reasons, it cannot be said that protection of the
ferroelectric capacitor is sufficient, and deterioration of the
ferroelectric capacitor becomes a problem.
[0005] Concerning an interlayer insulation film, a gap is sometimes
generated in the interlayer insulation film between a ferroelectric
capacitor and wiring or the like when a multilayered wiring
structure is formed. Therefore, high reliability is difficult to
obtain.
[0006] Further, high moisture endurance is the characteristic which
is required in not only a ferroelectric memory but also most
semiconductor devices.
[0007] Therefore, in a multilayered wiring structure, the one
provided with an SiN film between two wiring layers is also
proposed. However, such a structure does not have sufficient
moisture resistance.
[0008] Patent Document 1
[0009] Japanese Patent Application Laid-open No. 2001-36026
[0010] Patent Document 2
[0011] Japanese Patent Application Laid-open No. 2001-15703
SUMMARY OF THE INVENTION
[0012] An object of the present invention is to provide a
semiconductor device which can suppress deterioration of a
semiconductor element such as a ferroelectric capacitor, and a
manufacturing method thereof.
[0013] In a first semiconductor device according to the present
invention, a semiconductor substrate, a ferroelectric capacitor
formed above the semiconductor substrate, and an insulation film
directly covering the ferroelectric capacitor and having an
inclination of its surface more gradual than an inclination of a
surface of the ferroelectric capacitor are provided. A hydrogen
diffusion prevention film preventing diffusion of hydrogen to the
ferroelectric capacitor is formed on the insulation film.
[0014] In a second semiconductor device according to the present
invention, a semiconductor substrate, a semiconductor element
formed on the semiconductor substrate, a pad formed above the
semiconductor substrate and connected to the semiconductor element,
and one wiring layer, or two or more wiring layers formed between
the semiconductor element and the pad are provided. A water
permeation prevention film preventing permeation of water to a
lower layer side is formed between an uppermost wiring layer
located at an uppermost position of the one wiring layer or two or
more wiring layers and the pad.
[0015] In a first manufacturing method of a semiconductor device
according to the present invention, after a ferroelectric capacitor
is formed above a semiconductor substrate, an insulation film
directly covering the ferroelectric capacitor and having an
inclination of its surface more gradual than an inclination of a
surface of the ferroelectric capacitor is formed. A hydrogen
diffusion prevention film preventing diffusion of hydrogen to the
ferroelectric capacitor is formed on the insulation film.
[0016] In a second manufacturing method of a semiconductor device
according to the present invention, after a semiconductor element
is formed on a semiconductor substrate, one wiring layer, or two or
more wiring layers is or are formed above the semiconductor
element. Next, a water permeation prevention film preventing
permeation of water to a lower layer side is formed above an
uppermost wiring layer located at an uppermost position of the one
wiring layer or two or more wiring layers. A pad connected to the
semiconductor element is formed above the water permeation
prevention film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIG. 1 is a circuit diagram showing a structure of a memory
cell array of a ferroelectric memory manufactured according to
embodiments of the present invention;
[0018] FIGS. 2A to 2G are sectional views of a manufacturing method
of a ferroelectric memory according to a first embodiment of the
present invention in sequence of process steps; and
[0019] FIGS. 3A to 3E are sectional views showing a manufacturing
method of a ferroelectric memory according to a second embodiment
of the present invention in sequence of process steps.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020] Hereinafter, embodiments of the present invention will be
explained in concrete with reference to the attached drawings. FIG.
1 is a circuit diagram showing a structure of a memory cell array
of a ferroelectric memory (semiconductor device) which is
manufactured by a method according to the embodiments of the
present invention.
[0021] This memory cell array is provided with a plurality of bit
lines 3 extending in one direction, plurality of word lines 4 and
plate lines 5 extending in the perpendicular direction to the
direction in which the bit lines 3 extend. A plurality of memory
cells of the ferroelectric memory according to the embodiments are
disposed in an array form to match a grid constituted by these bit
lines 3, word lines 4 and plate lines 5. Each memory cell is
provided with a ferroelectric capacitor 1 and a MOS transistor
2.
[0022] A gate of the MOS transistor 2 is connected to the word line
4. One source/drain of the MOS transistor 2 is connected to the bit
line 3, and the other source/drain is connected to one electrode of
the ferroelectric capacitor 1. The other electrode of the
ferroelectric capacitor 1 is connected to the plate line 5. Each of
the word lines 4 and the plate lines 5 is shared by a plurality of
MOS transistors 2 arranged in the same direction as the direction
in which they extend. Similarly, each of the bit lines 3 is shared
by a plurality of MOS transistors 2 arranged in the same direction
as the direction in which it extends. The direction in which the
word line 4 and the plate line 5 extend is sometimes called the row
direction, and the direction in which the bit line 3 extends is
sometimes called the column line.
[0023] In the memory cell array of the ferroelectric memory thus
constituted, data is stored in accordance with the polarization
state of the ferroelectric film provided on the ferroelectric
capacitor 1.
First Embodiment
[0024] Next, a first embodiment of the present invention will be
explained. Here, a structure of each memory cell is explained with
its manufacturing method for convenience. FIGS. 2A to 2G are
sectional views which show a manufacturing method of a
ferroelectric memory (semiconductor device) according to the first
embodiment of the present invention in sequence of process steps.
In FIGS. 2A o 2G, the part corresponding to two MOS transistors
sharing one bit line (corresponding to the bit line 3 in FIG. 1) is
shown.
[0025] In the first embodiment, a well 12 is formed on a surface of
a semiconductor substrate 11 of the silicon substrate or the like
first as shown in FIG. 2A. Next, an element isolation region 13 is
formed on the surface of the semiconductor substrate 11 by STI
(Shallow Trench Isolation), for example. Subsequently, gate
insulation films 14, gate electrodes 15, cap films 16, side walls
17, source/drain diffusion layers 18 and silicide layers 19 are
formed on the surface of the well 12, and thereby, MOS transistors
2 are formed as switching elements. The MOS transistor 20
corresponds to the MOS transistor 2 in FIG. 1. Two source/drain
diffusion layers 18 are formed for source and drain in each of the
MOS transistors 20, and one of them is shared by two MOS
transistors 20.
[0026] Next, a silicon oxynitride film 21 is formed on the entire
surface to cover the MOS transistor 20, and an SiO.sub.2 film 22 is
further formed on the entire surface as an interlayer insulation
film, and the SiO.sub.2 film 22 is flattened by CMP (Chemical
Mechanical Polishing) or the like. The silicon oxynitride film 21
is formed to prevent water deterioration of the gate insulation
film 14 or the like on forming the SiO.sub.2 film 22.
[0027] Thereafter, as shown in FIG. 2B, a ferroelectric capacitor
23 of a planar structure is formed on the SiO.sub.2 film 22. The
ferroelectric capacitor 23 is composed of a bottom electrode 23a, a
ferroelectric film 23b and a top electrode 23c which are layered in
sequence. The ferroelectric capacitor 23 corresponds to the
ferroelectric capacitor 1 in FIG. 1.
[0028] Subsequently, as shown in FIG. 2C, an insulation film 24
having an inclination of its surface more gradual than the
inclination of the surface of the ferroelectric capacitor 23 is
formed. As the insulation film 24, an SiO.sub.2 film doped with no
impurity (NSG (Non-doped Silicate Glass) film), an SiO.sub.2 film
doped with P (PSG (Phospho-Silicate Glass) film), an SiO.sub.2 film
doped with B and P (BPSG (Boron Phospho-Silicate Glass) film), an
SiO.sub.2 film doped with F (FSG (Fluoro-Silicate Glass) film) and
the like may be formed, by an atmospheric-pressure CVD method with
TEOS (Tetra-Ethyl Ortho-Silicate) and O.sub.3 being used, for
example. As the insulation film 24, an NSG film, a PSG film, a BPSG
film, an FSG film, SiON film and the like may be formed by a high
density plasma (HDP: High Density Plasma) CVD method, for example.
Further, as the insulation film 24, an SiO.sub.2 film, SiON film
and the like may be formed by a plasma CVD method.
[0029] It should be noted that, when the insulation film 24 is
formed by the atmospheric pressure CVD method or the plasma CVD
method, it is preferable to reduce water in the insulation film 24
and improve the film quality of the insulation film 24 by
performing plasma treatment using plasma of N.sub.2 or N.sub.2O for
the insulation film 24. It is preferable to set the treatment
temperature at this time at 200.degree. C. to 450.degree. C.
[0030] When the insulation film 24 is formed by the atmospheric
pressure CVD method, it is preferable to form an SiO.sub.2 film or
an SiON film of about 300 .ANG. to 1000 .ANG. by a plasma CVD
method. This is for enhancement of coverage and prevention of
permeation of water into the ferroelectric capacitor 23.
[0031] Further, it is preferable to set the temperature of the
semiconductor substrate 11 at the time of film forming at
175.degree. C. to 350.degree. C. This is because there is a
possibility that the coverage becomes low if the temperature is
lower than 175.degree. C. and there is a possibility that the
ferroelectric capacitor 23 already formed is broken if the
temperature exceeds 350.degree. C.
[0032] Next, as shown in FIG. 2D, an alumina film (aluminum oxide
film) 25 is formed on the insulation film 24 as a hydrogen
diffusion prevention film. Since steep portions exist on side
surfaces or the like of the ferroelectric capacitor 23,
insufficient coverage occurs when the alumina film is formed to
directly cover the ferroelectric capacitor 23, but in this
embodiment, low coverage of the alumina film 25 does not matter,
because the insulation film 24 is formed and the inclination of its
surface is gradual.
[0033] Next, as shown in FIG. 2E, an Si oxide film 26 is formed on
the entire surface as an interlayer insulation film, and flattening
of the Si oxide film 26 is performed by CMP or the like.
[0034] Thereafter, as shown in FIG. 2F, a contact hole which
reaches each of the silicide layers 19 is formed in the Si oxide
film 26, the alumina film 25, the insulation film 24, the SiO.sub.2
film 22 and the silicon oxynitride film 21, and thereby, a plug
contact part is opened, with patterning and etching techniques
used. Subsequently, a barrier metal film (not shown) is formed in
each contact hole, and a W film is buried in an inside thereof by a
CVD method, for example, and the W film is flattened by performing
CMP, whereby W plugs 27 and 28 are formed. The W plug 28 is one
connected to the silicide layer 19 shared by the two MOS
transistors 20, and the W plug 27 is another one connected to the
remaining silicide layer 19.
[0035] Next, as shown in FIG. 2G, contact holes which reach the top
electrodes 23c are formed in the Si oxynitride film 26, the alumina
film 25 and the insulation film 24, with patterning and etching
techniques used. Subsequently, wirings 29 which connect the top
electrodes 23c and the W plugs 27 via the contact holes and a
wiring 30 which is connected to the W plug 28 is formed, on the Si
oxide film 26.
[0036] It is preferable to perform annealing at 400.degree. C. to
600.degree. C. for the ferroelectric capacitor 23 in oxygen
atmosphere, nitrogen atmosphere, or the atmosphere of the mixture
gas of them, before formation of the wirings 29 and 30. By
performing such annealing, the characteristic of the ferroelectric
capacitor 23 which is deteriorated in the process steps so far is
recovered.
[0037] Thereafter, formation of interlayer insulation films,
formation of contact plugs, formation of wirings from the second
layer onward and the like are performed. Subsequently, a
passivation film composed of a silicon oxide film and an
Si.sub.3N.sub.4 film, for example, is formed, and thereby, a
ferroelectric memory having a ferroelectric capacitor is completed.
On forming the upper wiring, a wiring (not shown) connected to the
bottom electrode 23a is connected to the plate line (corresponding
to the plate line 5 in FIG. 1), and the wiring 29 is connected to
the bit line (corresponding to the bit line 3 in FIG. 1). As for
the gate electrode 15, the gate electrode 15 itself may be made the
word line, and the gate electrode 15 may be connected to the word
line in the upper wiring.
[0038] According to the first embodiment, coverage of the alumina
film 25 does not become a problem, and therefore, permeation of
hydrogen into the ferroelectric capacitor 23 can be reliably
prevented. Namely, it becomes possible to reliably protect the
ferroelectric capacitor 23.
[0039] Especially when a silicon oxynitride film is formed by a
high density plasma CVD method as the insulation film 24, this
insulation film 24 also functions as the water permeation
prevention film, and therefore, the ferroelectric capacitor 23 can
be protected more firmly.
[0040] It is preferable that the thickness of the hydrogen
diffusion preventing film is 10 nm to 100 nm. This is because if
the thickness is less than 10 nm, there is a possibility that
diffusion of hydrogen cannot be prevented sufficiently, and if the
thickness exceeds 100 nm, etching of the hydrogen diffusion
preventing film becomes difficult.
[0041] As a hydrogen diffusion preventing film, an Al oxynitride
film, a Ta oxide film, a Ti oxide film and the like may be formed
other than the alumina film.
Second Embodiment
[0042] Next, a second embodiment of the present invention will be
explained. Here, a structure of a semiconductor device will be
explained with its manufacturing method for convenience. FIGS. 3A
to 3E are sectional views showing a manufacturing method of a
ferroelectric memory (semiconductor device) according to the second
embodiment of the present invention in sequence of the process
steps.
[0043] In the second embodiment, after a semiconductor element (not
shown) and the like are formed on a semiconductor substrate (not
shown) as in the first embodiment, an interlayer insulation film 31
is formed above the semiconductor substrate as shown in FIG.
3A.
[0044] Next, a raw material film of a bottom electrode (bottom
electrode film), a ferroelectric film and a raw material film of a
top electrode (top electrode film) are sequentially deposited on
the interlayer insulation film 31, and by patterning the top
electrode film and the ferroelectric film, a top electrode 34 and a
ferroelectric capacity insulation film 33 are formed. Next, an
alumina film 35 is formed on an entire surface, and the alumina
film 35 and the bottom electrode film are patterned, whereby a
bottom electrode 32 is formed. Subsequently, an alumina film 36 is
formed on the entire surface. The thickness of the alumina films 35
and 36 are, for example, about 50 nm and 20 nm respectively.
[0045] Thereafter, an interlayer insulation film 37 is formed on
the entire surface, and a contact hole is formed in the interlayer
insulation film 37, the alumina film 36 and the interlayer
insulation film 31, and a W plug 38 is buried in the contact hole.
Further, contact holes which respectively reach the top electrode
34 and the bottom electrode 32 are formed in the interlayer
insulation film 37, the alumina film 36 and the alumina film 35.
Then, an Al wiring 39 connected to the top electrode 34, an Al
wiring 40 connected to the bottom electrode 32, and an Al wiring 41
connected to the W plug 38 are formed on the interlayer insulation
film 37. Subsequently, an alumina film 42 of the thickness of about
20 nm is formed on the entire surface, and an interlayer insulation
film 43 is formed thereon.
[0046] Next, a contact hole which reaches the Al wiring 41 and the
like is formed in the interlayer insulation film 43 and the alumina
film 42, and a W plug 44 is buried in this contact hole. Next, an
Al wiring 45 is formed on the interlayer insulation film 43.
[0047] Thereafter, as shown in FIG. 3B, an SiO.sub.2 film 46 of the
thickness of about 2.2 .mu.m is formed by a plasma CVD method with
TEOS as a raw material. Subsequently, the SiO.sub.2 film 46 is
flattened by being polished until it has the thickness of about 1.0
.mu.m by CMP. Thereafter, plasma treatment using N.sub.2O is
performed for the SiO.sub.2 film 46, and thereby, water existing in
the SiO.sub.2 film 46 is reduced.
[0048] Subsequently, as shown in FIG. 3C, an SiO.sub.2 film 47 of
the thickness of about 100 nm is formed on the entire surface by a
plasma CVD method with TEOS as a raw material. Then, plasma
treatment using N.sub.2O is performed for the SiO.sub.2 film 47,
and thereby, water existing in the SiO.sub.2 film 47 is reduced.
Next, an alumina film 48 is formed on the SiO.sub.2 film 47 as a
water permeation prevention film, and an SiO.sub.2 film 49 of the
thickness of about 100 nm is formed on the alumina film 48 with
TEOS as a raw material by a plasma CVD method. Then, plasma
treatment using N.sub.2O is performed for the SiO.sub.2 film 49,
and thereby, water existing in the SiO.sub.2 film 49 is reduced.
Then, a contact hole which reaches the Al wiring 45 is formed, and
a W plug 50 is buried in this contact hole. The thickness of the
alumina film 48 is about 50 nm, for example.
[0049] When the SiO.sub.2 film 46 is formed by an HDP (High Density
Plasma) CVD method, and a void (pore) does not occur in the
SiO.sub.2 film 46, after N.sub.2O plasma treatment is performed as
necessary after flattening by CMP, and the alumina film 48 may be
directly formed on the SiO.sub.2 film 46 without forming the
SiO.sub.2 film 47.
[0050] Next, as shown in FIG. 3D, an Al wiring 51 is formed on the
SiO.sub.2 film 49. At this time, as shown in FIG. 3E, a pad 54 for
wire-bonding is formed at the same layer as the Al wiring 51.
Namely, an Al film is formed on the SiO.sub.2 film 49, and by
patterning this, the Al wiring 51 and the pad 54 are formed from
the same Al film.
[0051] Thereafter, as shown in FIGS. 3D and 3E, a high density
plasma SiO.sub.2 film 52 and Si.sub.3N.sub.4 film 53 are
sequentially formed on the entire surface as a passivation film.
Then, an opening for exposing a part of the pad 54 is formed in the
high density plasma SiO.sub.2 film 52 and Si.sub.3N.sub.4 film
53.
[0052] According to the second embodiment, permeation of water into
the semiconductor element (ferroelectric capacitor and the like)
can be prevented more reliably. Namely, when a water permeation
prevention film is formed to cover the ferroelectric capacitor,
wiring and the like, there is a possibility that water permeates
onto the water permeation prevention film and water concentrates
thereon and thereafter, the water permeates into the semiconductor
element, but if the water permeation prevention film (alumina film
48) is formed between the pad 54 and the wiring layer on the
uppermost layer as in this embodiment, water hardly reaches the
semiconductor element, and therefore, water permeation can be
prevented more reliably.
[0053] The alumina film 48 used as the water permeation prevention
film in the second embodiment also has a function of preventing
diffusion of hydrogen. Therefore, it is also possible to suppress
deterioration of the ferroelectric capacitor by hydrogen.
Accordingly, it is preferable to use the water permeation
prevention film which not only can prevent permeation of water but
also can prevent diffusion of hydrogen, as the water permeation
prevention film.
[0054] Here, the result of the moisture resistance test which the
inventors of the present application actually made will be
explained. In this moisture resistance test, the produced
semiconductor devices were placed under the conditions of the
predetermined temperature and humidity, and it was examined whether
the semiconductor devices normally operated 72 hours later, 168
hours later and 336 hours later. The results are shown in Table 1
to Table 3. In example 1, the alumina film was formed as the water
permeation prevention film between the uppermost wiring layer
(wiring layer located at the uppermost position) and the pad as in
the second embodiment. On the other hand, in the comparative
example 2, such an alumina film as in example 1 was not formed. The
denominators of "the number of failures" in Table 1 to Table 3 are
the total numbers of specimens used in measurement, and the
numerators are the total numbers of the specimens which were
determined as fail because they did not operate normally. As shown
in Table 1 to Table 3, example 1 according to the second embodiment
was extremely excellent in moisture resistance for a long period of
time.
[0055] After an insulation film is formed by a high density plasma
CVD method so as to cover a wiring layer on the uppermost layer, a
water permeation prevention film may be formed thereon.
[0056] It is preferable that the thickness of a water permeation
prevention film is 10 nm to 100 nm. This is because if the
thickness is less than 10 nm, permeation of water cannot be
sufficiently prevented, and if the thickness exceeds 100 nm, it
becomes difficult to etch the water permeation prevention film.
[0057] Further, as a water permeation prevention film, a silicon
nitride film, a silicon oxynitride film, a tantalum oxide film, a
titanium oxide film and the like may be formed other than an
alumina film.
[0058] A pad is not limited to the use for wire-bonding, and a bump
may be formed on, for example, the pad.
[0059] In any of the first and the second embodiments, a forming
method of the alumina film is not specially limited. For example,
the alumina film may be formed by a physical vapor deposition
method, or an MOCVD method, or the alumina film may be formed with
hydrolysis expressed by the following chemical formula.
[0060] -Chemical Formula-
2AlCl.sub.3+3H.sub.2O.fwdarw.Al.sub.2O.sub.3+6HCl .Arrow-up
bold.
[0061] In formation of a passivation film, it is preferable to form
a silicon oxide film under an Si.sub.3N.sub.4 film by a high
density plasma CVD method, or it is preferable to form two silicon
oxide films by a high density plasma CVD method, to form a hydrogen
diffusion prevention film therebetween and to form an
Si.sub.3N.sub.4 film on the upper silicon oxide film. A TEOS oxide
film may be used as the silicon oxide film under the
Si.sub.3N.sub.4 film.
[0062] Further, a wiring material is not limited to Al. For
example, Cu wiring or Al--Cu alloy wiring may be used. In formation
of the contact plug, it is preferable to form a barrier metal film
composed of a TiN film and a Ti film sequentially formed, or a
barrier metal film composed of only a TiN film in a contact hole
before the W plug is buried.
[0063] As a capacity insulation film (ferroelectric film) of a
ferroelectric capacitor, for example, a PZT (Pb (Zr, Ti) O.sub.3)
film, a SBT (SrBi.sub.2Ta.sub.2O.sub.9) film, or the like can be
used. The methods for forming these films are not specially
limited, and, they can be formed by, for example, an MOCVD
method.
[0064] Both effects can be obtained by applying the first
embodiment and the second embodiment at the same time.
INDUSTRIAL APPLICABILITY
[0065] As explained in detail thus far, according to the present
invention, permeation of hydrogen or water can be prevented more
reliably by the hydrogen diffusion prevention film or the water
permeation prevention film. Therefore, reliability is enhanced, and
yield and productivity are increased.
1 TABLE 1 72 HOURS LATER NUMBER OF FAILURES FAILURE RATE (%)
EXAMPLE 1 0/20 0.0 COMPARATIVE 0/20 0.0 EXAMPLE 2
[0066]
2 TABLE 2 168 HOURS LATER NUMBER OF FAILURES FAILURE RATE (%)
EXAMPLE 1 0/20 0.0 COMPARATIVE 0/20 0.0 EXAMPLE 2
[0067]
3 TABLE 3 336 HOURS LATER NUMBER OF FAILURES FAILURE RATE (%)
EXAMPLE 1 0/20 0.0 COMPARATIVE 8/20 40.0 EXAMPLE 2
* * * * *