U.S. patent application number 11/111582 was filed with the patent office on 2005-09-01 for nanotube films and articles.
This patent application is currently assigned to Nantero, Inc.. Invention is credited to Rueckes, Thomas, Segal, Brent M..
Application Number | 20050191495 11/111582 |
Document ID | / |
Family ID | 29215412 |
Filed Date | 2005-09-01 |
United States Patent
Application |
20050191495 |
Kind Code |
A1 |
Rueckes, Thomas ; et
al. |
September 1, 2005 |
Nanotube films and articles
Abstract
Nanotube films and articles and methods of making the same are
disclosed. A conductive article or a substrate comprises at least
two unaligned nanotubes extending substantially parallel to the
substrate and each contacting end points of the article but each
unaligned relative to the other, the nanotubes providing a
conductive pathway within a predefined space.
Inventors: |
Rueckes, Thomas; (Rockport,
MA) ; Segal, Brent M.; (Woburn, MA) |
Correspondence
Address: |
WILMER CUTLER PICKERING HALE AND DORR LLP
60 STATE STREET
BOSTON
MA
02109
US
|
Assignee: |
Nantero, Inc.
|
Family ID: |
29215412 |
Appl. No.: |
11/111582 |
Filed: |
April 21, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11111582 |
Apr 21, 2005 |
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10776573 |
Feb 11, 2004 |
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10776573 |
Feb 11, 2004 |
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10128118 |
Apr 23, 2002 |
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6706402 |
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10128118 |
Apr 23, 2002 |
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09915173 |
Jul 25, 2001 |
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6643165 |
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10128118 |
Apr 23, 2002 |
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09915095 |
Jul 25, 2001 |
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6574130 |
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10128118 |
Apr 23, 2002 |
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09915093 |
Jul 25, 2001 |
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6919592 |
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Current U.S.
Class: |
428/408 ;
257/E21.582; 257/E27.004; 257/E27.07; 257/E27.112 |
Current CPC
Class: |
H01L 51/0017 20130101;
G11C 2213/77 20130101; C01B 2202/22 20130101; D01F 9/127 20130101;
H01L 51/0003 20130101; Y10T 428/24802 20150115; B82Y 40/00
20130101; Y10S 977/778 20130101; Y10S 977/742 20130101; G11C
2213/16 20130101; D04H 1/4242 20130101; H01L 51/0048 20130101; Y10T
428/2918 20150115; H01L 21/76838 20130101; H01L 27/10 20130101;
G11C 13/025 20130101; H01L 27/1203 20130101; Y10S 977/75 20130101;
C01B 32/162 20170801; H01L 2221/1094 20130101; Y10T 428/2982
20150115; Y10T 428/30 20150115; B82Y 10/00 20130101; H01L 51/0098
20130101; G11C 23/00 20130101; Y10S 977/943 20130101; D04H 1/43838
20200501; C01B 2202/02 20130101; D04H 1/4234 20130101; G11C 2213/81
20130101; B82Y 30/00 20130101 |
Class at
Publication: |
428/408 |
International
Class: |
B32B 009/00 |
Claims
What is claimed is:
1. A conductive article or a substrate comprising: at least two
unaligned nanotubes extending substantially parallel to the
substrate and each contacting end points of the article but each
unaligned relative to the other, the nanotubes providing a
conductive pathway within a predefined space.
2. The article of claim 1, wherein the nanotubes include
single-walled nanotubes.
3. The article of claim 1, wherein the nanotubes include
multi-walled nanotubes.
4. The article of claim 1, wherein the nanotubes have different
lengths.
5. The article of claim 1, wherein the nanotubes are of a
controllable density.
6. A conductive article comprising: at least two unaligned
nanotubes extending substantially parallel to a substrate and each
contacting end points of the article but each unaligned relative to
the other, wherein the nanotubes conform to a non-planar surface of
a substrate.
7. The conductive article of claim 6, wherein the nanotubes form a
conductive pathway within a predefined space.
8. The article of claim 6, wherein the nanotubes include
single-walled nanotubes.
9. The article of claim 6, wherein the nanotubes include
multi-walled nanotubes.
10. The article of claim 6, wherein the nanotubes have different
lengths.
11. The article of claim 6, wherein the nanotubes form a conformal
layer.
12. The article of claim 6, wherein the nanotubes are of a
controllable density.
13. A method of making a conductive article on a substrate
comprising: providing a layer of nanotubes on a substrate, said
nanotube layer comprising at least two unaligned nanotubes, the
nanotubes being substantially parallel to a surface of the
substrate; and selectively patterning the layer to define an
electrically conductive element having the unaligned nanotubes.
14. The method of claim 13, wherein the layer comprises nanotubes
of a controllable density.
15. The method of claim 13, wherein the nanotube layer is provided
by dipping, spraying or spincoating.
16. The method of claim 13, wherein patterning is provided by
selectively removing a portion of the nanotube layer.
17. The method of claim 16, wherein selective removal comprises a
stencil.
18. The method of claim 16, wherein selective removal comprises
photoresist.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 10/776,573 filed on Feb. 11, 2004, entitled
NANOTUBE FILMS AND ARTICLES, which is a continuation of U.S. patent
application Ser. No. 10/128,118, filed on Apr. 23, 2002, entitled
NANOTUBE FILMS AND ARTICLES, which is a continuation-in-part and
claims priority under 35 U.S.C. .sctn. 120 to the following
applications, and all of which are incorporated herein by reference
in their entirety:
[0002] U.S. patent application Ser. No. 09/915,093, filed Jul. 25,
2001, entitled ELECTROMECHANICAL MEMORY ARRAY USING NANOTUBE
RIBBONS AND METHOD FOR MAKING SAME;
[0003] U.S. patent application Ser. No. 09/915,095, filed Jul. 25,
2001, now U.S. Pat. No. 6,574,130, entitled HYBRID CIRCUIT HAVING
NANOTUBE ELECTROMECHANICAL MEMORY; and
[0004] U.S. patent application Ser. No. 09/915,173, filed Jul. 25,
2001, now U.S. Pat. No. 6,643,165, entitled ELECTROMECHANICAL
MEMORY HAVING CELL SELECTION CIRCUITRY CONSTRUCTED WITH NANOTUBE
TECHNOLOGY.
BACKGROUND
[0005] 1. Technical Field
[0006] This invention relates in general to carbon nanotube films,
fabrics, layers, and articles and in particular to making
electrically conductive articles from carbon nanotube films,
fabrics, or layers for a variety of uses in circuits or the
like.
[0007] 2. Discussion of Related Art
[0008] The reliable fabrication of electrically conductive,
ultra-thin metallic layers and electrodes in the sub-10 nm regime
is problematic, see, e.g., S. Wolf, Silicon Processing for the VLSI
era; Volume 2--Process Integration (Lattice Press, Sunset Beach,
1990). Metal films in this size regime are usually non-continuous
and not conductive over macroscopic distances. Furthermore, these
sub-10 nm films are prone to thermal damage by electrical current
making them unsuitable for applications such as electrical
interconnects in semiconductor devices. Thermal damage of thin
metal interconnects caused by their low heat conductivities is one
of the main factors inhibiting dramatic miniaturization and
performance improvements of highly integrated semiconductor
devices.
[0009] Conventional interconnect technologies have a tendency to
suffer from thermal damage and metal diffusion eroding the
performance of the semiconductor devices especially from
degradation of the electrical properties. These effects become even
more pronounced with size reduction in current generation 0.18 um
and 0.13 um structures, e.g. by metal diffusion through ultra-thin
gate oxide layers.
[0010] There is therefore a need in the art for conductive elements
that may operate well in contexts having high current densities or
in extreme thermal conditions. This includes circuit contexts with
very small feature sizes but includes other high current density
extreme thermal environment contexts as well. There is also a need
for conductive elements that will be less likely to diffuse
undesirable amounts of contaminants into other circuit
elements.
SUMMARY
[0011] The invention provides nanotube films and articles and
methods of making the same. Under one aspect of the invention, a
conductive article or a substrate comprises at least two unaligned
nanotubes extending substantially parallel to the substrate and
each contacting end points of the article but each unaligned
relative to the other, the nanotubes providing a conductive pathway
within a predefined space.
[0012] Under other aspects of the invention, the nanotube segments
may be single walled carbon nanotubes, or multi-walled carbon
nanotubes. The various segments may have different lengths and may
include segments having a length shorter than the length of the
article.
[0013] Under other aspects of the invention, the nanotubes have a
controllable density.
[0014] Under another aspect of the invention, a conductive article
comprises at least two unaligned nanotubes extending substantially
parallel to a substrate and each contacting end points of the
article but each unaligned relative to the other, wherein the
nanotubes conform to a non-planar surface of a substrate.
[0015] Under another aspect of the invention, a method of making a
conductive article on a substrate includes providing a layer of
nanotubes on a substrate. The nanotube layer comprises at least two
unaligned nanotubes, the nanotubes being substantially parallel to
a surface of the substrate. The layer is selectively patterned to
define an electrically conductive element having the unaligned
nanotubes.
BRIEF DESCRIPTION OF THE DRAWING
[0016] In the Drawing,
[0017] FIG. 1 illustrates a nanotube belt crossbar memory device
according to certain embodiments of the invention;
[0018] FIGS. 2A-B illustrate two states of a memory cell according
to certain embodiments of the invention;
[0019] FIGS. 3 and 3a illustrate acts of making memory devices
according to certain embodiments of the invention;
[0020] FIGS. 4-11 illustrate several forms of creating an
intermediate structure used to make memory devices according to
certain embodiments of the invention;
[0021] FIG. 12 illustrates the non-woven nanotube fabric, or matted
nanotube layer, used to make certain embodiments of the
invention;
[0022] FIG. 13 illustrates the matted nanotube layer in relation to
hidden, underlying traces of certain embodiments of the
invention;
[0023] FIG. 14 illustrates addressing logic of certain embodiments
of the invention;
[0024] FIG. 15 illustrates a hybrid technology embodiment of the
invention in which the memory core uses nanotube technology;
[0025] FIG. 16 illustrates a hybrid technology embodiment of the
invention in which the memory core and addressing lines use
nanotube ribbon technology;
[0026] FIGS. 17 and 17a illustrate acts of making electrically
conductive articles according to certain embodiments of the
invention;
[0027] FIG. 18 illustrates how electrically conductive articles
according to certain embodiments of the invention may be used to
connect electrical components;
[0028] FIG. 19 illustrates a way of creating an intermediate
structure according to certain embodiments of the invention;
and
[0029] FIG. 20 illustrates a non-woven nanotube fabric, or matted
nanotube layer, used to make certain embodiments of the
invention.
DETAILED DESCRIPTION
[0030] New electromechanical memory arrays and methods for making
same are disclosed in which electromechanical memory cells are
created that operate analogously to the NTWCM devices disclosed in
WO 01/03208, which is hereby incorporated by reference in its
entirety. However, unlike the NTWCM devices disclosed in WO
01/03208, new ribbons or belts made from a matted layer of
nanotubes or a non-woven fabric of nanotubes are used as an
electrically conductive element. At points in this disclosure, the
ribbons are referred to as traces or electrically conductive
articles. In some instances, the ribbons are suspended, and in
other instances they are disposed on a substrate. In some
instances, they are used to deflect to certain states under
electrical control, and in other instances they do not move and
instead are used simply to carry an electrical current or voltage.
The new nanotube belt structures are believed to be easier to build
at the desired levels of integration and scale (in number of
devices made) and the geometries are more easily controlled. The
new nanotube ribbons are believed to be able to more easily carry
high current densities without suffering the above-outlined
problems experienced or expected with metal traces.
[0031] Under certain embodiments of the invention, electrically
conductive articles may be made from a nanotube fabric, layer, or
film. Carbon nanotubes with tube diameters as little as 1 nm are
electrical conductors that are able to carry extremely high current
densities, see, e.g., Z. Yao, C. L. Kane, C. Dekker, Phys. Rev.
Lett. 84, 2941 (2000). They also have the highest known heat
conductivity, see, e.g., S. Berber, Y.-K. Kwon, D. Tomanek, Phys.
Rev. Lett. 84, 4613 (2000), and are thermally and chemically
stable, see, e.g., P. M. Ajayan, T. W. Ebbesen, Rep. Prog. Phys.
60, 1025 (1997). However, using individual nanotubes is problematic
because of difficulties in growing them with suitably controlled
orientation, length, and the like. Creating traces from nanotube
fabrics allows the traces to retain many if not all of the benefits
of individual nanotubes. Moreover, traces made from nanotube fabric
have benefits not found in individual nanotubes. For example, since
the traces are composed of many nanotubes in aggregation, the trace
will not fail as the result of a failure or break of an individual
nanotube. Instead, there are many alternate paths through which
electrons may travel within a given trace. In effect, a trace made
from nanotube fabric creates its own electrical network of
individual nanotubes within the defined trace, each of which may
conduct electrons. Moreover, by using nanotube fabrics, layers, or
films, current technology may be used to create such traces.
[0032] Nanotube Ribbon Crossbar Memories (NTRCM)
[0033] Because the new nanotube belt crossbar memory devices
operate analogously to NTWCM, the description of their architecture
and principles of operation is brief. Reference may be made to WO
01/03208 for fuller description and background.
[0034] FIG. 1 illustrates an exemplary electromechanical memory
array 100 constructed according to principles of preferred
embodiments of the invention.
[0035] The array has a plurality of non-volatile memory cells 103
which can be in an "on" state 105 or "off" state 106. The actual
number of such cells is immaterial to understanding the invention
but the technology may support devices having information storage
capacities equivalent to or larger than modern non-volatile circuit
devices.
[0036] Each memory cell 103 includes a nanotube ribbon 101
suspended by one or more supports 102 over electrical traces or
wires, e.g., 104.
[0037] Each crossing of a ribbon 101 and a wire, e.g., 104 forms a
crossbar junction and defines a memory cell. Under certain
embodiments, each cell may be read or written by applying currents
and or voltages to electrodes 112 which are in electrical
communication with ribbons 101 or through electrodes (not shown) in
communication with traces or wires 104. The supports 102 are made
from a layer 108 of silicon nitride (Si3N4). Below layer 108 is a
gate oxide layer 109 separating the n-doped silicon traces 104 from
an underlying silicon wafer 110.
[0038] Referring conjointly to FIGS. 1-2B, junction 106 illustrates
the cell in a first physical and electrical state in which the
nanotube ribbon 101 is separated from corresponding trace 104.
Junction 105 illustrates the cell in a second physical and
electrical state in which the nanotube ribbon 101 is deflected
toward corresponding trace 104. In the first state, the junction is
an open circuit, which may be sensed as such on either the ribbon
101 or trace 104 when so addressed. In the second state, the
junction is a rectified junction (e.g., Schottky or PN), which may
be sensed as such on either the tube 101 or trace 104 when so
addressed.
[0039] Under certain embodiments, the nanotube ribbon 101 may be
held in position at the supports by friction. In other embodiments
the ribbon may be held by other means, such as by anchoring the
ribbons to the supports using any of a variety of techniques. This
friction can be increased through the use of chemical interactions
including covalent bonding through the use of carbon compounds such
as pyrenes or other chemically reactive species. Evaporated or
spin-coated material such as metals, semiconductors or insulators
especially silicon, titanium, silicon oxide or polyimide could also
be added to increase the pinning strength. The nanotube ribbons or
individual nanotubes can also be pinned through the use wafer
bonding to the surface. See R. J. Chen et al., "Noncovalent
Sidewall Functionalization of Single-Walled Carbon Nanotubes for
Protein Immobilization," J. Am. Chem. Soc., 123, 2001, 3838-39 and
Dai et al., Appl. Phys. Lett., 77, 2000, 3015-17 for exemplary
techniques for pinning and coating nanotubes by metals. See also
WO01/03208 for techniques.
[0040] Under certain preferred embodiments as shown in FIGS. 2A-B,
a nanotube ribbon 101 has a width of about 180 nm and is pinned to
a support 102 preferably fabricated of silicon nitride. The local
area of trace 104 under ribbon 101 forms an n-doped silicon
electrode and is positioned close to the supports 102 and
preferably is no wider than the belt, e.g., 180 nm. The relative
separation 208 from the top of the support 102 to the deflected
position where the belt 101 attaches to electrode 206 (see FIG. 2B)
should be approximately 5-50 nm. The magnitude of the separation
208 is designed to be compatible with electromechanical switching
capabilities of the memory device. For this embodiment, the 5-50 nm
separation is preferred for certain embodiments utilizing ribbons
101 made from carbon nanotubes, but other separations may be
preferable for other materials. This magnitude arises from the
interplay between strain energy and adhesion energy of the
deflected nanotubes. These feature sizes are suggested in view of
modern manufacturing techniques. Other embodiments may be made with
much smaller (or larger) sizes to reflect the manufacturing
equipment's capabilities.
[0041] The nanotube ribbon 101 of certain embodiments is formed
from a non-woven fabric of entangled or matted nanotubes (more
below). The switching parameters of the ribbon resemble those of
individual nanotubes. Thus, the predicted switching times and
voltages of the ribbon should approximate the same times and
voltages of nanotubes. Unlike the prior art which relies on
directed growth or chemical self-assembly of individual nanotubes,
preferred embodiments of the present invention utilize fabrication
techniques involving thin films and lithography. This method of
fabrication lends itself to generation over large surfaces
especially wafers of at least six inches. (In contrast, growing
individual nanotubes over a distance beyond sub millimeter
distances is currently unfeasible.) The ribbons should exhibit
improved fault tolerances over individual nanotubes, by providing
redundancy of conduction pathways contained with the ribbons. (If
an individual nanotube breaks other tubes within the rib provide
conductive paths, whereas if a sole nanotube were used the cell
would be faulty.) Moreover, the resistances of the ribbons should
be significantly lower than that for an individual nanotubes, thus,
decreasing its impedance, since the ribbons may be made to have
larger cross-sectional areas than individual nanotubes.
[0042] FIG. 3 illustrates a method of making certain embodiments of
NTRCM devices 100. A first intermediate structure 302 is created or
provided. In the illustrated embodiment, the structure 302 includes
a silicon substrate 110 having an insulating layer 109 (such as
silicon dioxide) and a silicon nitride layer (Si3N4) 108 that
defines a plurality of supports 102. In this instance, the supports
102 are formed by rows of patterned silicon nitride, though many
other arrangements are possible, such as a plurality of columns.
Conductive traces 104 extend between supports 102. In this
instance, the traces 104 are shown as essentially contacting the
supports 102, but other arrangements are possible as are other
geometries; for example, spaces may exist between trace 104 and
support 102 and trace 104 may be fashioned as a wire or may have
non-rectangular transverse, cross-sections, including triangular or
trapezoidal. Sacrificial layers 304 are disposed above the traces
104 so as to define one planar surface 306 with the upper surface
of the supports 102. This planar surface, as will be explained
below, facilitates growth of a matted nanotube layer of certain
embodiments.
[0043] Once such a structure 302 is created or provided, the upper
surface 306 receives a catalyst 308. For example, under certain
embodiments, a catalyst metal 308, containing iron (Fe), molybdenum
(Mo), cobalt or other metals, is applied by spin-coating or other
application techniques to create a second intermediate structure
310.
[0044] A matted layer 312 of nanotubes is then grown into a
non-woven fabric of single-walled carbon nanotubes (SWNTs) to form
a third intermediate structure 314. For example, the second
intermediate structure 310 may be placed into an oven and heated to
a high temperature (for example, about 800-1200.degree. C.) while
gases containing a carbon source, hydrogen and inert gas, such as
argon or nitrogen, are flowed over the upper surface. This
environment facilitates the generation or growth of the matted
layer or film 312 of single-walled carbon nanotubes. The layer 312
is primarily one nanotube thick and the various tubes adhere to one
another via Van der Waals forces. Occasionally, one nanotube grows
over the top of another, though this growth is relatively
infrequent due to the growth tendencies of the material. Under some
embodiments (not shown), the catalyst 308 may be patterned to
assist in growing the nanotubes with specific densities either more
or less dense as is desired. When conditions of catalyst
composition and density, growth environment, and time are properly
controlled, nanotubes can be made to evenly distribute over a given
field that is primarily a monolayer of nanotubes. Proper growth
requires control of parameters including but not limited to
catalyst composition and concentration, functionalization of the
underlying surface, spin coating parameters (length and RPM),
growth time, temperature and gas concentrations.
[0045] A photoresist may then be applied to the layer 312 and
patterned to define ribbons in the matted layer of nanotubes 312.
The ribbon patterns cross (for example, perpendicularly) the
underlying traces 104. The photoresist is removed to leave ribbons
101 of non-woven nanotube fabric lying on planar surface 306 to
form fourth intermediate structure 318.
[0046] The fourth intermediate structure 318 has portions 320 of
its underlying sacrificial layer 304 exposed as shown. The
structure 318 is then treated with an acid, such as HF, to remove
the sacrificial layer 304, including the portion under the ribbons
101, thus forming an array 322 of ribbons 101 suspended over traces
104 and supported by supports 102.
[0047] Subsequent metalization may be used to form addressing
electrodes, e.g., 112 shown in FIG. 1.
[0048] One aspect of the above technique is that the various
growth, patterning, and etching operations may use conventional
techniques, such as lithographic patterning. Currently, this may
entail feature sizes (e.g., width of ribbon 101) of about 180 nm to
as low as 130 nm, but the physical characteristics of the
components are amenable to even smaller feature sizes if
manufacturing capabilities permit.
[0049] As will be explained below, there are many possible ways of
creating the intermediate structures or analogous structures
described above. FIG. 4, for example, shows one way to create the
first intermediate structure 302.
[0050] A silicon wafer 400 is provided with an oxide layer 402. The
oxide layer is preferably a few nanometers in thickness but could
be as much 1 .quadrature.m. A silicon nitride (Si3N4) layer 404 is
deposited on top of the oxide surface 402. The silicon nitride
layer is preferably at least 30 nm thick.
[0051] The silicon nitride layer 404 is then patterned and etched
to generate cavities 406 to form support structure 407. With modern
techniques the cavity width may be about 180 nm wide or perhaps
smaller. The remaining silicon nitride material defines the
supports 102 (e.g., as row, or perhaps columns).
[0052] A covering 408 of n-doped silicon is then deposited to fill
the cavities 406. The covering 408 for exemplary embodiments may be
about 1 .quadrature.m thick but may be as thin as 30 nm.
[0053] The covering 408 is then processed, for example by
self-flattening of thick silicon layers or by annealing, to produce
a planar surface 306, discussed above, to form structure 411. In
the case of self-flattening, reactive ion etching (RIE) with
end-point detection (EPD) may be utilized until the upper surface
410 of the etched silicon nitride is reached.
[0054] The structure 411 is then oxidized to form and define
sacrificial layers 304 of SiO2 about 10-20 nm deep into planar
surface 306.
[0055] The unconverted, remaining portions of silicon form traces
104.
[0056] FIG. 5 shows another method that may be used to create the
NTRCM devices 100 of certain embodiments. A support structure 407,
like that described in connection with FIG. 4, is provided. A layer
514 of n-doped silicon is then added using a CVD process,
sputtering or electroplating. Under certain embodiments, layer 514
is added to be about half the height of the Si3N4 supports 102.
[0057] After the layer 514 is added, an annealing step is performed
to yield a planarized surface 306 to form a structure 411 like that
described above. The annealing step causes the silicon of layer 514
to flow into the cavities 406.
[0058] Like that described in connection with FIG. 4, the structure
411 is then oxidized to form and define sacrificial layers 304 of
SiO2 about 10-20 nm deep into planar surface 306.
[0059] FIG. 6 shows another approach for forming an alternative
first intermediate structure 302'. In this embodiment, a silicon
substrate 600 is covered with a layer 602 of silicon nitride having
a height 604 of at least 30 nm.
[0060] The silicon nitride layer 602 is then patterned and etched
to generate spacings 606 and to defined supports 102. The etching
process exposes a portion 608 of the surface of silicon substrate
600.
[0061] The exposed silicon surface 608 is oxidized to generate a
silicon dioxide (SiO2) layer 610 having a thickness of a few nm.
These layers 610 eventually insulate traces 104 analogously to the
way insulating layer 109 did for the above-described structures
302.
[0062] Once the insulating layers 610 have been created, the traces
104 may be created in any of a variety of manner. FIG. 6
illustrates the processing steps of FIGS. 4-5 used to create such
traces to illustrate this point.
[0063] FIG. 7 shows another approach for forming first intermediate
structure 302. A silicon substrate 700 having a silicon dioxide
layer 702 and a silicon nitride layer 704 receives a patterned
photoresist layer 706. For example, a photoresist layer may be
spin-coated on layer 704 and subsequently exposed and
lithographically developed.
[0064] Reactive ion etching (RIE) or the like may then be used to
etch the Si3N4 layer 704 to form cavities 708 and to define
supports 102.
[0065] Afterwards, n-doped silicon 710 may be deposited in the
cavities 708. Under certain embodiments silicon is deposited to a
height about equal to the height 712 of the Si3N4 supports 102.
[0066] The photoresist 706 and silicon 710 on top of the
photoresist 706 are then stripped away to form an intermediate
structure 411 like that described above.
[0067] The structure 411 is then oxidized to generate the
sacrificial SiO2 layers 304.
[0068] FIG. 8 shows another approach for forming first intermediate
structure 302. Under this approach, a starting structure 800 is
provided having a lowest silicon layer 802 with a lowest silicon
dioxide layer 804 on top of it. A second silicon layer 806 is on
top of layer 804 and a second silicon dioxide layer 808 is on top
of the second silicon layer 806.
[0069] The top silicon dioxide (SiO2) layer 808 is patterned by
photolithography to create an RIE mask 810. The mask is used to
etch the exposed portions 812 of second silicon layer 806 down to
the first silicon dioxide layer 804. This etching creates cavities
814 and defines traces 104.
[0070] The cavities 814 are filled and covered with silicon nitride
(Si3N4) 816.
[0071] The Si3N4 covering 816 is backetched with RIE to the same
height 818 as the remaining portions of the SiO2 layer 806 covering
the n-doped silicon electrodes 104 (which form the sacrificial
layer 304).
[0072] FIG. 9 shows an approach for forming an alternative first
intermediate structure 302". Under this approach, a structure like
407 (shown in FIG. 4, but not FIG. 9) is provided. In this
instance, the Si3N4 supports 102 have a height of about 30 nm. A
thin layer of metal 902 is deposited on top of the Si3N4 supports
102 and on top of the exposed portions SiO2 at the bottom of the
cavities 904 as depicted by item 903. Metal 902 and 903 form
temporary electrodes. A layer of n-doped silicon 906 may then be
deposited or grown by electroplating, covering the electrode 903
until the silicon 906 achieves a height 908 at the top of the
support 102 and contacting electrode 902. The growth process may be
controlled by the onset of a current flow between the lower and
upper metal electrodes 902,3.
[0073] The exposed metal electrodes 902 may then be removed by wet
chemical methods or dry chemical methods. This forms an
intermediate structure 411' like the structure 411 described above,
but with a buried electrode 903, as an artifact of the silicon
growing process.
[0074] The structure 411' is then oxidized to form sacrificial
layers 304 at the exposed portions of silicon, as described above.
For example, the layers 304 may be grown to a thickness of about 10
nm.
[0075] FIG. 10 shows another approach for forming first
intermediate structure 302. A silicon substrate 1002 having a layer
of silicon dioxide 1004 on top of it and a second layer 1006 of
silicon (n-doped) on top of layer 1004 is used as a starting
material. A mask layer 1008 is photolithographically patterned on
top of layer 1006.
[0076] Using nitridization techniques, exposed portions 1010 of
n-doped silicon layer 1006 are chemically converted to Si3N4
supports 102. The unconverted portions of layer 1006 form traces
104.
[0077] The mask 1008 is removed forming a structure 411 like that
described above.
[0078] The exposed portions 1012 of silicon surface are then
oxidized to form the SiO2 sacrificial layers 304.
[0079] FIG. 11 shows an approach for forming an alternative first
intermediate structure 302'". Under this approach a silicon
substrate 1102 is layered with a thin film 1104 of Si3N4 as a
starting structure. On top of the silicon nitride layer 1104,
n-doped silicon is added and lithographically patterned, by RIE, to
form traces 104.
[0080] The surfaces of traces 104 are oxidized to form the SiO2
layer 1106 which acts as an alternative form of sacrificial layer
304'.
[0081] The structure is overgrown with Si3N4 1108 and back etched
to form a planar surface 306 and to form alternative first
intermediate structure 302'". As will be evident to those skilled
in the art, under this approach, when the sacrificial layer is
subsequently removed, traces 104 will be separated from supports
102. Other variations of this technique may be employed to create
alternative transverse cross-sections of trace 104. For example,
the traces 104 may be created to have a rounded top, or to have a
triangular or trapezoidal cross section. In addition, the cross
section may have other forms, such as a triangle with tapered
sides.
[0082] As was explained above, once a first intermediate structure
is formed, e.g., 302, a matted nanotube layer 312 is provided over
the planar surface 306 of the structure 302. In preferred
embodiments, the non-woven fabric layer 312 is grown over the
structure through the use of a catalyst 308 and through the control
of a growth environment. Other embodiments may provide the matted
nanotube layer 312 separately and apply it directly over the
structure 302. Though structure 302 under this approach preferably
includes the sacrificial layer to provide a planar surface to
receive the independently grown fabric, the sacrificial layer may
not be necessary under such an approach.
[0083] Because the growth process causes the underside of such
nanotubes to be in contact with planar surface 306 of intermediate
structure 302, they exhibit a "self-assembly" trait as is suggested
by FIG. 12. In particular, individual nanotubes tend to adhere to
the surface on which they are grown whenever energetically
favorable, such that they form substantially as a "monolayer." Some
nanotubes may grow over another so the monolayer is not expected to
be perfect. The individual nanotubes do not "weave" with one
another but do adhere with one another as a consequence of Van der
Waals forces. FIG. 12 is an approximate depiction of an actual
nanotube non-woven fabric. Because of the small feature sizes of
nanotube, even modern scanning electron microscopy cannot
"photograph" an actual fabric without loss of precision; nanotubes
have feature sizes as small as 1-2 nm which is below the precision
of SEM. FIG. 12 for example, suggests the fabric's matted nature;
not clear from the figure, however, is that the fabric may have
small areas of discontinuity with no tubes present. Each tube
typically has a diameter 1-2 nm (thus defining a fabric layer about
1-2 nm) but may have lengths of a few microns but may be as long as
200 microns. The tubes may curve and occasionally cross one
another. Tubes attach to one another via Van der Waals forces.
[0084] In certain embodiments, nanotubes grow substantially
unrestrained in the x- and y-axis directions, but are substantially
restricted in the z-axis (perpendicular to page of FIG. 12) as a
consequence of the self-assembly trait. Other embodiments may
supplement the above approach to growing matte 312 with the use of
field-oriented or flow-oriented growth techniques. Such
supplementation may be used to further tailor growth such that any
growth in one planar axis (e.g. the--x-axis) is retarded. This
allows for a more even coverage of the desired area with a planar
interwoven monolayer coating of nanotubes with a controllable
density.
[0085] A plan view of the matted nanotube layer 312 with underlying
silicon traces 104 is shown in FIG. 13.
[0086] As explained above, once the matted nanotube layer 312 is
provided over the surface 306, the layer 312 is patterned and
etched to define ribbons 101 of nanotube fabric that cross the
supports 102. The sacrificial layer is then removed (e.g., with
acid) forming the array 322 described above in connection with FIG.
3. Because the matted layer of nanotubes 312 form a non-woven
fabric that is not a contiguous film, etchants or other chemicals
may diffuse between the individual nanotube "fibers" and more
easily reach the underlying components, such as the sacrificial
layer.
[0087] Subsequent metalization may be used to form addressing
electrodes, e.g., 112 shown in FIG. 1, as outlined above. Other
embodiments use nanotube technology to implement addressing of
memory cells instead of using metallized electrodes 112 and
addressing lines (not shown).
[0088] More specifically, under certain embodiments described
above, nanotubes are used to form NTRCM arrays. Certain embodiments
use nanotube technology, whether in individual wire or belt form,
to implement addressing logic to select the memory cell(s) for
reading or writing operations. This approach furthers the
integration of nanotube technology into system design and may
provide beneficial functionality to higher-level system design. For
example, under this approach the memory architecture will not only
store memory contents in non-volatile manner but will inherently
store the last memory address.
[0089] The nanotube-based memory cells have bistability
characterized by a high ratio of resistance between "0" and "1"
states. Switching between these states is accomplished by the
application of specific voltages across the nanotube belt or wire
and the underlying trace, in which at least one of the memory cell
elements is a nanotube or a nanotube ribbon. In one approach, a
"readout current" is applied and the voltage across this junction
is determined with a "sense amplifier." Reads are non-destructive,
meaning that the cell retains its state, and no write-back
operations are needed as is done with DRAM.
[0090] FIG. 14 depicts a branching binary select system, or
decoder, 1400. As will be explained below, decoder 1400 may be
implemented with nanotubes or nanotube ribbon technology. Moreover,
the decoder may be constructed on the same circuit component as a
nanotube memory cell array, e.g., NTRCM or NTWCM.
[0091] A perpendicular intersection of two lines 1404 and 1406
depicted as a dot 1402 indicates a junction of two nanotubes or
nanotube ribbons. In this regard, the interaction is analogous to a
"pass transistor" found in CMOS and other technology, in which the
intersection may be opened or closed.
[0092] Locations such as 1420 where one nanotube or nanotube ribbon
may cross another but which are not intended to create a crossbar
junction may be insulated from one another with a lithographically
patterned insulator between the components.
[0093] For the sake of clarity, the decoder illustrated is for a
3-bit binary address carried on addressing lines 1408. Depending on
the value of the encoding the intersections (dots) will be switched
to create only one path through which sensing current I may pass to
select lines 1418.
[0094] To use this technique, a "dual rail" representation 1408 of
each bit of the binary address is fashioned externally so that each
of the address bits 1410 is presented in true and complementary
form. Thus, line 1406 may be the logical true version of address
line 1408a and line 1407 may be the logical complement of address
line 1408a. The voltage values of the representation 1408 are
consistent with that needed to switch a crossbar junction to the
"1" or "0" state as described above.
[0095] In this fashion an address 1408 may be used to supply a
sense current I to a bit or row of bits in an array, e.g., to
nanotubes or nanotube ribbons. Likewise, the same approach may be
used to sense a given trace, for example, selecting specific array
column(s) to read sense from in conjunction with selecting a row.
Thus this approach may be used for X and/or Y decoding both for
reading and for writing operations.
[0096] Certain embodiments of the invention provide a hybrid
technology circuit 1500, shown in FIG. 15. A core memory cell array
1502 is constructed using NTWCM or NTRCM, and that core is
surrounded by semiconductor circuits forming X and Y address
decoders 1504 and 1506; X and Y buffers 1508 and 1510; control
logic 1512 and output buffers 1514. The circuitry surrounding the
NTWCM or NWBCM core may be used for conventional interfacing
functions, including providing read currents and sensing output
voltages.
[0097] In other embodiments, the X and Y address decoders 1504 and
1506 may be substituted with the nanotube wire or belt addressing
technique discussed above. In these embodiments the core would
include memory cells and addressing logic.
[0098] In certain embodiments, the hybrid circuit 1500 may be
formed by using a nanotube core (having either just memory cells or
memory cells and addressing logic) and by implementing the
surrounding circuitry using a field programmable gate array. The
core and gate array circuitry may be contained in a single physical
package if desired. Or, they may be packaged separately. For
example, a hermitically packaged nanotube circuit (having memory or
memory and addressing logic) may be combined with a PLD/FPGA/ASIC
in which the I/O interfacing logic is contained. The resulting
compact chipset provides access to the benefits of the NT memory
for the user of the product, while maximizing the use of
"off-the-shelf" technologies, which may be utilized on an as-needed
basis by the manufacturer.
[0099] FIG. 16 depicts one possible implementation 1600 of the
hybrid technology. A FPGA chip 1602 containing the buffering and
control logic (described above) is connected via conducting traces
on a (perhaps multilayer) printed circuit board (PCB) 1604 to a
nanotube (NT) chip 1606 containing the memory cells and addressing
logic.
[0100] This particular embodiment is suggested to conform to the
PCI bus standard, typical of today's personal computers. Other
passive circuitry, such as capacitors, resistors, transformers,
etc. (not pictured) would also be necessary to conform to the PCI
standard. A front-side bus speed of 200 MHz-400 MHz is annotated,
suggesting the kinds of external clock speeds such a chipset might
run at. This speed is limited by the PCB interconnects and
FPGA/PLD/ASIC speed, and also the chip packages, not the NT memory
cell speed.
[0101] Carbon Nanotube Films, Layers, Fabrics, and Articles
[0102] The above embodiments of NTRCM and addressing lines use
traces or electrically conductive articles made from nanotube
layers 312, such as those shown in FIGS. 3 and 12. The layers may
have thickness of about 1 nm or less, i.e., the thickness of a
given nanotube. The nanotube matte 312 is grown or deposited on a
surface, such as that of a silicon wafer, to form a contiguous film
of a given density. The two dimensional film can then be patterned
to generate electrically conductive lines or traces ranging in
width from 1 nm (the intrinsic minimum size of a nanotube) to
hundreds of microns or greater, depending on the application and
context. The pattern can be generated at multiple length and width
scales to allow the interconnection of various sized semiconductor
devices such as transistors or memory elements and eventually
fanning out to bond pads or other interconnecting materials or
constructs. The nanotube interconnects can be metallized if
necessary to connect different materials because of their intrinsic
properties that allow easy contact to metallic or semiconductor
materials.
[0103] The traces and electrically conductive articles may be used
in other forms of circuits. For example, nanotube traces may be
used for their ability to withstand high current densities,
normally found in very small sized traces (e.g., sub 10 nm
regimes). They may also be used to reduce the likelihood of
contaminating other circuit features.
[0104] FIG. 17, for example, illustrates an exemplary use of
nanotube ribbons, traces, or electrically conductive articles over
a substrate. (By inspection, one can see that FIG. 17 resembles
FIG. 3, but in this instance the film 312 is grown over a
substrate, instead of growing it over an intermediate structure
310.) In this example, a silicon substrate 110 has an oxide layer
109, similar to that shown in FIG. 3. To facilitate growth or
deposition of the film 312, a planar surface (shown as 306 in FIG.
3, but not shown in FIG. 17) may be generated. A film 312 with
single- and/or multi-walled nanotubes may then be grown over the
combination, e.g., using CVD, or deposited on the combination,
e.g., via spin coating. The film 312 is primarily one nanotube
thick if single-walled nanotubes are used but can be substantially
thicker if multi-walled nanotubes are used, e.g., up to 1000
nm.
[0105] If the film is to be grown, a catalyst may be used, as
described above. However, the catalyst (shown as 308 in FIG. 3, but
not shown in FIG. 17) does not need to be deposited directly on the
surface of the substrate; instead or in addition, it may be
provided in a gaseous form as part of the CVD process. For example,
a gas phase metallic species such as ferrocene could be used.
Ferrocene and other gas phase metallic species grow carbon
nanotubes as do other species containing iron, molybdenum,
tungsten, cobalt and other transition metals. These are all
suitable for forming catalysts in the gas phase. The metallic
gas-phase catalyst can be optimized or modified along with the
proper temperature, pressure, surface preparation and growth time
to generate a nanotube matte 312.
[0106] If the film 312 is to be deposited, pre-grown nanotubes may
be used. For example, under certain embodiments of the invention,
nanotubes may be suspended in a solvent in a soluble or insoluble
form and spin-coated over the surface to generate the nanotube film
312. In such an arrangement the film may be one or more nanotubes
thick, depending on the spin profile and other process parameters.
Appropriate solvents include dimethylformamide,
n-methylpyrollidinone, n-methyl formamide, orthodichlorobenzene,
paradichlorobenzene, 1,2, dichloroethane, alcohols, water with
appropriate surfactants such as sodium dodecylsulfate or TRITON
X-100 or others. The nanotube concentration and deposition
parameters such as surface functionalization, spin-coating speed,
temperature, pH and time can be adjusted for controlled deposition
of monolayers or multilayers of nanotubes as required.
[0107] The nanotube film 312 could also be deposited by dipping the
wafer or substrate in a solution of soluble or suspended nanotubes.
The film could also be formed by spraying the nanotubes in the form
of an aerosol onto a surface.
[0108] When conditions of catalyst composition and density, growth
environment, and time are properly controlled, nanotubes can be
made to evenly distribute over a given field that is primarily a
monolayer of nanotubes.
[0109] Upon formation of the nanotube matte 312, a photoresist
layer may be spin-coated on the nanotube film 312 and patterned by
exposure or the like to define conductive traces. In the example of
FIG. 17, the traces are shown as parallel straight traces, but the
trace definition may take other forms. The defined traces can have
a width of at least 1 nm and as much as 100 microns or more
depending upon the type of device which is to be
interconnected.
[0110] Once so defined, the exposed photoresist may be processed to
remove some of the layer but to leave the traces 101. Subsequent
metallization may be used to form addressing electrodes or a fanned
interconnect structure, e.g., 1706 shown in FIG. 17.
[0111] With reference to FIG. 18, nanotube ribbon patterns 1802 may
then be connected to other ribbons 101, metallic traces (not shown)
or electronic features 1806. For example, with reference to
intermediate structure 1800, the nanotube traces 101 may be
connected to nanotube traces 1802 having different feature sizes,
such as width. The traces 101 may also be connected to elements
112, which may be metal contacts or bonding pads (though not shown
to scale in this figure). With reference to intermediate structure
1804, the traces 1010 may connect to memory elements such as in
1804, which may be formed as NTRCM cells or with semiconductor
sites. With reference to intermediate structure 1808, the traces
may connect electronic processing sites or logic 1806. Though not
necessarily drawn to scale, the traces 101 may also connect bond
pads, represented by item 112.
[0112] While these interconnects may primarily be formed of a
monolayer of nanotubes, multilayer ribbons and mattes can also be
envisioned using proper growth conditions. This requires control of
parameters including but not limited to catalyst composition and
concentration, functionalization of the underlying surface, spin
coating parameters (length and RPM, for example 40 seconds, 50-5000
rpm), growth time, temperature and gas concentrations.
[0113] One aspect of the above technique is that the various
growth, deposition, patterning, and etching operations may use
conventional techniques, such as lithographic patterning. With
current technology, traces may be made to have widths of about 180
nm to as low as 130 nm. However, the physical characteristics of
the traces 101 are amenable to even smaller feature sizes if
manufacturing capabilities permit.
[0114] Conventional interconnect technologies have a tendency to
suffer from thermal damage and metal diffusion eroding the
performance of the semiconductor devices especially from
degradation of the electrical properties. These effects become even
more pronounced with size reduction in current generation 0.18 um
and 0.13 um structures, e.g. by metal diffusion through ultra-thin
gate oxide layers. In contrast, carbon nanotube ribbons 101 are not
beset with these problems. They are substantially more robust
having the highest known thermal conductivities and are not prone
to thermal failure. Furthermore, no metal or dopant diffusion can
occur since they are constructed entirely of covalently bound
carbon atoms.
[0115] FIG. 19 shows another approach for forming first
intermediate structure 302. A silicon substrate 1900 having a
silicon dioxide layer 1902 receives a patterned photoresist layer
1904. For example, a photoresist layer may be spin-coated on layer
1902 and subsequently exposed and lithographically developed
yielding cavities 1906 and a mask pattern 1908.
[0116] Afterwards, n-doped silicon or metal such as molybdenum,
tungsten or tantalum 1910 and a sacrificial layer 1912 such as
aluminum oxide may be deposited in the cavities 1906, also forming
corresponding features 1914 and 1916.
[0117] The photoresist 1912, material 1914 and aluminum oxide
(Al2O3) 1916 on top of the photoresist 1912 are then stripped away
to form an intermediate structure 1918 with electrodes 104 and
sacrificial layer 304. A spin-on-glass (SOG) such as flowable oxide
(FOX) is spin-coated over the structure 1918 and annealed using a
ramped temperature protocol at 600.degree. C. using standard
techniques forming a SiO2 layer 1920 at a height of from 200-2000
nm above the top of the sacrificial layer 1912.
[0118] Reactive ion etching (RIE) or the like may then be used to
etch the SiO2 layer 1920 to form a structure 302 with supports
102.
[0119] The choice of electrode material is limited by the method by
which the nanotubes are placed upon the substrate surface. The
three above methods include spin-coated catalyst-based growth,
gas-phase catalyst-assisted CVD and spin-coating or direct
deposition of nanotubes. In the case of the catalyst-based growth
as has been described above the catalyst is distributed on the
surface either by spin-coating, or dipping the substrate in the
catalyst material followed by standard washing protocols. In each
of these cases the nanotubes are then grown via a CVD process at
800.degree. C. using a combination of hydrogen and
carbon-containing precursor gas as has been described above. Thus,
electrode materials which are sufficiently robust to survive these
temperatures would be preferred including molybdenum, tungsten,
tantalum, germanium, copper and alloys thereof. The electrode
material can be constructed of a single or stacked structure of
materials including silicon, tungsten, molybdenum, tantalum, copper
and others. The stacked electrode structure may assist with or be
sufficient in creating a Schottky barrier sufficient for
rectification of each memory bit.
[0120] In the event that the nanotubes are grown using a gas-phase
catalyst such as ferrocene, it is possible to envision
substantially lower temperatures being required for growth allowing
the use of electrode materials that melt at a substantially lower
temperature less than 800.degree. C. and as low as 400.degree. C.
Some gas-phase catalysts of interest may include cobalt, tungsten,
molybdenum or rhenium metallocenes containing five of six-membered
rings. These compounds can with the proper knowledge of inorganic
chemistry be synthesized and brought by the use of a bubbler into
the gas-phase to act as nucleation sites on substrates for nanotube
growth. Of course these materials would be substantively compatible
with the typical CMOS processes known in the literature and used by
standard industrial fabrication facilities.
[0121] In the event that nanotubes are deposited on a surface at
room temperature by spin-coating of a solution or suspension of
nanotubes then the choice of electrode materials is expanded
substantially. In this case there is no high temperature step and
any metal typically compatible with standard CMOS metallization
conditions would be acceptable especially, aluminum, and alloys
thereof.
[0122] The sacrificial layer 304 can be constructed of Al2O3, metal
oxides, salts, metals and other materials. The intermediate
structure 302 can be formed using a variety of materials to form
the supports 102 including SOG, SiO2 and others. In the event that
a low temperature spin-coating of nanotube protocol is chosen the
materials suitable to be sacrificial layers expands substantially.
This could include materials such as PMMA or other polymers, metals
such tungsten, chromium, aluminum, bismuth and other transition and
main group metals. Also other semiconductors such as germanium and
insulators such as salts, oxides and other chalcogenides.
[0123] The choice of materials for the support layer greatly
depends upon the method chosen for nanotube growth and other
factors. In the even that a low-temperature process is chosen for
placing nanotubes on the surface, one can envision utilizing such
materials as Al2O3, silicon monoxide, semiconductors, insulators
and polymers such as polyimide.
[0124] The materials selection process is confined to those
materials that are compatible with the fabrication process
described above. It is understood by those sufficiently skilled in
the art that upon selection of a particular electrode material, the
sacrificial layer and support materials naturally become limited
based upon typical processing steps available in semiconductor
fabrication. Likewise if a particular sacrificial layer is chosen
the choices of electrode and sacrificial layer materials is
suitably limited. Furthermore, upon selection of a particular
support material it follows that the electrode and sacrificial
layer materials choice is likewise limited.
[0125] FIG. 20 shows an Atomic Force Microscopic (AFM) image of an
exemplary nanotube fabric 312. In this figure, each nanotube is
about 1.5 nm in diameter. (The image is fuzzy due to the inherent
limitations in the microscopy, not due to the actual texture of a
given nanotube.) This image is at the lateral resolution limit of
AFM.
[0126] Though most of the disclosure above is written as if the
fabric were made of nanotubes of the same type, e.g., all single
walled, the fabrics may be composed of all multi-walled structures
or of a combination of single- and multi-walled structures.
Other Embodiments
[0127] In order to facilitate the growth of interconnects or
electrode materials it may become useful to first form a pattern
using standard lithographic methods to define regions where the
nanotubes are intended to grow in a horizontal fashion over the
surface. Such an approach has been used to pattern SiO2 structures
to grow thick multiwalled vertical nanotubes. In a similar approach
patterned SiO2 can be used for the purpose of growing horizontal
nanotube films with a thickness of 1-1000 nm to create structures
of the form described above such as 101. Other materials which
provide a support for nanotube growth and nucleation such as
insulators and metal oxides may be useful when used in concert with
properly chosen gas-phase metallocenes or other vaporizable
metallic precursors to yield patterned nanotube ribbons. This
underlying patterned layer could also act as a sacrificial layer
which upon removal would form a suspended nanotubes. This method of
growth represents a form of "positive" growth whereby the nanotubes
use the prepatterned surface as a nucleation site.
[0128] In a further embodiment one can envision using a "negative"
growth method whereby the lithographically patterned substrate
contains a metallic or other material which does not support
nanotube growth. When a proper gas-phase precursor such as a
metallocene or similar compound is supplied the nanotubes would
substantively grow only in the regions without the patterned
material. The removal of an underlying material could provide
suspended nanotubes 101 or interconnect structures upon the removal
of the patterned metallic species.
[0129] In yet another embodiment, instead of using wet-chemical
removal of sacrificial layer to suspend nanotubes at specific
height over electrodes, a controlled etch of the electrode (i.e. 15
nm etch of 0.18 um wide electrode) can be used; e.g. metal (e.g.
copper) and semiconductor (e.g. silicon) electrodes can be etched
at etch rates of a few nanometer per second.
[0130] In another embodiment pinning of nanotubes onto the supports
using an overlayed thin coating to prevent slipping of tubes during
operation. This would open "windows" just over the memory cell
itself.
[0131] The electrical properties of the layers and electrically
conductive articles can be tuned by controlling the cross section
of the nanotube ribbons. For example, the ribbon thickness may be
increased at a given width and nanotube density. The higher the
cross section, the greater the number of conduction channels
leading to enhanced electrical properties.
[0132] The method of preparing of the nanotube ribbons allows
continuous conductivity even over rough surface topologies. In
contrast, typical evaporation of metallic electrodes would suffer
from structural and thus, electrical defects.
[0133] Besides carbon nanotubes other materials with electronic and
mechanical properties suitable for electromechanical switching
could be envisioned. These materials would have properties similar
to carbon nanotubes but with different and likely reduced tensile
strength. The tensile strain and adhesion energies of the material
must fall within a range to allow bistability of the junction and
electromechanical switching properties to exist within acceptable
tolerances.
[0134] For the purpose of integrating CMOS logic for addressing two
approaches can be envisioned. In the first embodiment the nanotube
array will be integrated before metallization but after ion
implantation and planarization of the CMOS logic devices. A second
method involves growth of the nanotube arrays before fabrication of
the CMOS devices involving ion implementation and high temperature
annealing steps. Upon completion of these steps the final
metallization of both the nanotube ribbons and the CMOS devices
will proceed using standard and widely used protocols.
[0135] Electrodes consisting of n-doped silicon on top of some
metal or semiconductor line can also be envisioned. This will still
provide rectifying junctions in the ON state so that no multiple
current pathways exist.
[0136] In addition to rectifying junctions, there are other widely
accepted and used methods to prevent the occurrence of electrical
crosstalk (i.e. multiple current pathways) in crossbar arrays.
Tunnel barriers on top of the static, lithographically fabricated
electrodes prevent the formation of ohmic ON states. No leakage
currents at zero bias voltage will occur but a small bias voltage
has to be applied for the charge carriers to overcome this barrier
and tunnel between the crossing lines.
[0137] Methods to increase the adhesion energies through the use of
ionic, covalent or other forces can be envisioned to alter the
interactions with the electrode surfaces. These methods can be used
to extend the range of bistability with these junctions.
[0138] Nanotubes can be functionalized with planar conjugated
hydrocarbons such as pyrenes which may then aid in enhancing the
internal adhesion between nanotubes within the ribbons.
[0139] Certain of the above aspects, such as the hybrid circuits
and the nanotube technology for addressing, are applicable to
individual nanotubes (e.g., using directed growth techniques, etc.)
or to nanotube ribbons.
[0140] It will be further appreciated that the scope of the present
invention is not limited to the above-described embodiments but
rather is defined by the appended claims, and that these claims
will encompass modifications of and improvements to what has been
described.
* * * * *