U.S. patent application number 11/061224 was filed with the patent office on 2005-08-25 for comparator and ad conversion circuit having hysteresis circuit.
Invention is credited to Kawamura, Yasunori, Yuki, Hirofumi.
Application Number | 20050184762 11/061224 |
Document ID | / |
Family ID | 34863507 |
Filed Date | 2005-08-25 |
United States Patent
Application |
20050184762 |
Kind Code |
A1 |
Yuki, Hirofumi ; et
al. |
August 25, 2005 |
Comparator and AD conversion circuit having hysteresis circuit
Abstract
A comparator is provided, which compares an input voltage and a
reference voltage by using a plurality of inverting circuits
connected in series. The comparator includes a first inverting
circuit, a second inverting circuit, a feedback path, and a
capacitor arranged on the feedback path. The first inverting
circuit inverts a difference between the input voltage and the
reference voltage for output. The second inverting circuit further
inverts the output of the first inverting circuit for output. The
feedback path feeds back the output of the second inverting circuit
to the input side of the first inverting circuit. The capacitor
causes hysteresis such that an increasing threshold and a
decreasing threshold of the second inverting circuit corresponding
to an increase and a decrease of the input voltage have a
difference therebetween.
Inventors: |
Yuki, Hirofumi; (Ukyo-Ku,
JP) ; Kawamura, Yasunori; (Ukyo-Ku, JP) |
Correspondence
Address: |
CANTOR COLBURN, LLP
55 GRIFFIN ROAD SOUTH
BLOOMFIELD
CT
06002
|
Family ID: |
34863507 |
Appl. No.: |
11/061224 |
Filed: |
February 18, 2005 |
Current U.S.
Class: |
327/77 |
Current CPC
Class: |
H03K 5/2481 20130101;
H03M 1/0845 20130101; H03K 5/249 20130101; H03M 1/365 20130101 |
Class at
Publication: |
327/077 |
International
Class: |
H03K 005/153 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 20, 2004 |
JP |
JP2004-044913 |
Jan 24, 2005 |
JP |
JP2005-015642 |
Claims
What is claimed is:
1. A comparator which compares an input voltage and a reference
voltage by using a plurality of inverting circuits connected in
series, the comparator comprising: a first inverting circuit which
inverts and outputs a difference between the input voltage and the
reference voltage; a second inverting circuit which further inverts
and outputs the output of the first inverting circuit; a feedback
path which feeds back the output of the second inverting circuit to
the input side of the first inverting circuit; and a capacitor
which is arranged on the feedback path and causes hysteresis such
that an increasing threshold and a decreasing threshold of the
second inverting circuit corresponding to an increase and a
decrease of the input voltage have a difference therebetween.
2. The comparator according to claim 1, further comprising a
circuit which is arranged on the feedback path and switches on or
off the application of the output of the second inverting circuit
to the capacitor.
3. The comparator according to claim 1, wherein the capacitor
functions to increase the value of the difference between the input
voltage and the reference voltage slightly when the output of the
second inverting circuit changes from low level to high level.
4. The comparator according to claim 2, wherein the capacitor
functions to increase the value of the difference between the input
voltage and the reference voltage slightly when the output of the
second inverting circuit changes from low level to high level.
5. The comparator according to claim 1, further comprising: a first
switch which switches on and off the input of the input voltage to
the first inverting circuit; a second switch which switches on and
off the input of the reference voltage to the first inverting
circuit; and a third switch arranged on a path which feeds back the
output of the first inverting circuit to the input side of the
first inverting circuit, the third switch switching on and off the
feedback, and wherein the output of the first inverting circuit
settles down at an intermediate value in its voltage range when the
first switch is off and the second and third switches are on, and
takes the value of the difference between the input voltage and the
reference voltage when the second and third switches are off and
the first switch is on, and the capacitor increases the value of
the difference slightly while the input voltage is on the increase
when the second and third switches are off and the first switch is
on.
6. The comparator according to claim 2, further comprising: a first
switch which switches on and off the input of the input voltage to
the first inverting circuit; a second switch which switches on and
off the input of the reference voltage to the first inverting
circuit; and a third switch arranged on a path which feeds back the
output of the first inverting circuit to the input side of the
first inverting circuit, the third switch switching on and off the
feedback, and wherein the output of the first inverting circuit
settles down at an intermediate value in its voltage range when the
first switch is off and the second and third switches are on, and
takes the value of the difference between the input voltage and the
reference voltage when the second and third switches are off and
the first switch is on, and the capacitor increases the value of
the difference slightly while the input voltage is on the increase
when the second and third switches are off and the first switch is
on.
7. The comparator according to claim 3, further comprising: a first
switch which switches on and off the input of the input voltage to
the first inverting circuit; a second switch which switches on and
off the input of the reference voltage to the first inverting
circuit; and a third switch arranged on a path which feeds back the
output of the first inverting circuit to the input side of the
first inverting circuit, the third switch switching on and off the
feedback, and wherein the output of the first inverting circuit
settles down at an intermediate value in its voltage range when the
first switch is off and the second and third switches are on, and
takes the value of the difference between the input voltage and the
reference voltage when the second and third switches are off and
the first switch is on, and the capacitor increases the value of
the difference slightly while the input voltage is on the increase
when the second and third switches are off and the first switch is
on.
8. The comparator according to claim 4, further comprising: a first
switch which switches on and off the input of the input voltage to
the first inverting circuit; a second switch which switches on and
off the input of the reference voltage to the first inverting
circuit; and a third switch arranged on a path which feeds back the
output of the first inverting circuit to the input side of the
first inverting circuit, the third switch switching on and off the
feedback, and wherein the output of the first inverting circuit
settles down at an intermediate value in its voltage range when the
first switch is off and the second and third switches are on, and
takes the value of the difference between the input voltage and the
reference voltage when the second and third switches are off and
the first switch is on, and the capacitor increases the value of
the difference slightly while the input voltage is on the increase
when the second and third switches are off and the first switch is
on.
9. An AD conversion circuit which converts an analog signal into a
digital signal by using a plurality of comparators, the comparators
each comparing an input voltage and a reference voltage by using a
plurality of inverting circuits connected in series, wherein the
plurality of comparators each comprise: a first inverting circuit
which inverts and outputs a difference between the input voltage
and the reference voltage; a second inverting circuit which further
inverts and outputs the output of the first inverting circuit; a
feedback path which feeds back the output of the second inverting
circuit to the input side of the first inverting circuit; and a
capacitor which is arranged on the feedback channel and causes
hysteresis such that an increasing threshold and a decreasing
threshold of the second inverting circuit corresponding to an
increase and a decrease of the input voltage have a difference
therebetween.
10. The AD conversion circuit according to claim 9, further
comprising a circuit arranged on the feedback path, the circuit
switching on and off the application of the output of the second
inverting circuit to the capacitor.
11. The AD conversion circuit according to claim 9, wherein the
capacitor functions to increase the value of the difference between
the input voltage and the reference voltage slightly when the
output of the second inverting circuit changes from low level to
high level.
12. The AD conversion circuit according to claim 10, wherein the
capacitor functions to increase the value of the difference between
the input voltage and the reference voltage slightly when the
output of the second inverting circuit changes from low level to
high level.
13. The comparator according to claim 9, further comprising: a
first switch which switches on and off the input of the input
voltage to the first inverting circuit; a second switch which
switches on and off the input of the reference voltage to the first
inverting circuit; and a third switch arranged on a path which
feeds back the output of the first inverting circuit to the input
side of the first inverting circuit, the third switch switching on
and off the feedback, and wherein the output of the first inverting
circuit settles down at an intermediate value in its voltage range
when the first switch is off and the second and third switches are
on, and takes the value of the difference between the input voltage
and the reference voltage when the second and third switches are
off and the first switch is on, and the capacitor increases the
value of the difference slightly while the input voltage is on the
increase when the second and third switches are off and the first
switch is on.
14. The comparator according to claim 10, further comprising: a
first switch which switches on and off the input of the input
voltage to the first inverting circuit; a second switch which
switches on and off the input of the reference voltage to the first
inverting circuit; and a third switch arranged on a path which
feeds back the output of the first inverting circuit to the input
side of the first inverting circuit, the third switch switching on
and off the feedback, and wherein the output of the first inverting
circuit settles down at an intermediate value in its voltage range
when the first switch is off and the second and third switches are
on, and takes the value of the difference between the input voltage
and the reference voltage when the second and third switches are
off and the first switch is on, and the capacitor increases the
value of the difference slightly while the input voltage is on the
increase when the second and third switches are off and the first
switch is on.
15. The comparator according to claim 11, further comprising: a
first switch which switches on and off the input of the input
voltage to the first inverting circuit; a second switch which
switches on and off the input of the reference voltage to the first
inverting circuit; and a third switch arranged on a path which
feeds back the output of the first inverting circuit to the input
side of the first inverting circuit, the third switch switching on
and off the feedback, and wherein the output of the first inverting
circuit settles down at an intermediate value in its voltage range
when the first switch is off and the second and third switches are
on, and takes the value of the difference between the input voltage
and the reference voltage when the second and third switches are
off and the first switch is on, and the capacitor increases the
value of the difference slightly while the input voltage is on the
increase when the second and third switches are off and the first
switch is on.
16. The comparator according to claim 12, further comprising: a
first switch which switches on and off the input of the input
voltage to the first inverting circuit; a second switch which
switches on and off the input of the reference voltage to the first
inverting circuit; and a third switch arranged on a path which
feeds back the output of the first inverting circuit to the input
side of the first inverting circuit, the third switch switching on
and off the feedback, and wherein the output of the first inverting
circuit settles down at an intermediate value in its voltage range
when the first switch is off and the second and third switches are
on, and takes the value of the difference between the input voltage
and the reference voltage when the second and third switches are
off and the first switch is on, and the capacitor increases the
value of the difference slightly while the input voltage is on the
increase when the second and third switches are off and the first
switch is on.
17. A semiconductor device incorporating the comparator according
to claim 1.
18. A semiconductor device incorporating the AD conversion circuit
according to claim 9.
19. An image capturing apparatus comprising an AD conversion
circuit which converts an analog signal into a digital signal by
using a plurality of comparators, the comparators each comparing an
input voltage and a reference voltage by using a plurality of
inverting circuits connected in series, and wherein the plurality
of comparators of the AD conversion circuit each comprise: a first
inverting circuit which inverts and outputs a difference between
the input voltage and the reference voltage; a second inverting
circuit which further inverts and outputs the output of the first
inverting circuit; a feedback path which feeds back the output of
the second inverting circuit to the input side of the first
inverting circuit; and a capacitor which is arranged on the
feedback channel and causes hysteresis such that an increasing
threshold and a decreasing threshold of the second inverting
circuit corresponding to an increase and a decrease of the input
voltage have a difference therebetween.
20. An image capturing apparatus comprising: a lens which forms an
image of a subject; a CCD which acquires the image of the subject
through the lens optically and converts the same into an electric
signal; an AD conversion circuit which converts an analog electric
signal received from the CCD into a digital value; an image
processing unit which corrects a digital value received from the AD
conversion circuit, and generates a digital image; a display unit
which displays the digital image on-screen; and a recording unit
which records the digital image, and wherein the AD conversion
circuit converts the analog signal into a digital signal by using a
plurality of comparators, the comparators each comparing an input
voltage and a reference voltage by using a plurality of inverting
circuits connected in series, and the plurality of comparators each
comprise a first inverting circuit which invert and outputs a
difference between the input voltage and the reference voltage, a
second inverting circuit which further inverts and outputs the
output of the first inverting circuit, a feedback path which feeds
back the output of the second inverting circuit to the input side
of the first inverting circuit, and a capacitor which is arranged
on the feedback channel and causes hysteresis such that an
increasing threshold and a decreasing threshold of the second
inverting circuit corresponding to an increase and a decrease of
the input voltage have a difference therebetween.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a comparator, an AD
conversion circuit, a semiconductor device, and an image capturing
apparatus. In particular, the invention relates to the technology
of a hysteresis circuit to be formed in a comparator and an AD
conversion circuit.
[0003] 2. Description of the Related Art
[0004] Conventionally, some comparators for use in multi-bit AD
conversion circuits have incorporated a hysteresis circuit for
reducing noise effect for the sake of improved operation stability
(for example, see Japanese Patent Laid-Open Publication No. Hei
5-167400). The reason is that in multi-bit AD conversion circuits
beyond 10 bits in particular, the increasing number of bits makes
bit-by-bit voltage steps smaller and thus increases the possibility
of noise-induced malfunctions. The conventional hysteresis circuit
switches its reference voltage to a voltage value higher than a
threshold when its input voltage increases and switches the
reference voltage to a voltage value lower than the threshold when
the input voltage decreases. Thus, even if the input voltage
fluctuates in value near the threshold, the output will not
alternate between high level and low level. As a result, stable
output is obtained.
[0005] Nevertheless, there has been the disadvantage that the
conventional multi-bit AD conversion circuits have a plurality of
switches, such as transistors, for realizing the hysteresis
circuit, with an increase in circuit scale accordingly. There has
also been the possibility that the increased number of switches can
complicate the design and control.
SUMMARY OF THE INVENTION
[0006] In view of the foregoing, the inventor has achieved the
present invention. It is thus an object of the invention to realize
a hysteresis circuit of simple configuration and achieve a
comparator of higher stability.
[0007] To solve the foregoing problems, a comparator according to
one of the aspects of the present invention compares an input
voltage and a reference voltage by using a plurality of inverting
circuits connected in series. The comparator comprises: a first
inverting circuit which inverts and outputs a difference between
the input voltage and the reference voltage; a second inverting
circuit which further inverts and outputs the output of the first
inverting circuit; a feedback path which feeds back the output of
the second inverting circuit to the input side of the first
inverting circuit; and a capacitor which is arranged on the
feedback path, and causes hysteresis such that an increasing
threshold and a decreasing threshold of the second inverting
circuit corresponding to an increase and a decrease of the input
voltage have a difference therebetween.
[0008] Here, the "increasing threshold" refers to a threshold
voltage at which the output of the second inverting circuit starts
to increase with the increasing input voltage. The "decreasing
threshold" refers to a threshold voltage at which the output of the
second inverting circuit starts to decrease with the decreasing
input voltage. According to this aspect, it is possible to increase
the difference between the input voltage and the reference voltage
slightly by push-up through the capacitor which functions as a
hysteresis circuit. This can reduce noise effect since the output
voltage will not vary even when the input voltage makes small
fluctuations near the thresholds. Moreover, since all that is
required is to provide the capacitor, it is possible to achieve an
easy-to-control hysteresis circuit with the simple
configuration.
[0009] Another aspect of the present invention is an AD conversion
circuit. This AD conversion circuit converts an analog signal into
a digital signal by using a plurality of comparators, the
comparators each comparing an input voltage and a reference voltage
by using a plurality of inverting circuits connected in series. The
plurality of comparators each comprise: a first inverting circuit
which inverts and outputs a difference between the input voltage
and the reference voltage; a second inverting circuit which further
inverts and outputs the output of the first inverting circuit; a
feedback path which feeds back the output of the second inverting
circuit to the input side of the first inverting circuit; and a
capacitor which is arranged on the feedback path and causes
hysteresis such that an increasing threshold and a decreasing
threshold of the second inverting circuit corresponding to an
increase and a decrease of the input voltage have a difference
therebetween.
[0010] According to this aspect, this AD conversion circuit can
increase the difference between the input voltage and the reference
voltage slightly by push-up through the capacitor which functions
as a hysteresis circuit. Since the output voltage will not vary
even when the input voltage makes small fluctuations near the
thresholds, it is possible to reduce noise effect for higher AD
conversion accuracy. Moreover, since all that is required is to
provide the capacitor, it is possible to achieve an easy-to-control
hysteresis circuit with the simple configuration.
[0011] This AD conversion circuit having the comparators may be
implemented on CCDs, or CCD-based image capturing apparatuses and
scanners. The AD conversion circuit may also be implemented on a
DVD drive.
[0012] Incidentally, any combinations of the foregoing components,
and the components and expressions of the present invention
replaced with methods, apparatuses, circuits, and the like mutually
are also intended to constitute applicable aspects of the present
invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a diagram showing the basic configuration of an
image capturing apparatus;
[0014] FIG. 2 is a diagram showing the configuration of an AD
conversion circuit according to a first embodiment;
[0015] FIG. 3 is a circuit diagram theoretically showing the
configuration of comparators included in the AD conversion
circuit;
[0016] FIG. 4 is a timing chart showing initialization operations
and comparison operations;
[0017] FIG. 5 is a graph showing the hysteresis occurring between
the input voltage and the output voltage;
[0018] FIG. 6 is a diagram showing the configuration of a
comparator according to a second embodiment;
[0019] FIG. 7 is a diagram showing the configuration of an AD
conversion circuit according to a third embodiment; and
[0020] FIG. 8 is a diagram showing the detailed configuration of a
first stage.
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment
[0021] Conventional hysteresis circuits were achieved by switching
the reference voltages to be input to their comparators. That is,
it was necessary to provide at least two possible reference voltage
signals, and a plurality of switches for switching the same. Those
switches were analog switches, and thus had to be reduced in
impedance as much as possible. For example, for AD conversion on a
voltage value of 1 V.sub.pp in 10 bits of resolution, 1 LSB was
0.98 mV. For AD conversion in 12 bits of resolution, 1 LSB=0.24 mV.
Consequently, the greater the number of bits was, the smaller the
bit-by-bit steps became in width. This facilitated noise-induced
errors accordingly, with a drop in the conversion accuracy of the
lower bits.
[0022] In the present embodiment, a hysteresis circuit is achieved
by the configuration of applying pulses to an input stage of a
chopper type comparator. As a result, small hysteresis can be
realized by the simple configuration without providing a plurality
of switches as a hysteresis circuit. In particular, since the
hysteresis circuit can be turned on and off by a logic circuit, it
is possible to suppress the circuit area small. In addition,
smaller hysteresis can be achieved easily by trimming
capacitances.
[0023] In the present embodiment, description will be given with an
image capturing apparatus having the hysteresis circuit and the
comparator as an example.
[0024] FIG. 1 shows the basic configuration of the image capturing
apparatus. The image capturing apparatus 100 comprises a lens 102,
a CCD 104, an AD conversion circuit 10, an image processing unit
106, a display unit 108, and a recording unit 110. The CCD 104
acquires the image of a subject through the lens 102 optically, and
converts it into an electric signal. The AD conversion circuit 10
converts the analog electric signal received from the CCD 104 into
digital values. The image processing unit 106 corrects the digital
values received from the AD conversion circuit 10, and generates a
digital image. The display unit 108 displays the captured digital
image on-screen. The recording unit 110 records the captured
digital image onto a memory card 112 which is loaded from
exterior.
[0025] FIG. 2 shows the configuration of the AD conversion circuit
according to the first embodiment. This AD conversion circuit 10 is
a flash type (parallel comparison type) AD conversion circuit. For
example, when the circuit is intended for AD conversion in n bits
of resolution, 2.sup.n-1 (hereinafter, referred to as m)
comparators, or a first to mth comparators A.sub.1 to A.sub.m, are
connected in parallel between the input path of an input voltage
V.sub.in and that of a reference voltage V.sub.ref. The voltage
between the reference voltage V.sub.ref and a ground potential is
divided by (m-1) resistors R.sub.1 to R.sub.(m-1). The divided
voltages are input to the comparators A.sub.1 to A.sub.m as
respective reference voltages in descending order of the
potentials. The differences between these reference voltages and
the input voltage V.sub.in are output from the first to mth
comparators A.sub.1 to A.sub.m as the results of comparison,
respectively. An encoder 12 converts the results of comparison
output from the respective first to mth comparators A.sub.1 to
A.sub.m into an n-bit digital signal for output. The AD conversion
circuit 10 thus determines which comparator has the reference
voltage coinciding with the input voltage V.sub.in in value, out of
the first to mth comparators A.sub.1 to A.sub.m,
instantaneously.
[0026] FIG. 3 is a circuit diagram theoretically showing the
configuration of the comparators included in the AD conversion
circuit. This diagram shows the first comparator A.sub.1 of FIG. 2.
The second to mth comparators A.sub.2 to A.sub.m have the same
configuration as that of the first comparator A.sub.1. The first
comparator A.sub.1 chiefly includes a first inverting circuit 28, a
second inverting circuit 30, a latch circuit 40, a NOR circuit 44,
and a fourth inverting circuit 45. The first inverting circuit 28
and the second inverting circuit 30 are arranged in series. The
input terminal of the first inverting circuit 28 is connected to
one end of a first capacitor C.sub.1. The first capacitor C.sub.1
has a capacitance of 5 pF, for example, and is connected to a first
node 24 at the other end. The output terminal of the first
inverting circuit 28 is connected to one end of a second capacitor
C.sub.2. The other end of the second capacitor C.sub.2 is connected
to the input terminal of the second inverting circuit 30. The
output of the second inverting circuit 30 is input to the latch
circuit 40. The output of the latch circuit 40 is input to the NOR
circuit 44 via a third feedback path 42, and is also inverted and
output as V.sub.out by a third inverting circuit 60. The NOR
circuit 44 also receives a timing signal P.sub.1 that is inverted
by the fourth inverting circuit 45.
[0027] When the timing signal P.sub.1 is low, the NOR circuit 44
always outputs low. When the timing signal P.sub.1 is high, the NOR
circuit 44 outputs low if the output of the latch circuit 40 is
high, and outputs high if the output of the latch circuit 40 is
low. A third capacitor C.sub.3 is interposed between the output
terminal of the NOR circuit 44 and the input terminal of the first
inverting circuit 28. The third capacitor C.sub.3 may be a small
capacitor, for example, on the order of 0.0005 pF. Parasitic
capacitances such as the gate capacitor of a transistor and an
aluminum-to-aluminum capacitance may also be used.
[0028] The input voltage V.sub.in is applied to the first node 24
through a first switch 20. The reference voltage V.sub.ref is
applied to the first node 24 through a second switch 22. The output
of the first inverting circuit 28 is fed back to a second node 26,
which establishes the connection between the input terminal of the
first inverting circuit 28 and the first capacitor C.sub.1, through
a third switch 32. Similarly, the output of the second inverting
circuit 30 is fed back to a third node 27, which establishes the
connection between the input terminal of the second inverting
circuit 30 and the second capacitor C.sub.2, through a fourth
switch 34. The first inverting circuit 28 inverts and outputs a
signal input thereto. This output signal is further inverted and
output by the second inverting circuit 30.
[0029] Description will now be given of the operation of the first
comparator A.sub.1. In an initialization operation on this circuit,
all of the second switch 22, the third switch 32, and the fourth
switch 34 are turned on. In the meantime, the first inverting
circuit 28 and the second inverting circuit 30 settle down at
values 1/2 their output ranges because their outputs, or inverted
inputs, are fed back. Given a power supply voltage of 3 V, the
first inverting circuit 28 and the second inverting circuit 30
settle down at 1.5 V, or at the midpoints in their output ranges.
When the second switch 22, the third switch 32, and the fourth
switch 34 are turned off, the potential of the first node 24 and
the potential of the second node 26 are held at the voltage value
of the reference voltage V.sub.ref and at 1.5 V, respectively.
[0030] In a comparison operation, the first switch 20 is turned on
to apply the input voltage V.sub.in. The potential of the first
node 24 varies as much as a difference between the reference
voltage V.sub.ref and the input voltage V.sub.in, or
.DELTA.V=V.sub.ref-V.sub.in. Where the third capacitor C.sub.3 and
the potential difference across the same are negligible, the
potential of the second node 26 is pushed up or down from 1.5 V by
.DELTA.V, or into 1.5 V+.DELTA.V. When this .DELTA.V has a positive
value, the first inverting circuit 28 outputs low. When .DELTA.V
has a negative value, the first inverting circuit 28 outputs high.
The second inverting circuit 30 inverts the output of the first
inverting circuit 28 further. Eventually, V.sub.out becomes high
when .DELTA.V has a positive value, and V.sub.out becomes low when
.DELTA.V has a negative value. The latch circuit 40 outputs a value
based on the signal input from the second inverting circuit 30 when
a clock signal QC.sub.1 is high. More specifically, when the second
inverting circuit 30 outputs high, the latch circuit 40 outputs
low. When the second inverting circuit 30 outputs low, the latch
circuit 40 outputs high. Note that when the output of the second
inverting circuit 30 is 1.5 V, the output of the latch circuit 40
is kept at the previous output value.
[0031] The timing signal P.sub.1 is low during the initialization
operation, and high during the comparison operation. Thus, the NOR
circuit 44 always outputs low in the initialization operation. In
the comparison operation, the NOR circuit 44 outputs low when the
output of the latch circuit 40 is high, and outputs high when the
output of the latch circuit 40 is low. When the output voltage
V.sub.out is high, the output of the latch circuit 40 is low. When
the timing signal P.sub.1 becomes high, the latch circuit 40
outputs high, so that the potential of the third capacitor C.sub.3
on the side of the NOR circuit 44 is low. Consequently, when the
output voltage V.sub.out changes from high to low, the potential of
the third capacitor C.sub.3 on the side of the NOR circuit 44
remains low. This precludes the second node 26 from being pushed up
in potential. On the other hand, when the output voltage V.sub.out
changes from low to high, the potential of the third capacitor
C.sub.3 on the side of the NOR circuit 44 is switched from low to
high. This pushes up the potential of the second node 26 by an
amount corresponding to the capacitance of the third capacitor
C.sub.3, or a small voltage .DELTA.Vx. This gives the second node
26 a potential of 1.5+.DELTA.V+.DELTA.Vx, thereby removing noise
effect as much as .DELTA.Vx.
[0032] FIG. 4 is a timing chart showing the initialization
operations and the comparison operations. The chart shows, in
descending order, the on-off timing of the second switch 22, the
first switch 20, the third switch 32, and the clock signal
QC.sub.1. Initially, when the second switch 22 and the third switch
32 are turned on, the first inverting circuit 28 starts the
initialization operation. When the second switch 22 and the third
switch 32 are turned off, the first inverting circuit 28 ends the
initialization operation. The clock signal QC.sub.1 is then turned
off, and the first switch 20 on. While the first switch 20 is
turned on, the comparison operation is performed on the input
voltage V.sub.in and the reference voltage V.sub.ref. Before the
first switch 20 is turned off, the clock signal QC.sub.1 is turned
on to output the output voltage V.sub.out from the latch circuit
40. When the first switch 20 is turned off, the second switch 22
and the third switch 32 are turned on to start the next
initialization operation. The initialization operation and the
comparison operation are repeated in this way.
[0033] FIG. 5 shows the hysteresis occurring between the input
voltage and the output voltage. When the input voltage Vin exceeds
a threshold T.sub.2 and the output voltage V.sub.out changes from
low to high, the output voltage V.sub.out will not switch from high
to low even if the input voltage V.sub.in falls below the threshold
T.sub.2. When the input voltage V.sub.in keeps falling to below a
threshold T.sub.1, the output voltage V.sub.out switches from high
to low. Subsequently, the output voltage V.sub.out remains low even
if the input voltage V.sub.in rises to above the threshold T.sub.1.
When the input voltage V.sub.in exceeds the threshold T.sub.2, the
output voltage V.sub.out switches from low to high. As can be seen,
the thresholds T.sub.1 and T.sub.2 have a difference of .DELTA.Vx,
which is a voltage value corresponding to the third capacitor
C.sub.3. This .DELTA.Vx constitutes the hysteresis dead zone, in
which the input voltage V.sub.in varies without switching the
output voltage V.sub.out. Here, the output voltage V.sub.out is
kept at the previous value, either high or low.
[0034] As described above, the first comparator A.sub.1 operates
without changing the value of the reference voltage V.sub.ref
itself. Instead, the first comparator A.sub.1 operates such that
the threshold T.sub.2 of the input voltage V.sub.in in switching
the output voltage V.sub.out from low to high and the threshold
T.sub.1 of the input voltage V.sub.in in switching the same from
high to low have different values from each other. This causes
hysteresis near the reference voltage V.sub.ref, so that small
variations in the input voltage V.sub.in between the thresholds
T.sub.1 and T.sub.2, ascribable to noise, have no effect on the
output voltage V.sub.out any longer. The width of the difference
between T.sub.1 and T.sub.2 depends on the value of the third
capacitor C.sub.3. The third capacitor C.sub.3, however, need not
have a strictly-determined value in terms of circuit design, but
may be given only some small value for a corresponding effect.
Consequently, the hysteresis circuit of the present embodiment has
the design facility that the third capacitor C.sub.3 and the NOR
circuit 44 have only to be provided chiefly. The circuit area can
thus be suppressed smaller. Moreover, since the operation is under
the control of the NOR circuit 44, it is possible to exercise
control easily with the configuration simpler than that of
conventional hysteresis circuits using analog switches.
Second Embodiment
[0035] Comparators according to the present embodiment make
basically the same operations as those of the comparators according
to the first embodiment. Note that the comparators of the present
embodiment, as shown in FIG. 6, are configured to include
differential amplifiers. In other respects than the comparators,
the present embodiment has the same circuit configuration as in the
first embodiment. Description thereof will thus be omitted.
[0036] FIG. 6 shows the configuration of a comparator according to
the second embodiment. In the first comparator A.sub.1, a first
differential amplifier 50 and a second differential amplifier 52
are arranged in series. The first differential amplifier 50
corresponds to the first inverting circuit 28 in FIG. 3, and has
differential input terminals and inverted differential output
terminals. Similarly, the second differential amplifier 52
corresponds to the second inverting circuit 30 in FIG. 3, and has
differential input terminals and inverted differential output
terminals.
[0037] The differential outputs of the second differential
amplifier 52 are inverted by a fifth inverting circuit 54 and a
sixth inverting circuit 56, respectively, and input to an RS latch
circuit 58. These circuits, namely, the fifth inverting circuit 54,
the sixth inverting circuit 56, and the RS latch circuit 58 chiefly
correspond to the latch circuit 40 of FIG. 3. Note that the clock
signal QC.sub.1 input to the latch circuit 40 corresponds, in FIG.
6, to an eleventh switch 78 for turning on and off the power supply
of the second differential amplifier 52. The output of the RS latch
circuit 58 is inverted into an output voltage V.sub.out by a third
inverting circuit 60.
[0038] The output of the RS latch circuit 58 is input to a NOR
circuit 44 via a third feedback path 42. The NOR circuit 44 outputs
the logic NOR between the output of the RS latch circuit 58 and a
signal obtained by inverting a timing signal P.sub.1 through a
fourth inverting circuit 45. The NOR circuit 44 and the fourth
inverting circuit 45 correspond to the NOR circuit 44 and the
fourth inverting circuit 45 of FIG. 3. A sixth capacitor C.sub.6 is
arranged on the path that establishes connection between the NOR
circuit 44 and an input terminal of the first differential
amplifier 50. The sixth capacitor C.sub.6 corresponds to the third
capacitor C.sub.3 of FIG. 3. The input voltage V.sub.in is
differentially input through a fifth switch 66 and a seventh switch
70. The reference voltage V.sub.ref is differentially input through
a sixth switch 68 and an eighth switch 72. The fifth switch 66 and
the seventh switch 70 correspond to the first switch 20 of FIG. 3.
The sixth switch 68 and the eighth switch 72 correspond to the
second switch 22 of FIG. 3.
[0039] The differential input terminals of the first differential
amplifier 50 are in connection with a fourth capacitor C.sub.4 and
a fifth capacitor C.sub.5, respectively. The fourth capacitor
C.sub.4 and the fifth capacitor C.sub.5 correspond to the first
capacitor C.sub.1 of FIG. 3. The differential output terminals and
the differential input terminals of the first differential
amplifier 50 are connected to a fourth feedback path 82 and a fifth
feedback path 84, which correspond to the first feedback path 36 of
FIG. 3. A ninth switch 74 and a tenth switch 76, formed on the
fourth feedback path 82 and the fifth feedback path 84, correspond
to the third switch 32 of FIG. 3.
[0040] The circuits described above operate theoretically the same
as the first comparator A.sub.1 shown in FIG. 3 does. Description
of the detailed operations will thus be omitted. This configuration
can also achieve an easy-to-control hysteresis circuit of simple
configuration as in the first embodiment.
Third Embodiment
[0041] An AD conversion circuit according to the present embodiment
is a pipelined AD conversion circuit.
[0042] FIG. 7 shows the configuration of the AD conversion circuit
according to the third embodiment. The AD conversion circuit 200 is
composed of s stages, which process AD conversion in several bits
each. Here, the AD conversion circuit 200 includes a first stage
202, a second stage 204, a third stage 206, . . . , an sth stage
208. The first stage 202 converts input voltages V.sub.in.sup.+ and
V.sub.in.sup.- into several bits of digital value, and transmits it
to a signal generating circuit 210. The first stage 202 also
subtracts the converted values from the original input values,
amplifies the resultants, and transmits them to the second stage
204. Similarly, the second stage 204 converts the input values into
several bits of digital value, and transmits it to the signal
generating circuit 210. The second stage 204 subtracts the
converted values from the original input values, amplifies the
resultants, and transmits them to the third stage 206. The third
stage 206 also converts the input values into several bits of
digital value, and transmits it to the signal generating circuit
210. The third stage 206 subtracts the converted values from the
original input values, amplifies the resultants, and transmits them
to the next stage. The final stage, or sth stage 208, converts the
input values into several bits of digital value, and transmits it
to the signal generating circuit 210.
[0043] While the values past the conversion by the first stage 202
are subjected to the AD conversion in the second stage 204, the
first stage 202 performs an AD conversion on the next input values.
In this way, the first stage 202, the second stage 204, the third
stage 206, . . . , the sth stage 208 process their respective AD
conversions in parallel. The AD conversion in each stage includes
processing of only several bits, such as four bits or less, and
thus has high processing speed. Besides, the individual stages make
simultaneous processing. The processing speed is thus improved as a
whole. The digital signals output from the respective stages are
collected by the signal generating circuit 210 for output.
[0044] FIG. 8 shows the detailed configuration of the first stage.
The first stage 202 includes a sample-and-hold circuit 212, a sub
AD conversion circuit 214, a sub DA conversion circuit 216, a first
subtracter 218, a second subtracter 220, and an amplifier 222. The
input voltages V.sub.in.sup.+ and V.sub.in.sup.- are differentially
input to and held in the sample-and-hold circuit 212. The analog
values held in the sample-and-hold circuit 212 are converted into n
bits of digital value by the sub AD conversion circuit 214. The
digital value is output to the signal generating circuit 210, as
well as converted into analog values by the sub DA conversion
circuit 216. The first subtracter 218 and the second subtracter 220
subtract the analog values converted by the sub DA conversion
circuit 216 from the values held in the sample-and-hold circuit
212. The resultants are differentially input to the amplifier 222.
The amplifier 222 amplifies the signals received from the first
subtracter 218 and the second subtracter 220, and transmits the
resultants to the next stage, or second stage 204.
[0045] The sub AD conversion circuit 214 is the same flash type AD
conversion circuit as the AD conversion circuit 10 of FIG. 2. In
spite of the different numbers of bits, the sub AD conversion
circuit 214 makes the same operations as those of the AD conversion
circuits 10 in the first and second embodiments. Consequently, the
sub AD conversion circuit 214 can also achieve an easy-to-control
hysteresis circuit of simple configuration as in the first and
second embodiments.
[0046] Up to this point, the present invention has been described
in conjunction with the embodiments thereof. These embodiments are
given solely by way of illustration. It will be understood by those
skilled in the art that various modifications may be made to
combinations of the foregoing components and processes, and all
such modifications are also intended to fall within the scope of
the present invention. The following provides one of the
modifications.
[0047] The foregoing embodiments have dealt with the control that
the reference voltage V.sub.ref is applied in the initialization
operation, and the input voltage V.sub.in is applied in the
comparison operation. In a modification, the control may be such
that the input voltage V.sub.in is applied in the initialization
operation, and the reference voltage V.sub.ref is applied in the
comparison operation.
* * * * *