U.S. patent application number 11/038487 was filed with the patent office on 2005-08-18 for frequency divider.
This patent application is currently assigned to THALES. Invention is credited to De Gouy, Jean-Luc, Gabet, Pascal.
Application Number | 20050179475 11/038487 |
Document ID | / |
Family ID | 34639781 |
Filed Date | 2005-08-18 |
United States Patent
Application |
20050179475 |
Kind Code |
A1 |
De Gouy, Jean-Luc ; et
al. |
August 18, 2005 |
Frequency divider
Abstract
A divider to divide a frequency F.sub.e comprises at least the
following elements: three flip-flop circuits, each of the flip-flop
circuits receiving the frequency to be divided, every feedback loop
between an output of a flip-flop circuit and its input or the input
of the other flip-flop circuits comprising a single multiplexer,
wherein one of the flip-flop circuits commands the loading of all
the flip-flop circuits during one period of the frequency A
multiplexer has two inputs, one selection bit and one output and is
integrated into a flip-flop circuit.
Inventors: |
De Gouy, Jean-Luc; (Briis
Sous Forges, FR) ; Gabet, Pascal; (Cholet,
FR) |
Correspondence
Address: |
LOWE HAUPTMAN GILMAN & BERNER, LLP
1700 DIAGNOSTIC ROAD, SUITE 300
ALEXANDRIA
VA
22314
US
|
Assignee: |
THALES
Neuilly Sur Seine
FR
|
Family ID: |
34639781 |
Appl. No.: |
11/038487 |
Filed: |
January 21, 2005 |
Current U.S.
Class: |
327/115 |
Current CPC
Class: |
H03K 23/665 20130101;
H03K 23/544 20130101 |
Class at
Publication: |
327/115 |
International
Class: |
H03K 021/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 20, 2004 |
FR |
04 00496 |
Claims
1. A divider to divide a frequency comprising: three flip-flop
circuits, each of the flip-flop circuits receiving the frequency to
be divided, every feedback loop between an output of a flip-flop
circuit and its input or the input of the other flip-flop circuits
comprising a single multiplexer, wherein one of the flip-flop
circuits commands the loading of all the flip-flop circuits during
one period of the frequency.
2. The device according to claim 1, wherein a multiplexer has two
inputs, one selection bit and one output and is integrated into a
flip-flop circuit.
3. The device according to claim 1, comprising two latch circuits
and two multiplexers, respectively receiving two inputs of the
divider.
4. The device according to claim 3, wherein a multiplexer is
integrated with a flip-flop circuit.
5. The device according to claim 2, comprising two latch circuits
and two multiplexers, respectively receiving the two inputs of the
divider.
6. The device according to claim 1 comprising two flip-flop
circuits and two multiplexers, respectively receiving the two
inputs of the divider.
7. The device according to claim 2 comprising two flip-flop
circuits and two multiplexers, respectively receiving the two
inputs of the divider.
8. The divider with three division ratios comprising a device
according to claim 1.
9. The device according to claim 2, comprising two latch circuits
and two multiplexers, respectively receiving two inputs of the
divider.
Description
BACKGROUND OF THE INVENTION
[0001] The invention pertains to a frequency division device with
at least three division ratios.
[0002] It can be applied, for example, in the field of frequency
synthesis as a front-end divider for a fractional ratio division
chain.
[0003] Prior art front-end dividers are generally dividers with two
consecutive division ratios.
SUMMARY OF THE INVENTION
[0004] The invention relates to a device for dividing a frequency
F.sub.e. The device comprises at least the following elements:
[0005] three flip-flop circuits (U.sub.1, U.sub.2, U.sub.3), each
of the flip-flop circuits receiving the frequency F.sub.e to be
divided, every feedback loop between an output of a flip-flop
circuit and its input or the input of the other flip-flop circuits
comprising a single multiplexer (M.sub.1, M.sub.2, M.sub.3),
wherein
[0006] one of the flip-flop circuits commands the loading of all
the flip-flop circuits (U.sub.1, U.sub.2, U.sub.3) during a period
of F.sub.e.
[0007] A multiplexer comprises, for example two inputs, one
selection bit and one output and is integrated into a flip-flop
circuit.
[0008] The device may have two latch circuits (U.sub.4, U.sub.5)
and two multiplexers (M.sub.4, M.sub.5), respectively receiving the
inputs INC1 and INC2 of the divider. The multiplexer may be
integrated with a flip-flop circuit.
[0009] The device can be applied to a divider with three division
ratios 2/3/4.
[0010] The invention has especially the following advantages: its
working frequency is the maximum because the feedback loop paths
between the D flip-flop circuit output and its input or the input
of another D flip-flop circuit are minimal in terms of numbers of
logic layers. In normal operation, these paths comprise only one
multiplexer. The multiplexer is integrated or can be integrated
with the D flip-flop circuit as a function of the technology.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Other features and advantages of the present invention shall
appear more clearly from the following description which in no way
restricts the scope of the invention, and from the appended
figures, of which:
[0012] FIG. 1 exemplifies a frequency divider dividing by the
ratios 2, 3, 4,
[0013] FIG. 2 shows an alternative embodiment of the divider of
FIG. 1.
MORE DETAILED DESCRIPTION
[0014] In order to understand the principle implemented in the
frequency divider according to the invention, the following example
relates to a three-ratio divider. The principle can also be applied
to frequency dividers with more than 3 ratios, for example 4, 5
etc.
[0015] FIG. 1 provides a schematic view of a frequency divider
dividing a frequency F.sub.e by three ratios 2, 3 and 4. The choice
between the three division ratios is done by means of a command bus
formed by two bits referenced P1 and P2.
[0016] The frequency divider comprises, for example, three D
flip-flop circuits U.sub.1, U.sub.2, U.sub.3 whose outputs are
referenced Q1, Q2 and Q3. Q1 is the output of the divider. The
input signals P1 and P2 can be used to control the division ratio
of this divider. This scheme is optimal in terms of operating
frequency because any feedback function between an output Q, Q of a
D flip-flop circuit D and its input or the input of another D
flip-flop circuit comprises, in normal operation, only one
multiplexer M.sub.1, M.sub.2, M.sub.3 which, in most technologies,
is generally integrated or can be integrated with the D flip-flop
circuit. A multiplexer comprises, for example, two inputs E.sub.i1,
E.sub.i2, one selection bit SELi and one output Si, with i=1, 2,
3.
[0017] Any flip-flop circuit having an output that stores the value
of the input at the instant of the clock transition ( positive or
negative clock signal edge) may also be used to replace a D
flip-flop circuit.
[0018] In the present description, the term "multiplexer"
designates a multiplexer or any other device that possesses one or
more signal inputs, a selection input and an output that copies the
value of one of the signal inputs as a function of the selection
command.
[0019] The three flip-flop circuits work on the same clock signal
F.sub.e. The circuit thus constituted is characterized, for
example, by the following equations:
Q1=P1*Q3+Q2*Q3
Q2=P2*Q3+Q2*Q3
Q3=Q1*Q3
[0020] where "*" designates a logic AND and "+" designates a logic
OR.
[0021] The following table 1 groups together the division ratio
values obtained by the divider of FIG. 1.
1 P1 P2 Division ratio obtained as a function of P1 and P2 0 1 The
circuit divides by 2 1 0 The circuit divides by 3 1 1 The circuit
divides by 4
[0022] FIG. 2 represents an alternative embodiment used to process
the disallowed case where P1=P2=0.
[0023] As compared with the divider of FIG. 1, the divider
additionally has, for example, two latches U.sub.4, U.sub.5 and two
2 multiplexers M.sub.4, M.sub.5, respectively receiving the inputs
INC1 and INC2 of the divider. The two latches may be replaced by
two flip-flop circuits or any other device having the same
function.
[0024] The working of the divider is given in the following table
2.
2 INC1 INC2 0 0 The circuit divides by 2 1 0 The circuit divides by
3 0 1 The circuit divides by 3 1 1 The circuit divides by 4
[0025] For these two embodiments, one of the D flip-flop circuits
commands the loading of the three flip-flop circuits U.sub.1,
U.sub.2, U.sub.3 during a period of the clock signal F.sub.e. This
operation is the optimum from the viewpoint of the positioning time
for the commands P1 and P2 and the elimination of the false
cycles.
[0026] Another characteristic of the device according to the
invention is that Q1 has a low state with a duration equal to only
one period of F.sub.e for all three division ratios. This low state
is, for example, located at the end of a cycle of Q1. This
characteristic is used when this circuit is used as a front-end
divider in a division chain, in giving a possibility of selection
of only one edge of the frequency F.sub.e per output cycle of the
front-end divider.
[0027] According to another alternative embodiment, each D
flip-flop circuit is subdivided into at least two latch
circuits.
[0028] Another variant consists in keeping the same logic equations
giving Q1, Q2 and Q3 which are characteristic of the circuit and in
applying the usual logic transformations to them. An example of a
transformation consists in complementing the two parts of each
equation.
[0029] Without departing from the framework of the invention, any
flip-flop circuit whose output stores the value of the input at the
instant of the clock transition (positive or negative clock signal
edge) can be used in the divider according to the invention.
* * * * *