U.S. patent application number 10/836618 was filed with the patent office on 2005-08-18 for method of etching porous dielectric.
Invention is credited to Yeoh, Joon Chai.
Application Number | 20050178741 10/836618 |
Document ID | / |
Family ID | 34841429 |
Filed Date | 2005-08-18 |
United States Patent
Application |
20050178741 |
Kind Code |
A1 |
Yeoh, Joon Chai |
August 18, 2005 |
Method of etching porous dielectric
Abstract
The present invention relates to methods of etching a porous
dielectric. The method includes etching the film in a plasma etch
chamber with CF.sub.4, H.sub.2 and a noble gas, wherein the
CF.sub.4 to H.sub.2 gas flow ratio is between 1.33:1 and 2.7:1 and
the noble gas is greater than about 42% of the total gas flow to
the plasma chamber.
Inventors: |
Yeoh, Joon Chai; (North
Shields, GB) |
Correspondence
Address: |
VOLENTINE FRANCOS, & WHITT PLLC
ONE FREEDOM SQUARE
11951 FREEDOM DRIVE SUITE 1260
RESTON
VA
20190
US
|
Family ID: |
34841429 |
Appl. No.: |
10/836618 |
Filed: |
May 3, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60468263 |
May 7, 2003 |
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Current U.S.
Class: |
216/67 ;
257/E21.252 |
Current CPC
Class: |
H01L 21/31116
20130101 |
Class at
Publication: |
216/067 |
International
Class: |
C23F 001/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 3, 2003 |
GB |
0310238.1 |
Claims
What is claimed is:
1. A method of etching a porous carbon-doped silicon dioxide type
dielectric film including plasma etching the film in a plasma etch
chamber with CF.sub.4, H.sub.2 and a noble gas, wherein the
CF.sub.4 to H.sub.2 gas flow ratio is between 1.33:1 and 2.7:1 and
the noble gas is greater than about 42% of the total gas flow to
the plasma chamber.
2. A method as claimed in claim 1 wherein the CF.sub.4:H.sub.2
ratio is about 2:1.
3. A method as claimed in claim 1 wherein the noble gas is
argon.
4. A method as claimed in claim 3 wherein argon is present at up to
about 77% of the total gas flow to the plasma etch chamber.
5. A method as claimed in claim 1 wherein film temperature is in
the range of 100.degree. C. and 170.degree. C.
6. A method as claimed in claim 1 wherein the chamber pressure is
in the range 90 mT to 300 mT.
7. A method as claimed in claim 1 wherein the power supplied to the
plasma is between 700 and 1000 Watts.
8. A method as claimed in claim 1 wherein the etch is terminated
within the film.
9. A method as claimed in claim 8 wherein the film is within an
interconnect structure.
10. A method as claimed in claim 1 wherein the plasma etch is
forming an interconnect structure or other relevant structure in
the film.
11. A device incorporating a film as etched by the method of claim
1.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] A claim of priority is made to U.S. provisional application
Ser. No. 60/468,263, filed May 7, 2003, and to British patent
application no. 0310238.1, filed May 3, 2003.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to methods of etching a porous
dielectric layer that forms part of an interconnect structure on a
substrate such as a wafer or multi chip module. In particular, but
not exclusively, it relates to a method of etching a porous
dielectric layer forming part of a dual damascene structure. More
particularly it relates to a method of etching the upper part of a
dual damascene structure.
[0003] To reduce the RC product in interconnect layers there is a
requirement to reduce the capacitive coupling between adjoining
conductors. Low dielectric constant (k) materials are therefore
desirable and it is known that a vacuum gap has the lowest k value
of 1. A known method of reducing bulk insulators' k values is to
introduce porosity such that there is a matrix material and voids,
thereby reducing the k value to less than that of the matrix.
[0004] Such porous materials present numerous problems for
integration into practical devices and an additional complexity is
introduced by the requirement to make ever smaller structures. As
yet no porous dielectrics have been successfully integrated into
state of the art devices in volume manufacturing for public
sale.
[0005] At e.g. the 65 nm technology node there is a potential
integration scheme whereby the total thickness of the dual
damascene dielectric is deposited without an etch stop layer within
it. The trench is then etched for a timed period into the
dielectric and the etching terminated part way through the
thickness of the dielectric. Over and above all the well known
desirable aspects of anisotropic etching there is an additional
requirement that the base of the etched trench is smooth. If the
dielectric is porous (i.e. containing voids) then this is clearly a
challenge. If the voids are very small then stopping in the voided
dielectric may be acceptable though some degree of `healing` of
these voids is also desirable.
[0006] The Applicants have developed a porous dielectric known as
Orion.TM. as is described in various patent applications in the
name of the Applicants, e.g. WO/03/009364. This material has a k
value in the range of 1.8 to 2.6 and is under evaluation at this
time for integration into 65 nm (and below 65 nm) design rule logic
devices at a k value of 2.2 to 2.5. It is this material that has
been etched in this invention, though the invention also relates to
any porous carbon doped silicon dioxide low-k dielectric e.g. a
SiCOH type material. Typically such carbon doped oxides have methyl
groups contained within them. Carbon (and thereby hydrogen)
concentrations may be varied, higher concentrations leading to
porosity under certain circumstances.
[0007] It should be made clear that this application is not related
to the etched sidewalls. It is well known that to achieve
anisotropic (directional) etching polymer is deposited on sidewalls
to protect them from chemical attack whilst bombardment of the etch
front (base of trench) removes this protective layer enabling
downward etching. After etching the photoresist and any remaining
polymer is then removed.
[0008] It should also be understood that in almost all cases layers
of material forming interconnect layers are completely etched
through such that the etch process stops on an `etch stop` layer or
some other layer that etches more slowly in the etchant than the
layer being etched. It is somewhat unusual to terminate an etch
part way through a layer but elimination of a device etch-stop
layer is highly desirable as it reduces the effective k value of
the structure and reduces the number of interfaces between layers.
The Applicants have found (in unpublished work) that, perhaps not
surprisingly, when such a partial etch is performed on a porous
dielectric then a rough trench base is formed. This can be seen in
FIGS. 1 (a) and 1 (b).
[0009] FIG. 1 (a) and (b) show rough etch front on SEM images after
partial etch using CF.sub.4 and CH.sub.2F.sub.2 gases, at 1250 W
helicon source plasma power, 400 W platen (wafer) bias power, 2
mTorr, with wafer helium back pressure of 15 Torr (giving a wafer
surface temperature of approximately 90-100.degree. C. as indicated
by temperature sensitive labels) in a MORI.TM. process chamber, as
supplied by the Applicants.
[0010] FIG. 1 (a) shows a dual damascene structure. The etched
porous oxide surface is at 1.
[0011] There is therefore a need for an improved etch process to
provide a smooth base to an etched feature formed within a carbon
doped silicon oxide type porous dielectric layer.
SUMMARY OF THE INVENTION
[0012] From one aspect the invention consists in a method of
etching a porous carbon-doped silicon dioxide type dielectric film
including plasma etching the film in a plasma etch chamber with
CF.sub.4H.sub.2 and a noble gas, wherein the CF.sub.4 to H.sub.2
gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is
greater than about 42% of the total gas flow to the plasma
chamber.
[0013] From another aspect the invention provides a method of
plasma etching a porous dielectric layer of carbon doped silicon
oxide material such as a SiCOH material with the following
desirable characteristics:
1 Characteristic Target result Etch depth 40-70% of film thickness
Etch rate 200-500 nm/min Selectivity to photoresist Greater than
5:1 ARDE percentage less than 5% (Aspect Ratio Dependent Etch rate:
the difference in etch rate in features of different aspect ratio)
Side wall angle 90 degrees Micro-trenching none visible in an
electron micrograph Roughness none visible in an electron
micrograph when surface viewed in plan view or at 45.degree. degree
glancing angle (at minimum magnification of 20,000)
[0014] Although the invention has been defined above it includes
any inventive combination of the features set out above or in the
following description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The invention may be performed in various ways and specific
embodiments will now be described with reference to the
accompanying drawings:
[0016] FIGS. 1(a) and (b), are SEM images of an etch front and
partial etch using CF.sub.4 and CH.sub.2F.sub.2 gases;
[0017] FIGS. 2(a), (b) and (c) illustrate similar etch fronts using
CF.sub.4 and H.sub.2 with increasing amounts of argon present;
[0018] FIG. 3(a)a shows the etch front resulting from a non
optimised process, whilst FIG. 3(b) illustrates the effect of a
partial oxygen based resist step on the material of 3 (a);
[0019] FIGS. 4(a), (b) and (c) illustrate the effect of reducing
amounts of backside cooling whilst FIGS. 5(a) and 5(b) are similar
SEM's for a specified set of process conditions;
[0020] FIGS. 6(a) and (b) illustrate the results of the process
using reduced cooling for particular process conditions and can be
compared with FIG. 7 where the same process was run, but with
increased cooling; and
[0021] FIGS. 8(a) and (b) show the etch front surfaces before and
after resist etch has taken place.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] Whilst a rough etch front 1(a) and (b) exhibited in FIG. 5
might be thought of as an obvious consequence of the film's
porosity, it was observed that the surface roughness was greater
than the mean pore size of 1-4 nm. This therefore suggested that
the roughness of the etch front was not simply the result of
exposure of pores and it was therefore postulated that an improved
etch process could yield a smoother etch front/base of trench.
[0023] Initially the Applicants determined that noble gas
additions, such as argon improved the smoothness of the etch front
as illustrated in FIGS. 2, a, b and c.
[0024] Each of the processes illustrated in FIG. 2 was carried out
in the MORI.TM. chamber referred to above with the chamber pressure
being 110 mT, the plasma power 700 w applied to the wafer platen
only and wafer helium backside pressure of 15 T (i.e. the water
temperature was approximately 90-100.degree. C.).
[0025] The gas flow rates, in seem, for the samples illustrated in
FIGS. 2(a), (b) and (c) respectively were as follows:
2 CF.sub.4 80 60 60 H.sub.2 30 30 30 Ar 0 90 120
[0026] At 1 can be seen the etch front/base surface of the porous
oxide where a) is no argon additions, b) has argon added, and c)
has the most argon added to a reactive ion etch process of
CF.sub.4+H.sub.2. It will be seen that the addition of argon
results in a smoother etch front 1, with that of 2(c) being the
smoothest. This is contrary to expectation, as it would be
anticipated that increasing the physical sputter etch component by
adding a heavy noble gas would increase roughness of etch front of
a material of non-uniform density.
[0027] The process of FIG. 2c is still not acceptable and shows for
example pronounced microtrenching at 2.
[0028] It will be noted that in all cases the Applicants had
selected a CF.sub.4 and H.sub.2 mix, rather than the more usual
CF.sub.4/O.sub.2 for the etch gas for the following reasons.
[0029] CF.sub.4 is a well known and readily available fluorine
source and can etch with lower wafer bias power levels than other
well known fluorine containing etch gasses because of its low
polymer generation. Whilst silicon dioxide films are generally
etched in a CF.sub.4+Oxygen gas mix it was determined that oxygen
should be excluded from the etch process, because the Applicants
anticipated that there may be methyl groups formed in the film,
which would be stripped from the film by O.sub.2.
[0030] Hydrogen was then selected as an additional process gas on
the basis of its ability to scavenge fluorine and increase
selectivity by depressing the etch rate of silicon compared to
silicon dioxide or carbide. Hydrogen plasma is known to cure or
treat low-k materials from Applicants GB-A-0020 509. Increasing
levels of hydrogen are known to have only a limited effect on
silicon dioxide etch rate and to increase polymerization. Therefore
the plasma would provide hydrogen radicals from hydrogen gas
directly, rather than from CH.sub.2F.sub.2 gas.
[0031] Argon was selected as a heavy noble gas (others may have
been selected, such as krypton or xenon) because of its ability to
increase ionization efficiency.
[0032] Considerable DOE (Design of Experiment) experimentation was
then performed yielding the conclusions that a CF.sub.4:H.sub.2
ratio of 2:1 was the best for this application, and a range of
CF.sub.4 to H.sub.2 gas flow ratios of between 1.33:1 and 2.7:1
were acceptable.
[0033] This is an unusually high hydrogen concentration. It is
generally held that in a CF.sub.4+Hydrogen gas mix, the etch rate
of both silicon dioxide and silicon falls to about zero at about
40% hydrogen in the CF.sub.4+H.sub.2 gas mix due to the level of
polymerization.
[0034] It was further discovered that for the CF.sub.4 and H.sub.2
flows rates being used, the argon flow should be at least 90 sccm
and preferably about 77 percent of total gas flow. In a process of
80 sccm CF.sub.4 and 40 sccm of hydrogen, then argon gas flow was
preferably 400 sccm and at least 90 sccm.
[0035] A further non-optimized process is shown at FIG. 3a. At 1
the etch front can be seen and shows some surface roughness e.g. at
4 and micro trenching e.g. at 2 after etch completion into
approximately 80 percent of Orion porous SICOH material with a k
value of 2.2. ARDE is less than 2% (0.25 nanometres /1.25 micron
structures), selectivity to photoresist 3 is greater than 6:1 and
the etch rate is greater than 300 nm/min. The same structure as at
FIG. 3a was then subjected to a partial oxygen based resist strip
and the results are shown at FIG. 3b. As can be seen there is
severe roughening of the etched base of the trench.
[0036] It has been discovered that to further improve etch results
stopping within the thickness of the porous carbon-doped oxide then
two further variations are necessary. Firstly, the porous SICOH
material should have small pores with tightly controlled
distribution. A material with average pore sizes in the range 1-4
nm etches more smoothly that a porous dielectric with a larger
average pore size e.g. 4-5 nm and pores ranging in size from 2
nm-12 nm. It has also been found that the wafer temperature during
etching has an effect on the surface roughness of the etch
front.
[0037] Higher wafer temperatures yield smoother etch fronts.
However, the maximum temperature is limited by photoresist
reticulation.
[0038] It is notoriously difficult to specify the temperature of a
film during an etch (or deposition) process as it is practically
impossible to measure. Attempts at estimation may be made using
temperature indicating stickers or `Sensarray.TM.` wafers with
embedded thermocouples, but these are only approximations. It has
however been noted that reducing the pressure of helium to the
backside of the electrostatically clamped wafer (thereby reducing
the thermal coupling of the wafer to the chilled electrostatic
chuck) improved etch front smoothness as illustrated in FIGS. 4a
and b. These are submicron structures etched to 86% of the Orion
film thickness both with the electrostatic chuck coolant set to
-15.degree. C. At FIG. 4a is the etch result with 15 torr of helium
pressure (sufficient to thermally couple the wafer to the chuck
with a small thermal gradient) and in the case of FIG. 4b the
helium pressure is 2 torr. As can be seen the etch front 1 at FIG.
4b is smoother than at FIG. 4a.
[0039] Temperature sensing stickers on the face of a wafer indicate
a wafer surface temperature of 93-99.degree. C. for 15 torr
pressure, -15.degree. C. coolant temperature, and 143-149.degree.
C. for 2 torr helium backpressure and -15.degree. C. coolant
temperature.
[0040] An acceptable wafer surface temperature for the process of
this invention is therefore estimated as above 100.degree. C.,
preferably within the range 130.degree. C. to 220.degree. C., more
preferably between 130-170.degree. C. and most preferably about
150.degree. C. (the upper temperature limited by the photoresist,
higher temperatures being otherwise at least potentially equally
preferable).
[0041] Minimum preferred pressure for the process is 80 mTorr. FIG.
5 (a) and (b) show the onset of etch front 1 surface roughness 4,
for gas flows of 70 sccm CF.sub.4, 30 sccm H.sub.2, 90 sccm Ar, 700
W, with a wafer helium back pressure of 15 T (wafer `cold`).
[0042] FIG. 6 (a) and (b) show smooth etch front 1 after etching at
higher wafer surface temperature (130.degree. to 170.degree. C.).
This is achieved by reducing the Helium back pressure to 2 Torr,
thereby lowering the thermal coupling of platen to wafer. The
process conditions where otherwise revise CF.sub.4--84 sccm;
H.sub.2--42 sccm; Ar--400 sccm; pressure 200 ml and power 1000
W.
[0043] FIG. 7 shows rougher etch fronts after processing at lower
wafer surface temperature (-10 to +99.degree. C.), when Helium back
pressure is 15 Torr. Here the process conditions where essentially
identical to those for FIG. 6 with slight variations in the
CF.sub.4 and H.sub.2 flow rates being 82.55 sccm and 37.5 sccm
respectively.
[0044] In order to prove that smooth etch front surface of the
invention is not due to polymer residues covering the etch
front/base, a N.sub.2+H.sub.2 plasma strip was used to remove the
photoresist post-etch. FIG. 8 (a) shows the smooth etch front 1 and
photoresist 3 in place after hot etch. Figure 8 (b) shows the
equally smooth etch front surface 1 after N.sub.2+H.sub.2 plasma
strip to remove the photoresist. There is no visible polymer
residue remaining.
[0045] The first order major responses of each individual factor
can thus be summarized below.
3 etch front increasing smoothness .mu.-trenching ARDE side wall
angle CF.sub.4/H.sub.2 .dwnarw. .dwnarw. .Arrow-up bold. -- Ar Flow
.Arrow-up bold. -- .dwnarw. -- pressure -- .dwnarw. .Arrow-up bold.
-- power -- .Arrow-up bold. .dwnarw. .Arrow-up bold. temperature
.Arrow-up bold. .dwnarw. -- --
[0046] Best known process conditions to partially etch a porous
SICOH type dielectric to leave a smooth etch front are
therefore:
4 Etch gasses: 80 sccm CF.sub.4, 40 sccm H.sub.2, 400 sccm Ar, 5%
variation in CF.sub.4 and H.sub.2 would yield similar result, so
long as the CF.sub.4:H.sub.2 ratio is kept at about 2:1. Etch
process pressure: 200 mTorr, Plasma power:1000 W: 13.56 MHz applied
to the wafer plate (RIE) (Power needs to be increased as pressure
increases to avoid "wafer lens effect") wafer surface temp.: 100 to
170.degree. C. (e.g. by adjusting platen temperature and/or Helium
wafer back pressure thermal coupling)
* * * * *