U.S. patent application number 11/084429 was filed with the patent office on 2005-08-04 for semiconductor part for component mounting, mounting structure and mounting method.
Invention is credited to Nishiyama, Kazuo.
Application Number | 20050167851 11/084429 |
Document ID | / |
Family ID | 17504179 |
Filed Date | 2005-08-04 |
United States Patent
Application |
20050167851 |
Kind Code |
A1 |
Nishiyama, Kazuo |
August 4, 2005 |
Semiconductor part for component mounting, mounting structure and
mounting method
Abstract
A semiconductor part for component mounting, a mounting
structure and a mounting method providing ample surplus wiring
pitch and width between terminals in order to improve the strength
of the connection with the printed circuit board in view of the
recent trends towards a greater number of pins and greater
component mounting density on printed circuit boards or substrates.
A semiconductor component for mounting has area terminals comprised
of area terminals mounted on the outer circumferential side and
area terminals mounted on the inner circumferential side of the
board. The area terminals on the outer circumferential side of the
board are arranged with a larger pitch and or diameter than the
area terminals on the inner circumferential side. A mounting method
and mounting structure having land terminals arrayed on a printed
circuit board or substrate with the same arrangement as the area
terminals of the semiconductor component, and the land terminals
are connected with the area terminals by a conductive bonding
agent.
Inventors: |
Nishiyama, Kazuo; (Kanagawa,
JP) |
Correspondence
Address: |
SONNENSCHEIN NATH & ROSENTHAL LLP
P.O. BOX 061080
WACKER DRIVE STATION, SEARS TOWER
CHICAGO
IL
60606-1080
US
|
Family ID: |
17504179 |
Appl. No.: |
11/084429 |
Filed: |
March 18, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11084429 |
Mar 18, 2005 |
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10210683 |
Jul 31, 2002 |
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10210683 |
Jul 31, 2002 |
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09398100 |
Sep 17, 1999 |
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6534875 |
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Current U.S.
Class: |
257/778 ;
257/E23.07 |
Current CPC
Class: |
H01L 2924/181 20130101;
H05K 2203/0465 20130101; H01L 23/49838 20130101; H01L 2224/05599
20130101; H01L 2224/85399 20130101; H01L 2924/14 20130101; H01L
2224/73265 20130101; H05K 1/111 20130101; Y02P 70/50 20151101; H05K
2201/094 20130101; H01L 24/48 20130101; H05K 2201/10734 20130101;
H01L 2924/15311 20130101; H01L 2224/48227 20130101; H05K 3/3436
20130101; H01L 2924/00014 20130101; H01L 2924/181 20130101; H01L
2924/00012 20130101; H01L 2224/85399 20130101; H01L 2924/00014
20130101; H01L 2224/05599 20130101; H01L 2924/00014 20130101; H01L
2924/00014 20130101; H01L 2224/45015 20130101; H01L 2924/207
20130101; H01L 2924/00014 20130101; H01L 2224/45099 20130101; H01L
2924/14 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/778 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 25, 1998 |
JP |
P10-271740 |
Claims
We claim:
1. A method of producing portable electronic equipment, the
portable electronic equipment including: an integrated circuit
having a function for the portable electronic equipment, an
interposer board including the integrated circuit and comprising an
outer circumferential side and an inner circumferential side, one
or more area terminals arrayed on the outer circumferential side of
the interposer board, and one or more area terminals arrayed on the
inner circumferential side of the interposer board, and a printed
circuit board comprising an outer circumferential side and an inner
circumferential side, one or more land terminals arrayed on the
outer circumferential side of the printed circuit board, and one or
more terminals arrayed on the inner circumferential side of the
printed circuit board, the method comprising the steps of: (a)
setting the integrated circuit on the substrate of the interposer
board; (b) applying a conductive bonding solution to at least one
of the area terminals arrayed on the outer circumferential side,
the area terminals arrayed on the inner circumferential side, the
land terminals arrayed on the outer circumferential side, and the
land terminals arrayed on the inner circumferential side; and (c)
connecting the area terminal arrayed on the outer circumferential
side to the land terminal arrayed on the outer circumferential
side, and the area terminal arrayed on the inner circumferential
side to the land terminal arrayed on the inner circumferential
side; wherein the area terminal on the outer circumferential side
is arrayed with a larger pitch than the area terminal on the inner
circumferential side; and wherein the land terminal on the outer
circumferential side is arrayed with a larger pitch than the land
terminal on the inner circumferential side.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor part for
component mounting, a mounting structure and a mounting method.
[0003] 2. Description of Related Art
[0004] Strong demands have been made in recent years for portable
electronic equipment such as digital cameras, digital portable
telephones and notebook type personal computers that are thinner,
are more compact and have lighter weight. Therefore, to what extent
the surface mounting density of the semiconductor components used
in the above devices can be increased has become an important
technical issue.
[0005] To cope with this trend, the development of compact CSP
(chip scale packages) typified by packaged ICs such as QFPs has
progressed and some compact chip scale packages are now
available.
[0006] These chip scale packages (CSP) incidentally, as can be seen
from their other name of FP-BGA (Fine Pitch BGA) are designed for a
compact BGA (Ball Grid Array) and their connection pin (hereafter
called area terminals) array usually have an 0.8 mm pitch (BGA
pitch is 1.27 mm.).
[0007] However, to cope with semiconductor LSI chips having higher
density and more functions, the scope of the area terminal layout
has shown a tend to continually increase and even the size of
supposedly small CSP (chip scale packages) are becoming larger.
[0008] In order to allow these semiconductor LSI chips to handle a
higher component mounting density by accommodating more pins, an
even finer pitch is required in the area terminal array.
[0009] A chart of semiconductor assembly technology and mounting
technology progress accompanying the miniaturization of
semiconductor LSI devices is shown in Table 1 below. As can be
seen, the number of area terminals has drastically increased to
keep pace with higher density, systemization and miniaturization of
semiconductor LSI devices. Table 1 also shows that in response to
these developments, the CSP and BGA array pitch has become smaller
and smaller.
1TABLE 1 Development Chart Reflecting Advances in Semiconductor
Technology Number of connection pins Aluminum CSP BGA Design
(general- electrode terminal terminal Year scale purpose) pitch
pitch pitch 1997 0.25 .mu.m 100-295 80 .mu.m 500 .mu.m 1.27 .mu.m
1999 0.18 .mu.m 117-400 70 .mu.m 400 .mu.m 1.27 .mu.m 2001 0.15
.mu.m 137-469 60 .mu.m 400 .mu.m 1.00 .mu.m 2003 0.13 .mu.m 161-551
50 .mu.m 300 .mu.m 1.00 .mu.m 2006 0.10 .mu.m 205-699 50 .mu.m 300
.mu.m 0.80 .mu.m
[0010] In a more specific description given while referring to the
drawings, the CSP area terminals 1 and 2 are shown respectively in
FIGS. 5A and 5B. A 0.8 mm pitch array is shown in FIG. 5A and a 0.5
mm pitch array is shown in FIG. 5B. In these figures, the reference
numeral 20 denotes the (LSI) chip, 21 denotes a bonding wire, 22
denotes the plastic mold, and 23 denotes the bonding agent
(adhesive).
[0011] Upon comparing these two pitch arrays in FIGS. 5A and 5B, it
can be clearly observed that as the package size becomes smaller
due to miniaturization, the diameter of the area terminal 2 becomes
extremely small when the terminal array has a 0.5 mm pitch as shown
in FIG. 5B.
[0012] FIG. 6 is a graph showing the correlation of package size
and number of area terminal pins for each type of CSP used in
portable telephones and handy digital video cameras on the market
up till now. The graph shows package size increasing due to the
trend to use a greater number of pins, and the package size
shrinking from miniaturization with a 0.5 mm pitch array. In other
words, the graph clearly shows that high density mounting is
indispensable.
[0013] However, when miniaturizing the pitch array of area
terminals in this way, reducing the size of the terminals is of
course unavoidable. Even when mounting (connecting) chip scale
packages (CSP) on boards, there is a large possibility of the
connection strength deteriorating due to factors such as heat
stress after mounting.
[0014] On the other hand, FIG. 7A shows the area terminals 1
arrayed with an 0.8 mm pitch on a CSP and at a 0.5 mm pitch in FIG.
7B along with the repositioned wiring 3 and 3a. As this figure
clearly shows, more wiring is passing towards the inner side
between the area terminals 1a and 1a rather than on the outermost
side.
[0015] When the diameter of the area terminals of the 0.8 mm pitch
array have for example been set to 0.4 mm, the L/S (line &
space) for each wire is 30.8 .mu.m (wiring pitch of 61.5 .mu.m).
However when the area terminal array is at a 0.5 mm pitch, and the
diameter of the area terminals becomes an even smaller 0.25 mm, the
wiring between those terminals have an L/S of 19.2 .mu.m (wire
pitch is 38.5 .mu.m) so that obviously even finer wiring
required.
[0016] Thus, when many wires are laid between the area terminals
and the gap between the terminals becomes exceedingly small, then
fine complex processing also becomes necessary on the board. For
instance, use of built-up multilayer wiring board such as in the
multilayering to rout the wiring 5 to the land terminal 4 is
required as shown in FIGS. 8A and 8B.
SUMMARY OF THE INVENTION
[0017] In view of the above problems with the conventional art, and
in view of recent trends toward high density component mounting and
increasing the number of pins, this invention therefore has the
object of providing a semiconductor part for component mounting, a
mounting structure and a mounting method wherein the connection to
the printed circuit board is strong and the wiring pitch between
terminals has a sufficient width margin.
[0018] To achieve the above objects of the invention, a
semiconductor part for component mounting of the invention, having
area terminals on the substrate is characterized in that, of the
area terminals that are arrayed on the outer and inner
circumferential sides of the substrate, those area terminals on the
outer circumferential side are arrayed with a larger pitch and/or
diameter than the area terminals on the inner circumferential
side.
[0019] To still further achieve the above objects, a mounting
structure of this invention comprised of a semiconductor part for
component mounting having area terminals, and having land terminals
arrayed on the outer and inner circumferential sides of the board
is characterized in that the land terminals on the outer
circumferential side are arrayed with a larger pitch and/or
diameter than the land terminals on the inner circumferential side
and further characterized in that a conductive bonding solution is
applied between the area terminals and land terminals.
[0020] In this invention, the area terminals on the substrate or
board are comprised of area terminals arrayed on the outer and
inner circumferential sides of the substrate or board. However, in
the semiconductor part arrayed with outer circumferential area
terminals having a larger pitch and/or diameter than the inner
circumferential area terminals, the area terminals may also be
arranged in a flip chip bump array.
[0021] These area terminals may also be installed on the CSP
interposer board, or may be installed on the BGA (ball grid array)
or the LGA (land grid array) interposer boards or may be installed
on the MCM (multi chip module) sub-board.
[0022] The area terminals of the semiconductor part of this
invention possess a diameter large enough to allow positioning on
the outer circumferential side of the board or substrate which is
subject to the greatest heat stress, and the strong connection is
both stable and reliable so that the connection is more than
sufficient to withstand the heat stress applied after mounting.
[0023] The pitch array becomes finer (smaller) the more the area
terminal is positioned on the inner side away from the outer
circumferential side so that the number of terminals can be
increased and the board is able to cope with recent and future
trends towards increased numbers of pins.
[0024] The larger pitch array of the area terminals close to the
outer circumference further signifies that the wiring routed
between those area terminals towards the inner circumferential
terminals has an ample margin and that easier mounting and lower
board wiring costs can be achieved. The larger pitch array also
means larger wires (or wiring) can be utilized so that high-speed,
high frequency mounting can be achieved since losses due to
resistance in the wiring are reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIGS. 1A and 1B are respectively a fragmentary cross
sectional view (1A) and a bottom view (1B) showing the array of the
area terminals for the chip scale packages of this embodiment of
this invention, wherein outermost row has pitch of 0.8 mm and inner
roll has pitch of 0.65 mm and two rows further inward have pitch of
0.5 mm.
[0026] FIGS. 2A and 2B are respectively a lower cross sectional
view (2A) and a flat plan view (2B) showing the array of the area
terminals for the flip chip type chip scale packages of this
embodiment of this invention, wherein outermost two rows have pitch
of 0.8 mm and inner three rolls have pitch of 0.5 mm.
[0027] FIGS. 3A and 3B are process views showing the mounting
procedure for the chip scale packages of the embodiment of this
invention with (3A) as the view prior to mounting and (3B) as the
view after mounting.
[0028] FIG. 4 is a pattern view of the area terminal (or land
terminals of the board/substrate) array status of this
invention.
[0029] FIGS. 5A and 5B are respectively a side view (5A: 0.8 mm
pitch CSP) and a flat view (5B: 0.5 mm pitch CSP) showing the area
terminal array of the chip scale package of the conventional
art.
[0030] FIG. 6 is a graph showing the number of terminal pins and
the package sizes for the main chip scale packages currently in
use.
[0031] FIG. 7A (area terminals with 0.8 mm pitch and wiring) and
FIG. 7B (area terminals with 0.5 mm pitch and wiring) are pattern
views showing the area terminal array status and wiring in the
conventional art.
[0032] FIGS. 8A and 8B are respectively a pattern view (8A) and a
cross sectional view (8B) showing the built-up multilayer wiring
substrate of the conventional art.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0033] The preferred embodiments of this invention will now be
described in specific detail while referring to the accompanying
drawings. The scope of this invention is not however limited by
such drawings or descriptions.
[0034] One row of large diameter area terminals 7a at a pitch of
0.8 mm are positioned on the outer circumference of an interposer
board 6 of the CSP as shown in FIGS. 1A and 1B. On the inner side
of the area terminal 7 row is one row of mid-size area terminals 7b
at a pitch of 0.65 mm and still further towards the inside of the
interposer board 6 are two rows of small area terminals 7c arrayed
at a pitch of 0.5 mm. In FIG. 1A, the reference numeral 20 denotes
an LSI (large scale integrated circuit) chip, 21 is bonding wires,
22 is a plastic molded package, and 23 is a bonding solution
(adhesive). The total number of area terminals 7 in this state is
136 pins. In contrast, in the conventional arrangement of area
terminals all of the same diameter arrayed at a 0.8 mm pitch, the
total number of area pins does not exceed 96 pins.
[0035] Next, in the flip type CSP interposer board 8 in FIG. 2, two
rows of mid-size area terminals 9a at a pitch of 0.8 mm are arrayed
on the outermost circumference of the interposer board 8. On the
inner side of the area terminal 9a are three rows of small area
terminals 9b at a pitch of 0.5 mm. In the arrangement in this
figure, the reference numeral 24 is a bump and 25 is the bonding
solution (adhesive) Of course, in the case of FIG. 2, the mid-size
area terminals 9a and the small area terminals 9b can be combined
at 0.8 mm pitch and a 0.65 pitch or at a 0.65 pitch and a 0.5 mm
pitch.
[0036] The process for the CSP with the area terminals arrayed as
described above onto the printed circuit board is shown in FIG. 3A.
The area terminals 11 on the interposer board 10 may for instance
be connected to the land terminals of the printed circuit board 12
with a conductive bonding material such as a solder cream 14. The
status after connection is shown in FIG. 3B.
[0037] Naturally, the printed circuit board has the same terminal
array (arrangement) as the interposer board/substrate. The closer
to the outer circumference of the board, the larger the diameter
and pitch of the land terminals. The farther to the inside of the
board, the smaller the diameter and pitch of the land terminals.
Solder is preferably used as the conductive bonding material. An
advantage of using solder is that a self-alignment effect is
obtained due to the melting of the solder. This self-alignment
contributes greatly to obtaining a strong highly reliable
connection, particularly when connecting printed circuit board land
terminals and area terminals on the outermost circumference of the
board/substrate.
[0038] Besides the above mentioned embodiments, this invention is
also applicable to BGA interposer boards. In this case, the number
of pins for the area terminals can be increased even further by
changing the commonly used pitch array of 1.27 mm to a pitch of
1.27 on the outermost circumference and to a pitch from 1.0 to 0.8
on the inner circumference to further miniaturize the area terminal
array on the inner circumferential side to allow handling recent
and future trends toward increasing the number of pins.
[0039] Also, besides the above example, this invention can also be
applied to area terminals on the recently popular MCM sub-boards
and the same effect can be obtained. Also, in the previously
mentioned examples, both the pitch and diameter of the area
terminals were specified as increasing near the outer circumference
however in this invention making a change to increase just the
outer circumference pitch or the diameter is sufficient.
[0040] FIG. 4 shows the wiring status for a printed circuit board
or a CSP interposer board. This figure illustrates how utilizing
the terminal array of this invention can alleviate the wiring load.
In FIG. 4 for example, even though the land terminal 15b or 15c (or
area terminal) array has a small (fine) pitch of 0.5 mm, the pitch
of the wiring 16 is determined by the land terminal 15a (or area
terminal) on the outermost circumference of the board. Thus, not
only can the wiring load of the printed circuit board and
semiconductor part be alleviated but the use of wires of greater
width has the advantages of reducing the resistance in the wire and
allowing high-speed, high frequency mounting.
[0041] As the above description clearly shows, one effect of the
semiconductor part and the mounting structure of this invention is
that the area terminals have a larger size on the outermost
circumference where heat stress is most severe, and these area
terminals exhibit a high contact strength more than sufficient to
withstand heat stress after mounting.
[0042] Another effect of this invention is that since the area
terminals have a smaller pitch toward the inner circumference, the
number of pins can also be increased so the current and future
trends towards an increased number of pins can be accommodated.
[0043] A still further effect of this invention is that with a
larger pitch array the closer the area terminals are to the
outermost circumference of the board, the benefit of space margin
occurs for the wiring running between the outer terminals towards
the inner terminals. This space margin makes mounting easier and
alleviates the wiring load on the printed circuit board or in other
words reduces the wiring costs. Further if wiring with a greater
width is utilized, then resistance losses in the wiring can be
reduced and high-speed, high frequency mounting achieved.
* * * * *