U.S. patent application number 11/087552 was filed with the patent office on 2005-07-28 for wafer level hermetic sealing method.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Cho, Chang-ho, Kim, Woon-bae, Shin, Hyung-Jae.
Application Number | 20050161757 11/087552 |
Document ID | / |
Family ID | 19705301 |
Filed Date | 2005-07-28 |
United States Patent
Application |
20050161757 |
Kind Code |
A1 |
Cho, Chang-ho ; et
al. |
July 28, 2005 |
Wafer level hermetic sealing method
Abstract
A device that is hermetically sealed at a wafer level or a
method of hermetically sealing a device, which is sensitive to high
temperatures or affected by heating cycles. Semiconductor devices
are formed on a wafer. A lid wafer is formed. Adhesives are formed
in a predetermined position over the wafer and/or the lid wafer.
The wafer and the lid wafer are sealed by the adhesives at the
wafer level. The sealing may be performed at a low temperature
using a solder to protect the devices sensitive to heat. The sealed
devices are diced into individual chips. In the wafer level
hermetic sealing method, a sawing operation is performed after the
devices are sealed. Therefore, the overall processing time is
reduced, devices are protected from the effects of moisture or
particles, and devices having a moving structure, such as MEMS
devices, are more easily handled.
Inventors: |
Cho, Chang-ho; (Seoul,
KR) ; Shin, Hyung-Jae; (Gyeonggi-do, KR) ;
Kim, Woon-bae; (Gyeonggi-do, KR) |
Correspondence
Address: |
STEIN, MCEWEN & BUI, LLP
1400 EYE STREET, NW
SUITE 300
WASHINGTON
DC
20005
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Suwon-si
KR
|
Family ID: |
19705301 |
Appl. No.: |
11/087552 |
Filed: |
March 24, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11087552 |
Mar 24, 2005 |
|
|
|
09984734 |
Oct 31, 2001 |
|
|
|
Current U.S.
Class: |
257/433 ;
257/587; 257/E21.499; 257/E23.193 |
Current CPC
Class: |
H01L 2224/48227
20130101; B81B 7/0077 20130101; B81C 1/00357 20130101; H01L
2924/10253 20130101; H01L 2924/01079 20130101; H01L 2224/45099
20130101; H01L 2924/01322 20130101; H01L 2224/05599 20130101; H01L
2924/12041 20130101; H01L 2924/00014 20130101; H01L 2224/85399
20130101; B81C 1/00269 20130101; H01L 23/10 20130101; H01L 21/50
20130101; B81C 2201/019 20130101; H01L 24/48 20130101; H01L
2924/16235 20130101; H01L 2924/10253 20130101; H01L 2924/00
20130101; H01L 2924/12041 20130101; H01L 2924/00 20130101; H01L
2224/85399 20130101; H01L 2924/00014 20130101; H01L 2224/05599
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/45099 20130101; H01L 2924/00014 20130101; H01L 2224/45015
20130101; H01L 2924/207 20130101 |
Class at
Publication: |
257/433 ;
257/587 |
International
Class: |
H01L 021/44; H01L
021/50 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 3, 2001 |
KR |
2001-5256 |
Claims
What is claimed is:
1. An apparatus with a wafer level hermetic seal comprising: a
wafer; a semiconductor device formed on a device side of the wafer;
a lid wafer with a front side facing the device side of the wafer;
and adhesives which adhere the device side of the wafer and the
front side of the lid wafer in a predetermined position, wherein
the adhesives seal the device in between the device side of the
wafer and the front side of the lid wafer.
2. The apparatus with the wafer level hermetic seal of claim 1,
wherein the adhesives are formed of one selected from the group
consisting of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an
alloy of two or more of these metals.
3. The apparatus with the wafer level hermetic seal of claim 2,
wherein the adhesives are formed of a material having a fusion
point of 100.about.300.degree. C.
4. The apparatus with the wafer level hermetic seal of claim 2,
wherein the adhesives are formed by deposition or sputtering.
5. The apparatus with the wafer level hermetic seal of claim 2,
further comprising adhesive promoters formed over the device side
of the wafer and/or the front side of the lid wafer to promote
adhesion of the adhesives.
6. The apparatus with the wafer level hermetic seal of claim 5,
wherein the adhesives and the adhesive promoters are disposed to
align the wafer with the lid wafer.
7. The apparatus with the wafer level hermetic seal of claim 5,
wherein the adhesive promoters are formed of metal or polymer.
8. The apparatus with the wafer level hermetic seal of claim 2,
wherein electrical connectors are formed on the wafer to transceive
an electrical signal.
9. The apparatus with the wafer level hermetic seal of claim 8,
wherein the lid wafer comprises a through hole so that the
electrical connectors are electrically connected to the outside via
an interconnection line passing through the hole.
10. The apparatus with the wafer level hermetic seal of claim 2,
wherein the adhesives have a preformed shape.
11. The apparatus with the wafer level hermetic seal of claim 2,
wherein the lid wafer formed is a transparent material to exchange
an optical signal.
12. The apparatus with the wafer level hermetic seal of claim 1,
wherein the adhesives are formed of a material having a fusion
point of 100.about.300.degree. C.
13. The apparatus with the wafer level hermetic seal of claim 1,
further comprising adhesive promoters formed over the device side
of the wafer and/or the front side of the lid wafer to promote
adhesion of the adhesives.
14. The apparatus with the wafer level hermetic seal of claim 13,
wherein the adhesives and the adhesive promoters are disposed to
align the wafer with the lid wafer.
15. The apparatus with the wafer level hermetic seal of claim 13,
wherein the adhesive promoters are formed of metal or polymer.
16. The apparatus with the wafer level hermetic seal of claim 1,
wherein electrical connectors are formed on the wafer to transceive
an electrical signal.
17. The apparatus with the wafer level hermetic seal of claim 16,
wherein the lid wafer comprises a through hole so that the
electrical connectors are electrically connected to the outside via
an interconnection line passing through the hole.
18. The apparatus with the wafer level hermetic seal of claim 1,
wherein the adhesives have a performed shape.
19. The apparatus with the wafer level hermetic seal of claim 1,
wherein the lid wafer formed is a transparent material to exchange
an optical signal.
20. The apparatus with the wafer level hermetic seal of claim 1,
wherein the adhesives are formed of an organic sealant.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No.
09/984,734 filed on Oct. 31, 2001, now pending, the content of
which is incorporated by reference herein.
[0002] This application claims the benefit of Korean Application
No. 2001-5256, filed Feb. 3, 2001, in the Korean Industrial
Property Office, the disclosure of which is incorporated by
reference herein.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] The present invention relates to a semiconductor device with
a wafer level hermetic seal and a method of hermetically sealing a
device at the wafer level. More particularly, the present invention
relates to a method of hermetically sealing a semiconductor device
which is at a wafer level where the device sensitive to high
temperatures or affected by a heat cycle can be thermally sealed at
a low temperature and is not affected by moisture or particles.
[0005] 2. Description of the Related Art
[0006] Referring to FIGS. 1 and 2, the surfaces of a conventional
semiconductor devices, such as MicroElectroMechanical Systems
(MEMS), are first micro-machined in order to hermetically seal the
devices. The surface micro-machining is a method by which a
sacrificial layer is formed, a structure is formed thereon, and
then the sacrificial layer is removed, thereby forming a moving
structure. In the case where the surface micro-machining is used,
structures or semiconductor devices are formed on a wafer (not
shown) in a state in which the sacrificial layer (also not shown)
is not removed (S201). Then the wafer is sawed in half (S203) and
the sacrificial layer is etched to form moving structures (S205).
The resulting moving structures must be carefully handled because
these structures can be damaged or rendered completely inoperative
by a single microscopic particle. Thus, a first anti-stiction film
is coated on the wafer (S207) to prevent dust or particles from
attaching to the moving structures. This coating also protects the
moving structures during the physical moving, handling and testing
of the devices. The anti-stiction film is a film that prevents dust
or particles from being attached to a surface by lowering the
surface energy of the surface.
[0007] After the first anti-stiction film coating, each individual
device is tested according to a first test (S210). Since the unit
cost of a packaging process is high, this first test is necessarily
performed to seek high quality devices. The atmosphere where the
first test is carried out must be adjusted so that there is almost
no moisture therein. By adjusting the atmosphere, high quality
devices can be prevented from being transformed into low quality
ones during the testing process. The wafer is sawed into individual
chips after the testing is completed (S213). Here, a high
percentage of the chips become defective due to the particles
generated during the sawing process. The equipment used in a
general semiconductor process cannot be used during the sawing
process, while additional equipment for fabricating devices such as
MEMS is required. This results in an increase in the production
cost.
[0008] Each individual chip 105 is attached to a package 100 by a
die adhesive 103 (S215) and electrically connected to the package
100 by a wire-bonding process 118 (S217). Here, the chip is exposed
to the outside environment, and moisture or particles can attach to
the chip if the anti-stiction film becomes contaminated. Therefore,
a cleaning process is performed to remove such particles (S220).
However, a second anti-stiction film coating is necessarily
required because the first anti-stiction film may also be removed
during the cleaning process (S223). Even if the first anti-stiction
film is not removed during the cleaning process, surfaces of the
chip with prolonged exposure to air will absorb the moisture,
making the second anti-stiction film coating necessary. The package
containing the chip is now also coated with the second
anti-stiction film.
[0009] The lid 115 is aligned with the package 100, which is coated
with the second anti-stiction film, and hermetically sealed with a
seal ring 110 (S225). Here, reference numeral 113 represents a lid
frame. By-products, moisture, and particles are generated when the
chip 105 is first tested in an unsealed state and then attached to
the package 100. These factors can damage the device or make the
device completely inoperable. Therefore, a second test is performed
after the seal (S227).
[0010] As described above, performing the hermetic sealing process
in a chip state is costly as well as labor and time intensive. An
increase in cost is attributable to additional equipment needed to
carefully handle the MEMS devices or chips having moving
structures. In addition, maintaining a multiple work environment
such as two anti-stiction coating lines and two testing lines is
also costly, and labor and time intensive. In particular, the
second anti-stiction film is coated on every package before
sealing. This process is slow because the area of the package to be
coated is large, thereby requiring a large amount of time to coat
the anti-stiction film.
[0011] The method of hermetically sealing the package 100 and the
lid 115 includes welding and glass high temperature splicing. In a
typical welding process, the lid frame 113 is attached to the lid
115 while the seal ring 110 is placed in-between the package 100
and the lid 115. Then the lid 115 along with the seal ring 110 is
attached to the package 100 by welding. Here, a high-priced ceramic
or metal is used to ensure the hermetic state.
[0012] A wafer level bonding method includes silicon-silicon fusion
bonding, silicon-glass anodic bonding, eutectic bonding using a
medium such as Au, and bonding using a glass frit. In these
methods, the cleanness of a surface to be sealed is very important
and high temperature or pressure is required.
[0013] Accordingly, these methods are not appropriate for devices
such as MEMS, which use aluminum actuators having a relatively low
fusion temperature. In the case of a silicon-glass anodic bonding
method, bonding is performed at a relatively low temperature of
about 450.quadrature.C. However, even a temperature of about
450.quadrature.C. is too high for aluminum actuators and high
pressure, which may negatively affect the device, is required.
SUMMARY OF THE INVENTION
[0014] To solve the above mentioned problems, it is an object of
the present invention to provide a semiconductor device or chip
with a wafer level hermetic seal and/or a wafer level hermetic
sealing method by which semiconductor device(s) can be sealed at a
wafer level so as not to be affected by moisture or particles, and
at a low temperature so as to be appropriate for devices such as
MEMS structures, which are sensitive to high temperature.
[0015] Additional objects and advantages of the invention will be
set forth in part in the description which follows and, in part,
will be obvious from the description, or may be learned by practice
of the invention.
[0016] Accordingly, to achieve the above and other objects, there
is provided a wafer level hermetic sealing method. In the method,
semiconductor devices are formed on a wafer. A lid wafer is formed.
Adhesives are formed in a predetermined position over the wafer
and/or the lid wafer. The wafer and the lid wafer are sealed
together by the adhesives. The sealed wafer-level devices are diced
into an individual wafer level chip.
[0017] The adhesives are formed of one of In, Sn, Ag, Pb, Zn, Au,
Bi, Sb, Cd, Ga and Cu, or an alloy of two or more of these metals.
The adhesives are formed of a material having a fusion point of
100.about.300.degree. C. The adhesives are formed by deposition or
sputtering. In the operation of forming the adhesives, adhesive
promoters are formed over the wafer and/or the lid wafer to promote
adhesion of the adhesives. In the operation of forming the adhesive
promoters, the adhesives and the adhesive promoters are disposed to
align the wafer with the lid wafer. The adhesive promoters are
formed of metal or polymer. Electrical connectors may be formed on
the wafer to transceive an electrical signal. In the operation of
forming the lid wafer, a hole may be formed in a predetermined
position so that the electrical connectors are electrically
connected to the outside via an interconnection line passing
through the hole.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above object and advantages of the present invention
will become more apparent by describing in detail a preferred
embodiment thereof with reference to the attached drawings in
which:
[0019] FIG. 1 is a cross-sectional view of semiconductor chip
packaged according to a conventional sealing method;
[0020] FIG. 2 is a flowchart showing the conventional sealing
method;
[0021] FIGS. 3A through 3E are drawings describing semiconductor
device(s) with a wafer level hermetic seal and/or method of
hermetically sealing device(s) at a wafer level according to the
present invention; and
[0022] FIG. 4 is a flowchart showing the method of hermetically
sealing device(s) at a wafer level according to the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0023] Reference will now be made in detail to the present
preferred embodiments of the present invention, examples of which
are illustrated in the accompanying drawings, wherein like
reference numerals refer to the like elements throughout. The
embodiments are described below in order to explain the present
invention by referring to the figures.
[0024] Referring to FIGS. 3A through 3E, in the wafer level sealing
method of the present invention, semiconductor devices are formed
at a wafer level, additional lids are also formed at a wafer level,
and the semiconductor devices and the lids are sealed at a low
temperature using an adhesive.
[0025] As shown in FIG. 3A, semiconductor devices 12 are formed on
a wafer 10. Electrical connectors 15 for electrical connection with
the outside may be formed.
[0026] As shown in FIG. 3B, a lid wafer 30 for transceiving an
optical signal is prepared apart from the wafer 10. Adhesives 35
are formed to bond the wafer 10 and the lid wafer 30 together. The
lid wafer 30 may be formed of transparent materials such as glass
in order to exchange an optical signal with the outside. Here, the
adhesives 35 are formed on the lid wafer 30 but may be formed on
the wafer 10. The adhesives 35 may use solder, metal, or organic
sealant, may have a preformed shape, and may be deposited by
deposition or sputtering.
[0027] Also, adhesive promoters 20 and 33 may be further formed
over the wafer 10 and/or the lid wafer 30 to promote adhesion of
the adhesives 35 before the adhesives 35 are formed. Here, the
adhesive promoters 20 and 33 may be formed of metal or polymer.
Particularly, the adhesives 35 and the adhesive promoters 20 and 33
are formed so as to align the wafer 10 with the lid wafer 30,
thereby easily and accurately sealing semiconductor devices at a
wafer level.
[0028] Meanwhile, as shown in FIGS. 3C through 3D, an electrically
connective hole 37 may be formed through the lid wafer 30 in order
to ensure space necessary for the electrical connection to the
electrical connectors 15. In other words, the electrically
connective hole 37 is used as a space for an interconnection line
when portions of the electrical connectors 15 exposed outside are
electrically connected to the outside via an interconnection
line.
[0029] As described above, the wafer 10 aligns with the lid wafer
30 on the basis of the adhesives 35 and the adhesive promoters 20
and 33 after the wafer 10 and the lid wafer 30 are formed, and the
wafer 10 and the lid wafer 30 are sealed under a suitable
atmosphere. Here, when the wafer 10 and the lid wafer 30 are
sealed, cavities 40 are formed therebetween. A low temperature
sealing process is possible if a solder is used as an adhesive in
the sealing process. Here, the solder is preferably formed of one
of In, Sn, Ag, Pb, Zn, Au, Bi, Sb, Cd, Ga and Cu, or an alloy of
two or more of these metals. Particularly, the solder is formed of
a material having a fusion point of 100.about.300.degree. C., more
preferably, 100.about.200.degree. C. For example, the material
includes BiSnPb, BiPbSn, BiSnCd, Biln, BiPbSnCd, BiSnPbCdCu, InCd,
BiPb, InSn, InSnPbCd, BiPb, PbBiSn, BiSnInPb, InSnPb, BiPbSnAg,
InAg, BiCd, InGa, PbBi, SnAg, InPb, SnZn, SnPbBi, SnPbSb, AuSn, and
SnCu and the like.
[0030] After the sealing process is completed, as shown in FIG. 3E,
devices sealed at a wafer level are sawed into individual chips 45.
Here, dust, particles, or moisture may not stick to the
semiconductor device 12 sealed within the individual chip 45 during
the sawing process.
[0031] FIG. 4 shows a flowchart of the wafer level sealing process
as described above. Individual semiconductor devices 12 are formed
on the wafer 10 (S1). A lid wafer 30 is formed apart from the wafer
10 and adhesives 35 are formed in a predetermined position to bond
the wafer 10 and the lid wafer 30 (S2). The wafer 10 and the lid
wafer 30 are sealed together using the adhesives 35 (S4). The
devices formed at a wafer level are diced into individual chips
(S5). Here, an operation S3 of forming an electrically connective
hole 37 may be further included when the lid wafer 30 is formed in
order to ensure a space necessary for an electrical connection.
[0032] The wafer level hermetic sealing method according to the
present invention can be applied to MEMS devices or chips whose
lives are shortened by a stiction phenomenon due to moisture or
particles, charged coupled devices (CCD) and sensors requiring the
minimization of high temperature, moisture, gas by-products, or
particles. Also, the wafer level hermetic sealing method can be
applied to general semiconductor devices and hybrid chips for
optical communication.
[0033] As described above, in the wafer level hermetic sealing
method according to the present invention, sealing is performed at
a wafer level and thus the overall required processing time is
reduced. It is easier to handle MEMS devices or chips having the
moving structures and production cost is reduced due to the use of
existing dicing processes. Also, in the present invention, sealing
is performed right after the moving structures are formed. Testing
the device and attaching the device to a package are performed in a
sealed state. Therefore, detrimental effects due to dust, particles
or moisture generated during the testing process can be
excluded.
[0034] Also, the hermetic sealing process can be performed at a low
temperature using a solder and thus it can be applied to
semiconductor devices sensitive to heat.
[0035] Although a few preferred embodiments of the present
invention have been shown and described, it would be appreciated by
those skilled in the art that changes may be made in this
embodiment without departing from the principles and spirit of the
invention, the scope of which is defined in the claims and their
equivalents.
* * * * *