U.S. patent application number 11/050010 was filed with the patent office on 2005-07-28 for method and resulting structure for manufacturing semiconductor substrates.
This patent application is currently assigned to Commonwealth Scientific and Industrial Research Organization. Invention is credited to Cunningham, Shaun Joseph.
Application Number | 20050160972 11/050010 |
Document ID | / |
Family ID | 3834720 |
Filed Date | 2005-07-28 |
United States Patent
Application |
20050160972 |
Kind Code |
A1 |
Cunningham, Shaun Joseph |
July 28, 2005 |
Method and resulting structure for manufacturing semiconductor
substrates
Abstract
A semiconductor wafer composite is used as a basis for
fabricating semiconductor chips, especially compound semiconductor
devices. The semiconductor wafer composite advantageously comprises
a metallic substrate 210 and multiple semiconductor tiles 220
bonded to the surface of the metallic substrate 210. The
semiconductor wafer composite is effectively used as a single large
semiconductor wafer for volume fabrication, and can be used to
fabricate semiconductor devices in a similar manner.
Inventors: |
Cunningham, Shaun Joseph;
(New South Wales, AU) |
Correspondence
Address: |
TOWNSEND AND TOWNSEND AND CREW, LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
Commonwealth Scientific and
Industrial Research Organization
Campbell
AU
|
Family ID: |
3834720 |
Appl. No.: |
11/050010 |
Filed: |
February 2, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11050010 |
Feb 2, 2005 |
|
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10389278 |
Mar 13, 2003 |
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Current U.S.
Class: |
117/101 ;
257/E21.51; 257/E21.597; 257/E23.006 |
Current CPC
Class: |
H01L 21/304 20130101;
H01L 2924/01079 20130101; H01L 2924/3025 20130101; H01L 2924/01082
20130101; H01L 2924/0105 20130101; H01L 23/3736 20130101; H01L
2924/01322 20130101; H01L 2224/83801 20130101; H01L 23/142
20130101; H01L 2924/01042 20130101; H01L 2924/01061 20130101; H01L
24/31 20130101; H01L 24/82 20130101; H01L 2924/01033 20130101; H01L
2924/3011 20130101; H01L 23/492 20130101; H01L 2224/18 20130101;
H01L 2924/14 20130101; H01L 21/76898 20130101; H01L 2924/01023
20130101; H01L 24/18 20130101; H01L 24/83 20130101; H01L 2924/01078
20130101; H01L 2924/01006 20130101; H01L 2924/30107 20130101; H01L
23/544 20130101; H01L 2924/01049 20130101; H01L 21/4871 20130101;
H01L 2924/19042 20130101; H01L 2224/8319 20130101; H01L 2924/01005
20130101; H01L 2924/12042 20130101; H01L 21/78 20130101; H01L
2224/92144 20130101; H01L 2924/19043 20130101; H01L 2924/10329
20130101; H01L 2924/30105 20130101; H01L 2224/97 20130101; H01L
24/97 20130101; H01L 2924/01029 20130101; H01L 2924/19041 20130101;
H01L 2924/0132 20130101; H01L 23/552 20130101; H01L 2224/97
20130101; H01L 2224/82 20130101; H01L 2224/97 20130101; H01L
2224/83 20130101; H01L 2924/0132 20130101; H01L 2924/01029
20130101; H01L 2924/01042 20130101; H01L 2924/12042 20130101; H01L
2924/00 20130101 |
Class at
Publication: |
117/101 |
International
Class: |
C30B 023/00; C30B
025/00; C30B 028/12; C30B 028/14 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 14, 2002 |
AU |
PS1122 |
Claims
What is claimed is:
1. A bonded semiconductor wafer composite for fabricating
semiconductor devices, the bonded semiconductor wafer comprising: a
metal support substrate having a first diameter, the metal support
substrate including an upper surface, the upper surface being
substantially planar, the metal support structure being
characterized by a first coefficient of thermal expansion
parameter; a plurality of trapezoidal shaped tiles comprising a
compound semiconductor material, the plurality of trapezoidal
shaped tiles being bonded onto the upper surface of the metal
support substrate, each of the trapezoidal shaped tiles including
at least one edge, the one edge being aligned with an edge of a
different trapezoidal shaped tile, each of the plurality of
trapezoidal shaped tiles being characterized by a second
coefficient of thermal expansion parameter; a eutectic bonding
material coupled between each of the trapezoidal shaped tiles and a
portion of the upper surface of the metal support substrate, the
eutectic bonding material providing a continuous mechanical and
electrical contact between the portion of the upper surface and the
trapezoidal shaped tile; wherein the first coefficient of thermal
expansion parameter is within a predetermined amount of the second
coefficient of thermal expansion parameter, the predetermined
amount being selected to reduce a possibility of breakage of any
portion of any trapezoidal shaped tile bonded to the portion of the
upper surface of the metal substrate from a thermal influence; and
wherein each of the trapezoidal shaped tiles being derived from a
compound semiconductor substrate of a second diameter, the second
diameter being less than the first diameter associated with the
metal substrate; each of the trapezoidal shaped tiles comprising a
predetermined thickness.
2. A semiconductor wafer composite for fabricating a semiconductor
device, the semiconductor wafer composite comprising: a metallic
substrate; and at least one semiconductor tile bonded to the
metallic substrate.
3. The semiconductor wafer composite as claimed in claim 2, wherein
the at least one semiconductor tile is sequentially (i) cut to a
predetermined shape, (ii) thinned, and (iii) bonded to the metallic
substrate.
4. The semiconductor wafer composite as claimed in claim 2, wherein
the at least one semiconductor tile is sequentially (i) thinned,
(ii) cut to a predetermined shape, and (iii) bonded to the metallic
substrate.
5. The semiconductor wafer composite as claimed in claim 2, wherein
the at least one semiconductor tile is sequentially (i) cut to a
predetermined shape, (ii) bonded to the metallic substrate, and
(iii) thinned.
6. The semiconductor wafer composite as claimed in claim 2, wherein
connections are formed between semiconductor devices on a
front-side surface of the at least one semiconductor tile and the
metallic substrate by etching apertures in semiconductor material
from a front-side of the at least one semiconductor tile and
patterning a metal layer across the resulting front-side surface
and aperture walls.
7. The semiconductor wafer composite as claimed in claim 6, wherein
semiconductor material is removed from the at least one
semiconductor tile to form elongated trenches arranged to form
perimeters around portions of a surface of the at least one
semiconductor tile.
8. The semiconductor wafer composite as claimed in claim 2, wherein
the semiconductor wafer composite is diced to form individual
integrated circuits having metallic substrates.
9. The semiconductor wafer composite as claimed in claim 2, wherein
the metallic substrate comprises a metallic base layer, and a
bonding layer to which the at least one semiconductor tile is
bonded.
10. The semiconductor wafer composite as claimed in claim 2,
wherein the metallic substrate further comprises an inert coating
layer that substantially covers at least part of the metallic base
layer and/or the bonding layer.
11. The semiconductor wafer composite as claimed in claim 2,
wherein the at least one semiconductor tile comprises a compound
semiconductor.
12. The semiconductor wafer composite as claimed in claim 11,
wherein the at least one semiconductor tile further comprises a
complementary bonding layer suitable for adhering to the metallic
substrate.
13. The semiconductor wafer composite as claimed in claim 12,
wherein the complementary bonding layer is predominantly formed of
one or more metals, one of which is a noble metal.
14. The semiconductor wafer composite as claimed in claim 9,
wherein the bonding layer is predominantly formed of two or more
metals that form a eutectic alloy when heated.
15. The semiconductor wafer composite as claimed in claim 10,
wherein the inert coating layer is predominantly formed of a noble
metal.
16. The semiconductor wafer composite as claimed in claim 2,
wherein the metallic substrate and the at least one semiconductor
tile have respective coefficients of thermal expansion that are
substantially similar values.
17. The semiconductor wafer composite as claimed in claim 2,
wherein the at least one semiconductor tile has a substantially
rectangular or square shape.
18. A method of manufacturing a semiconductor wafer composite for
fabricating a semiconductor device, the method comprising:
providing a metallic substrate; and bonding at least one
semiconductor tile to the metallic substrate.
19. The method as claimed in claim 18, further comprising
sequentially (i) cutting the at least one semiconductor tile to a
predetermined shape, (ii) thinning the at least one semiconductor
tile, and (iii) bonding the at least one semiconductor tile to the
metallic substrate.
20. The method as claimed in claim 18, further comprising
sequentially (i) thinning the at least one semiconductor tile, (ii)
cutting the at least one semiconductor tile to a predetermined
shape, and (iii) bonding the at least one semiconductor tile to the
metallic substrate.
21. The method as claimed in claim 18, further comprising
sequentially (i) cutting the at least one semiconductor tile to a
predetermined shape, (ii) bonding the at least one semiconductor
tile to the metallic substrate, and (iii) thinning the at least one
semiconductor tile.
22. The method as claimed in claim 18, further comprising the steps
of: forming connections between semiconductor devices on a
front-side surface of the at least one semiconductor tile and the
metallic substrate by etching apertures in semiconductor material
from a front-side of the at least one semiconductor tile; and
patterning a metal layer across the resulting front-side surface
and aperture walls.
23. The method as claimed in claim 22, further comprising removing
semiconductor material from the at least one semiconductor tile to
form elongated trenches arranged to form perimeters around portions
of the surface of the at least one semiconductor tile.
24. The method as claimed in claim 18, further comprising dicing
the semiconductor wafer composite to form individual integrated
circuits having metallic substrates.
25. The method as claimed in claim 18, further comprising forming
the metallic substrate from a metallic base layer, and a bonding
layer to which the at least one semiconductor tile is bonded.
26. The method as claimed in claim 18, further comprising
substantially covering at least part of the metallic base layer
and/or the bonding layer with an inert coating layer.
27. The method as claimed in claim 18, further comprising forming
the at least one semiconductor tile with a working layer
predominantly of a compound semiconductor.
28. The method as claimed in claim 18, further comprising forming
the at least one semiconductor tile with a complementary bonding
layer suitable for adhering the at least one semiconductor tile to
the metallic substrate.
29. The method as claimed in claim 28, further comprising forming
the complementary bonding layer predominantly of one or more
metals, one of which is a noble metal.
30. The method as claimed in claim 25, further comprising forming
the bonding layer predominantly of two or more metals that form a
eutectic alloy when heated.
31. The method as claimed in claim 28, further comprising forming
the inert coating layer predominantly of a noble metal.
32. The method as claimed in claim 18, further comprising matching
respective coefficients of thermal expansion of the at least one
semiconductor tile and the metallic substrate to substantially
similar values.
33. The method as claimed in claim 18, further comprising of
cutting a semiconductor wafer to a substantially rectangular or
square shape to form the at least one semiconductor tile.
34. A semiconductor wafer composite for fabricating a semiconductor
device, the semiconductor wafer composite manufactured by a process
comprising the steps of: providing a metallic substrate; and
bonding at least one semiconductor tile to the metallic
substrate.
35. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises sequentially (i) cutting the
at least one semiconductor tile to a predetermined shape, (ii)
thinning the at least one semiconductor tile, and (iii) bonding the
at least one semiconductor tile to the metallic substrate.
36. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises sequentially (i) thinning the
at least one semiconductor tile, (ii) cutting the at least one
semiconductor tile to a predetermined shape, and (iii) bonding the
at least one semiconductor tile to the metallic substrate.
37. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises sequentially (i) cutting the
at least one semiconductor tile to a predetermined shape, (ii)
bonding the at least one semiconductor-tile to the metallic
substrate, and (iii) thinning the at least one semiconductor
tile.
38. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises: forming connections between
semiconductor devices on a front-side surface of the at least one
semiconductor tile and the metallic substrate by etching apertures
in semiconductor material from a front-side of the at least one
semiconductor tile; and patterning a metal layer across the
resulting front-side surface and aperture walls.
39. The semiconductor wafer composite as claimed in claim 38,
wherein the process further comprises removing semiconductor
material from the at least one semiconductor tile to form elongated
trenches arranged to form perimeters around portions of the surface
of the at least one semiconductor tile.
40. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises dicing the semiconductor
wafer composite to form individual integrated circuits having
metallic substrates.
41. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises forming the metallic
substrate from a metallic base layer, and a bonding layer to which
the at least one semiconductor tile is bonded.
42. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises substantially covering at
least part of the metallic base layer and/or the bonding layer with
an inert coating layer.
43. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises forming the at least one
semiconductor tile with a working layer predominantly of a compound
semiconductor.
44. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises forming the at least one
semiconductor tile with a complementary bonding layer suitable for
adhering the at least one semiconductor tile to the metallic
substrate.
45. The semiconductor wafer composite as claimed in claim 44,
wherein the process further comprises forming the complementary
bonding layer predominantly of one or more metals, one of which is
a noble metal.
46. The semiconductor wafer composite as claimed in claim 41,
wherein the process further comprises forming the bonding layer
predominantly of two or more metals that form a eutectic alloy when
heated.
47. The semiconductor wafer composite as claimed in claim 42,
wherein the process further comprises forming the inert coating
layer predominantly of a noble metal.
48. The semiconductor wafer composite as claimed in claim 34,
wherein the process further comprises matching respective
coefficients of thermal expansion of the at least one semiconductor
tile and the metallic substrate to substantially similar
values.
49. The method as claimed in claim 34, wherein the process further
comprises cutting a semiconductor wafer to a substantially
rectangular or square shape to form the at least one semiconductor
tile.
50. A semiconductor wafer composite suitable for fabricating a
semiconductor device, the semiconductor wafer composite comprising:
a metallic substrate comprising (i) a base metallic layer, (ii) a
metallic bonding layer predominantly formed of two or metals that
form a euctectic alloy when heated, and (iii) an inert coating
layer predominantly formed of a noble metal; and multiple
semiconductor tiles bonded to the metallic substrate by heating the
semiconductor tiles and the metallic substrate when the
semiconductor tiles and the metallic substrate are in physical
contact, so that the semiconductor tiles bond to the metallic
bonding layer via the inert coating layer.
51. A packaged compound semiconductor integrated circuit device
comprising: a compound semiconductor substrate comprising a
backside surface; a metal substrate bonded to the backside surface,
the metal substrate providing mechanical support for the compound
semiconductor substrate before being packaged; and a support
substrate coupled to the metal substrate for packaging.
Description
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application claims priority to Australian Provisional
Patent Application No. PS1122 filed Mar. 14, 2002, commonly
assigned, and hereby incorporated by references for all
purposes.
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED
RESEARCH OR DEVELOPMENT BACKGROUND OF THE INVENTION
[0002] The present invention relates generally to manufacturing
substrates. More particularly, the invention provides a method and
device for improved semiconductor substrates to form advanced
semiconductor devices. Merely by way of example, the invention has
been applied to a metallic substrate that includes a plurality of
panels and/or tiles, which are bonded on the substrate, for the
manufacture of the advanced semiconductor devices. But it would be
recognized that the invention has a much broader range of
applicability.
[0003] As technology progresses, semiconductor manufacturers have
continually strived to use ever larger wafers to obtain economies
of scale, and consequently lower the cost of individual
semiconductor devices. Commonly, silicon crystal boules can be
readily grown large enough to slice into 12 inch diameter wafers.
The 12 inch wafers have been produced for single crystal silicon
materials for a variety of applications. Although the single
crystal silicon has many benefits, there are still numerous
disadvantages.
[0004] Many conventional industries have been increasingly reliant
on compound semiconductor devices fabricated from compound
semiconductors such as gallium arsenide, indium phosphide, and
gallium nitride. Unfortunately, integrated circuits made from these
semiconducting compounds are still relatively expensive compared to
circuits made from silicon semiconductors. This cost difference is
largely attributable to the respective material costs, and wafer
processing costs. Other limitations also exist with compound
semiconductor materials.
[0005] Compound semiconductor wafers are more prone to damage. For
example, they are more brittle than conventional single crystal
silicon wafers. Growing large crystal boules of compound
semiconductor material is extremely difficult compared with growing
large single crystal silicon boules. The maximum diameters for
commercially-produced compound semiconductor wafers of gallium
arsenide, indium phosphide and gallium nitride are respectively six
inches, four inches and two inches in conventional commercial
applications.
[0006] Larger compound semiconductor wafers would be desirable.
Unfortunately, larger diameter wafers are difficult to make
efficiently. Even if larger boules of compound semiconductor
material could be produced, handling the resulting large-diameter
compound semiconductor wafers would generally be problematic.
Compound semiconductor wafers of the desired thickness and diameter
would be extremely fragile and prone to breakage. Here, the larger
wafers would generally break due to the brittle nature of these
semiconductor compounds. Accordingly, certain techniques have been
proposed to manufacture larger compound semiconductor wafers using
an epitaxial grown layer.
[0007] As merely an example, a conventional process for fabricating
compound semiconductor chips could be outlined in steps (i) to
(vii) listed below.
[0008] (i) Grow epitaxial device layers on mono-crystalline
substrate.
[0009] (ii) Pattern these epitaxial layers and other deposited
dielectric and metallic layers using photolithographic
techniques.
[0010] (iii) Bond wafers face-down to a temporary supporting
substrate after front-side process is complete.
[0011] (iv) Thin wafers by mechanical grinding or lapping
back-side.
[0012] (v) Create "via holes" in the substrate, which provide a
means for connecting the back-side ground to appropriate front-side
ground connections.
[0013] (vi) Deposit a metal film on the wafer's back-side to
provide a ground plane, and coat the walls of the via holes,
thereby making contact with the front-side ground connections.
[0014] (vii) Dice wafer into individual chips.
[0015] In the above conventional process, wafers are typically 625
.mu.m in thickness during steps (i), (ii) and (iii), and have
sufficient mechanical strength to avoid breakage with careful
handling. Wafers are typically thinned to around 50 to 100 .mu.m in
thickness in step (iv). Thinning wafers has numerous advantages,
which relate to:
[0016] (i) reducing the depth (and also the size) of via holes, as
well as parasitic inductance associated with the via holes;
[0017] (ii) conducting heat away from front-side devices towards
the back-side, which is normally attached to a heat sink; and
[0018] (iii) preventing electromagnetic resonance in the substrate
at high frequencies.
[0019] Handling thinned compound semiconductor wafers is often
difficult, and compound semiconductor wafers are commonly broken
from step (iv) onwards. Breakage is costly, since most of the
processing (steps (i) to (iii)) is already complete. The fragility
of compound semiconductor materials also causes breakages of
resulting chip devices, and restricts the larger size of practical
chip designs that use compound semiconductor materials. Here,
larger sized compound semiconductor materials are not practical to
make efficiently.
[0020] In view of the above, a need exists for improved techniques
for producing and handling semiconductor wafers. In particular, a
need exists for techniques suitable for assisting practical and
cost-effective production of compound semiconductor devices.
BRIEF SUMMARY OF THE INVENTION
[0021] According to the present invention, techniques for
manufacturing substrates are provided. More particularly, the
invention provides a method and device for improved semiconductor
substrates to form advanced semiconductor devices. Merely by way of
example, the invention has been applied to a metallic substrate
that includes a plurality of panels and/or tiles, which are bonded
on the substrate, for the manufacture of the advanced semiconductor
devices. But, it would be recognized that the invention has a much
broader range of applicability.
[0022] Described herein are techniques for producing a
semiconductor wafer composite from which semiconductor chips can be
fabricated. The semiconductor wafer composite comprises a metallic
substrate and one or more semiconductor "tiles" bonded to the
surface of the metallic substrate. These semiconductor tiles are
formed by cutting a semiconductor wafer to a desired shape, as
later described. The described techniques find particular
application in fabricating compound semiconductor devices, but are
also more broadly applicable to all types of semiconductor
wafers.
[0023] Multiple wafer tiles are advantageously bonded to the
metallic substrate before any front-side processing. The metallic
substrate desirably remains attached to the semiconductor material
when the composite is divided into individual chips. The
semiconductor wafer composite is effectively used as a single large
semiconductor wafer, and can be used to fabricate semiconductor
devices in a similar manner. By way of the metal substrate, the
composite is more durable and efficient.
[0024] The semiconductor tiles are advantageously square or
rectangular, or one or more other shapes able to be conveniently
tessellated on the metallic substrate to efficiently cover the
surface of the metallic substrate. These shapes are conventionally
cut from the standard "clipped-circular" wafer shape.
[0025] In a specific embodiment, the invention provides a packaged
compound semiconductor integrated circuit device. The packaged
device includes a compound semiconductor substrate comprising a
backside surface. The device has a metal substrate bonded to the
backside surface. The metal substrate provides mechanical support
for the compound semiconductor substrate before being packaged. The
metal support allows the compound semiconductor to be handled. The
compound semiconductor has a predetermined size that is larger than
a size that would be damaged if it was free from the metal support
according to preferred embodiments. Here, the large size would be
too large for efficient handling without the support structure. A
support substrate is coupled to the metal substrate for
packaging.
[0026] In a further alternative embodiment, the invention provides
a bonded semiconductor wafer composite for fabricating
semiconductor devices. The bonded semiconductor wafer has a metal
support substrate. The metal substrate has a first diameter and an
upper surface, which is substantially planar. The metal support
structure is characterized by a first coefficient of thermal
expansion parameter. The wafer also has a plurality of trapezoidal
shaped tiles comprising a compound semiconductor material. The
plurality of trapezoidal shaped tiles are bonded onto the upper
surface of the metal support substrate. Each of the trapezoidal
shaped tiles includes at least one edge, which is aligned with an
edge of a different trapezoidal shaped tile. Each of the plurality
of trapezoidal shaped tiles is characterized by a second
coefficient of thermal expansion parameter. A eutectic bonding
material is coupled between each of the trapezoidal shaped tiles
and a portion of the upper surface of the metal support substrate.
The eutectic bonding material provides a continuous mechanical and
electrical contact between the portion of the upper surface and the
trapezoidal shaped tile. The first coefficient of thermal expansion
parameter is within a predetermined amount of the second
coefficient of thermal expansion parameter. The predetermined
amount is selected to reduce a possibility of breakage of any
portion of any trapezoidal shaped tile bonded to the portion of the
upper surface of the metal substrate from a thermal influence,
e.g., contraction, expansion. Each of the trapezoidal shaped tiles
is derived from a compound semiconductor substrate of a second
diameter, which is less than the first diameter associated with the
metal substrate. Each of the trapezoidal shaped tiles comprises a
predetermined thickness.
[0027] Various advantages can be achieved through use of a
semiconductor tile bonded to a metallic substrate. The
semiconductor wafer composite is less fragile than the
semiconductor tile, and can thus be handled in larger areas. As a
result, cost savings can be achieved through larger volume
fabrication.
[0028] In particular, compound semiconductor wafers that have been
hitherto produced from smaller diameter wafers can be processed in
any effective size through the use of multiple semiconductor tiles.
Consequently, existing fabrication equipment for treating 12 inch
diameter silicon wafers can be used to fabricate compound
semiconductor devices using the described semiconductor wafer
composite.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] FIG. 1 is a simplified schematic representation of a view,
from above, of a semiconductor wafer composite comprising a
circular metallic substrate on which four square semiconductor
tiles are bonded according to an embodiment of the present
invention.
[0030] FIG. 2 is a simplified cross-sectional view corresponding
with FIG. 1.
[0031] FIG. 3 is a simplified flowchart of a method involved in
fabricating semiconductor chips from the semiconductor wafer
composite of FIGS. 1 and 2 according to an embodiment of the
present invention
DETAILED DESCRIPTION OF THE INVENTION
[0032] According to the present invention, techniques for
manufacturing substrates are provided. More particularly, the
invention provides a method and device for improved semiconductor
substrates to form advanced semiconductor devices. Merely by way of
example, the invention has been applied to a metallic substrate
that includes a plurality of panels and/or tiles, which are bonded
on the substrate, for the manufacture of the advanced semiconductor
devices. But it would be recognized that the invention has a much
broader range of applicability.
[0033] A semiconductor wafer composite is described herein. The
composite is well suited to fabrication of compound semiconductor
devices. Further, the composite has particular application in the
context of large scale production of such devices. The
semiconductor wafer composite from which the individual
semiconductor devices are fabricated is first described, followed
by a procedure for high volume production of semiconductor devices
using the described semiconductor wafer composite.
[0034] FIGS. 1 and 2 schematically represent a simplified
semiconductor wafer composite, using top and side views
respectively according to an embodiment of the present invention.
This diagram is merely an example, which should not unduly limit
the scope of the claims herein. One of ordinary skill in the art
would recognize many variations, modifications, and alternatives.
The semiconductor wafer composite effectively replaces existing
semiconductor wafers from which semiconductor chip devices are
fabricated.
[0035] The described semiconductor wafer composite represented in
FIGS. 1 and 2 comprises a metallic substrate 210 upon which is
bonded a number of semiconductor tiles 220.
[0036] FIG. 1 represents the metallic substrate 210 as circular in
shape, and represents four abutting rectangular semiconductor tiles
220. The four rectangular shapes shown in dotted outline represent
further rectangular semiconductor tiles 220 that may be bonded to
the metallic substrate 210 near the periphery of the metallic
substrate 210, to more efficiently use the surface of the metallic
substrate 210. The substrate is preferably made from materials
which have good electrical and thermal conductivity and whose
coefficient of thermal expansion matches that of the semiconductor
tiles. For example, CuMo, AlSi and Mo are suitable materials.
Preferably, the substrate is highly conductive with resistivity in
the range 1 to 10 micro ohm centimeters (1-10.times.10.sup.-6
ohm-cm) according to a specific embodiment. Alternatively, the
material can be semiconductor according to other embodiments. The
tiles 220 are closely placed together, through perhaps not directly
abutting. A slight spacing between wafer tiles 220 eases tile
dimension accuracy requirements and allows for slight thermal
expansion gaps, if desirable. Indicative gap dimensions may be, for
example, less than 5 .mu.m. Preferably, each of the tiles should
have a slight gap to separate them from each other to account for
any differences in tolerances. Alternatively, the tiles are
abutting each other to prevent or reduce impurities (e.g.,
photoresist) from entering regions between the tiles according to
other embodiments.
[0037] FIG. 2 is a side view that corresponds with FIG. 1. The
peripheral semiconductor tiles 220 depicted in dotted outline in
FIG. 1 are not represented in FIG. 2. The metallic substrate 210
comprises a metallic base layer 240, upon which is formed a
metallic bonding layer 250. The metallic base layer 240 may be
formed of a suitable metal or alloys that matches the coefficient
of thermal expansion (CTE) of the compound semiconductor material.
For a gallium arsenide (GaAs) compound semiconductor tile 220, a
suitable choice of metallic substrate 210 is copper molybdenum
(CuMo). The metallic bonding layer 250 is desirably formed of tin
(Sn) or indium (In) and gold (Au), or other suitable metals having
a relatively low melting point, and which form a eutectic alloy
upon heating. In preferred embodiments, the eutectic alloy is
provided purely from compression and free from relative lateral
movement between the tile and substrate.
[0038] The semiconductor tiles 220 comprise a working layer 260 of
compound semiconductor material (such as gallium arsenide (GaAs)),
and a complementary bonding layer 270 preferably formed of a
material that assists the semiconductor tile 220 to adhere to the
metallic substrate 210. A suitable material is a combination of
titanium (Ti) and gold (Au).
[0039] Surrounding the metallic base layer 240 and metallic bonding
layer 250 is a thin metallic coating layer 290, formed of a noble
metal. Gold (Au) or platinum (Pt) is preferably used. The coating
layer 290 seals the metallic substrate 210 from damage during
subsequent fabrication of semiconductor devices from the
semiconductor wafer composite. The coating layer 290 can be applied
by evaporation/deposition techniques, or by electroplating, for
example.
[0040] While components of the semiconductor wafer composite are
described above with reference to FIGS. 1 and 2, various other
associated features and advantages of the semiconductor wafer
composite are described below with reference to a process for
manufacturing the semiconductor wafer composite. This manufacturing
process is described herein with reference to steps 310 to 330 of
FIG. 3. Remaining steps 340 to 370 of FIG. 3 describe subsequent
steps in fabricating semiconductor devices from the semiconductor
wafer composite.
[0041] In a specific embodiment, each of the tiles has a specific
size and shape. The metal substrate also has a desired shape and
size. That is, the metal substrate has a diameter "dm", which is
chosen according to the capabilities of the intended wafer
processing equipment. This dimension is preferably selected from a
set of industry diameters, e.g., 2 inch, 3 inch, 4 inch, 5 inch, 6
inch, 8 inch, 12 inch. The substrate is shaped to provide a "flat"
on one part of the circumference that acts as an alignment
reference, which is similar to conventional wafers.
[0042] Further, the substrate may be patterned to provide apertures
which aid packaging operations or which facilitate the coupling of
signals off chip. For example, the apertures may be used to form
slots which radiate high frequency signals off chip.
[0043] The tiles would be cut from circular compound semiconductor
wafers of radius "ds" where an integral number of wafer diameters
"ds" equate to the metal substrate diameter "dm" ie dm=n.times.ds
where n is the smallest possible integer. This relationship ensures
the least number of tiles and minimum wastage of expensive compound
semiconductor material in cutting tiles to the appropriate shape.
For example, four square tiles with 3 inch diagonal dimensions
could be cut from 3 inch semiconductor wafers to cover a six inch
metallic substrate in a 2.times.2 tile array. If only 2 inch
diameter semiconductor wafers were available, nine square tiles
with 2 inch diagonals could be prepared to cover a six inch
substrate in a 3.times.3 array. Of course, there would be various
modifications, alternatives, and variations.
[0044] Although the semiconductor wafer described above is
illustrated using a specific embodiment, there can be many
variations, alternatives, and modifications. For example, the metal
substrate can be made of an alloy or other material, as well as
other multilayered materials and the like, which have desirable
electrical and thermal characteristics. The metal substrate can
also be multi-layered, depending upon the application.
Additionally, one or more of the tiles can be made of a different
material on the substrate. These and other variations can be found
throughout the present specification and more particularly
below.
[0045] In a specific embodiment, a method for fabricating compound
semiconductor devices involves, in overview, the steps listed below
in Table 1. FIG. 3 flowcharts these steps, which are described in
further detail below.
1 TABLE 1 Step 310 Multiple semiconductor wafers are thinned 220.
Step 320 The wafers 220 are cut to form semiconductor tiles. Step
330 The semiconductor tiles 220 are bonded to the metallic
substrate 210. Step 340 Standard front-side processing techniques
are used to fabricate devices. Step 350 Via holes are opened from
the front-side to the metallic substrate 210. Step 360 Via holes
are metalized to make ground connections to the metallic substrate
210. Step 370 The metallic substrate 210 is cut to separate
individual chips.
[0046] As shown above, the above steps are merely illustrative.
Depending upon the embodiment, certain steps can be further
separated or even combined with other steps. Additional steps can
be added depending upon the embodiment. Other steps can replace
certain steps above. Accordingly, there can be many variations,
modifications, and alternatives. Further details of each the steps
can be found throughout the present specification and more
particularly below.
[0047] Thinning Semiconductor Tiles--Step 310
[0048] Individual wafer tiles 220 are thinned according to existing
processing techniques. If the wafers break at this point, the
associated cost is relatively low since the front side of the
semiconductor tile 220 has not been processed. According to a
specific embodiment, tiles are thinned using a lapping/grinding
and/or polishing operation. The tiles can be thinned to a thickness
of about 50 to 100 microns according to certain embodiments.
According to a specific embodiment, tiles are thinned using a
lapping /grinding and/or polishing operation.
[0049] Forming Semiconductor Tiles--Step 320
[0050] Semiconductor wafers are cut to form semiconductor tiles
220. Preferably, each of the tiles is provided using a scribing and
breaking process. More preferably, scribing can be provided via a
diamond stylus, laser cutting, or the like. These are preferably
"standard" wafers that have epitaxial layers grown on their front
side and are ready for device fabrication. The semiconductor tiles
220 are shaped such that these semiconductor tiles 220 can cover a
planar surface with minimal intervening gaps. According to a
specific embodiment, each of the tiles is formed along a
crystalline plane, which provides an accurate shape and form. Such
accurate shape and form allows for alignment between each of the
tiles to reduce a possibility of gaps between each of the tiles.
This also subsequently enables all tiles to be arranged on the
metallic substrate with the same crystal orientation.
[0051] Bonding Tiles to Substrate--Step 330
[0052] A metallic substrate material is chosen to match the
coefficient of thermal expansion (CTE) of the chosen semiconductor
over the required range of processing temperatures. The substrate
material is also chosen for its strength, thermal and electrical
conductivity and cost. Preferably, the substrate also has a high
thermal conductivity to carry away heat from an integrated device
formed thereon. According to certain embodiments, the thermal
conductivity of the metallic substrate can be 165 Watts/m-Kelvin or
greater.
[0053] For example, an alloy of approximately 80% molybdenum and
20% copper matches the CTE of gallium arsenide and has suitable
electrical and thermal conductivity. An advantage of using a
metallic substrate 210 is that the CTE can be adjusted by changing
the composition of the metal alloy. No such adjustment is possible
if a crystalline substrate such as silicon is used.
[0054] The metallic substrate 210 is polished on one face and its
perimeter is shaped to suit large diameter wafer processing
equipment. Preferably, polishing reduces a possibility of air gaps
forming between the surface of the substrate and the tiles. The
metallic substrate has a surface roughness no greater than a
predetermined amount and a uniformity of less than a certain amount
across the substrate in certain embodiments to facilitate the
bonding process. According to certain embodiments, the surface can
also include a series of patterns and/or textures, which prevent
the formation of air bubbles, etc. and enhance the bonding process.
This typically means the metallic substrate 210 is circular in
shape (as represented in FIGS. 1 and 2). A minor flat on one side
can be provided, for compatibility with existing wafer processing
equipment.
[0055] The metallic substrate 210 is preferably made as thin as
possible so as not to increase the weight or heat capacity of the
composite structure. A typical thickness might be in the range 200
.mu.m to 400 .mu.m.
[0056] An inert coating layer 290 is then deposited on the metallic
substrate 210 if there is a risk that the substrate 210 might be
effected by subsequent semiconductor process chemistry. A thin
layer (typically less than 1 .mu.m in thickness) of a noble metal
such as gold or platinum is generally suitable for this purpose.
Preferably, the coating is non-reactive with subsequent
semiconductor processing steps. Other materials (such as silicon
nitride) can also be used, provided such materials have sufficient
resistance to process chemistry and temperatures used in the
intended wafer processing steps.
[0057] The bonding layer 250 is deposited on the polished surface
of the metallic substrate 210. This metallic bonding layer 250 is
preferably made from two or more metals that form a eutectic alloy
on heating. The outermost layer is preferably a noble metal (such
as gold) that prevents the underlying layers from oxidising before
and during bonding. Underlying layers may be formed of tin or
indium. These metals are chosen such that the eutectic alloy forms
at relatively low temperature (for example, 200 Degrees Celsius)
and having formed, does not melt at the elevated temperatures
encountered during wafer processing. The bonding layer may also
serve as the inert coating layer for the metallic substrate.
[0058] A complementary bonding layer 270 is also deposited on the
back-side of each thinned semiconductor wafer tile 220. This
complementary bonding layer 270 is also preferably metallic and its
composition is chosen to provide maximum adhesion to the
semiconductor tile 220 over the range of subsequent processing
temperatures. The preferred layer structures are titanium/gold or
titanium/platinum/gold, but many other combinations of metals are
possible without departing from the scope and spirit of the
invention.
[0059] Numerous other bonding layer compositions are possible, and
may be chosen to match particular processing requirements (such as
maximum temperature) of different semiconductor materials.
[0060] The use of metallic bonding layers offers the advantage of
allowing bonding to occur at relatively low temperatures (for
example, 200.degree.). This ensures the epitaxial layer structure
of the wafer tiles 220 is not degraded. Non-metallic complementary
bonding layers 290 such as silicon, polysilicon, silicon dioxide or
silicon nitride may also be used.
[0061] Large gaps between semiconductor tiles 220 are desirably
avoided as such gaps may adversely affect the spin-deposition of
photoresist. The semiconductor tiles 220 are preferably square or
rectangular in shape. Such shapes allow arrays of rectangular chips
to be efficiently contained inside the semiconductor tiles 220, and
also allows semiconductor tiles 220 to be cut by scribing and
breaking along crystal planes, which are typically rectangular.
[0062] However, other tile shapes may also be used. Hexagonal
tiles, for example, may cover the surface of a circular substrate
210 more efficiently than rectangular tiles. The preferred
embodiment uses a set of non-uniform square or rectangular tiles as
represented in FIG. 1. The selected pattern semiconductor tiles 220
depends on the size of the available semiconductor wafers, and the
size of the metallic substrate 210.
[0063] The semiconductor tiles 220 are positioned on top of the
polished surface of the metallic substrate 210, such that the
semiconductor tiles 220 preferably abut each other (or are closely
spaced together) to form a substantially continuous semiconductor
surface. Small gaps (for example, of less than 5 .mu.m) may be
advantageous for the reasons noted above. The semiconductor tiles
220 are arranged to ensure a common crystal axis orientation. The
semiconductor tiles 220 and metallic substrate 210 are then
subjected to a compressive force at elevated temperature, which
causes a eutectic alloy to form and permanently bond the
semiconductor tiles 220 to the metallic substrate 210.
[0064] In a specific embodiment, bonding occurs by placing each of
the tiles overlying the metal substrate. A bonding layer such as
those described herein as well as others is also provided. Bonding
occurs using mechanical force between each of the tiles and the
substrate to compress the bonding layer. Heating is also provided.
In a specific embodiment, heating and pressure (normal to the
surface of the tiles and substrate) is applied, while maintaining
each of the tiles free from lateral movement with respect to the
substrate to form, for example, a eutectic bonding layer between
each of the tiles and the metal substrate. Of course, there can be
many variations, alternatives, and modifications.
[0065] Front-Side Processing of Composite--Step 340
[0066] The front-side of the composite wafer is now processed
according to standard semiconductor fabrication techniques.
Fiducial alignment marks are provided on each tile 220, to allow
for slight misalignments between semiconductor tiles 220.
Individual chips are preferably arranged on the semiconductor tiles
220, such that the chips are wholly contained within tiles 220 and
do not span semiconductor tile boundaries.
[0067] Opening Via Holes--Step 350
[0068] Unlike existing semiconductor processes, which create via
holes from the back-side of a wafer toward the front-side, via
holes can be made from the front side toward the metallic substrate
210. The alignment of via holes is thus simplified as this
alignment is relative to other visible front-side features.
[0069] Metallizing Via Holes--Step 360
[0070] The presence of the metallic substrate 210 allows large
areas of the semiconductor tiles 220 to be removed in the via hole
process without compromising the structural strength of the
composite wafer. This means that via hole "trenches" can be formed
on the semiconductor tiles 220. These trenches are able to provide
the following features:
[0071] (i) relatively low inductance ground connections compared to
ordinary round vias;
[0072] (ii) electromagnetic screening between adjacent circuits,
which is important as circuit densities increase;
[0073] (iii) chip separation outlines; and
[0074] (iv) contouring of the semiconductor wafer to achieve
localized heat spreading features.
[0075] Cutting into Individual Devices--Step 370
[0076] The individual chips are separated by cutting the metallic
substrate 210 either from the front-side or back-side depending on
the capabilities of the process machinery.
[0077] Since each chip is supported by a portion of the metallic
substrate 210, chip breakage is reduced during handling. Also,
larger chips may be fabricated. As a result, more functions/systems
may be integrated on a single chip. Such chips offer considerable
cost savings by simplifying engineering and production
requirements.
[0078] The presence of the metallic substrate 210 on each chip also
serves as a heat spreader, which is advantageous in high power
applications.
[0079] Further Variations
[0080] One variation of the above-described fabrication procedure
is to bond un-thinned wafer tiles 220 to the metallic substrate
210. The semiconductor tiles 220 may be subsequently thinned when
bonded to the metallic substrate 210. This variation provides the
advantages of "planarising" the semiconductor surface of the wafer
composite during the thinning process. The epitaxial device layers
are, as a consequence, grown on the wafer composite.
[0081] This revised procedure may provide economic benefits in
certain circumstances. Further, handling requirements of wafer
tiles 220 before bonding are relaxed as the semiconductor tiles 220
are of greater thickness at this stage.
[0082] A metallic bonding layer 250 is described herein, though
other techniques may be used to affix the semiconductor tiles 220
to a metallic substrate 210. For example, adhesives adapted to the
temperature and chemical processing conditions involved in
semiconductor fabrication may be used to adhere semiconductor tiles
220 to a metallic substrate 210.
[0083] The techniques described herein are suitable for
manufacturing semiconductor devices including those using composite
semiconductors large-diameter composite metallic substrates. As
well as other benefits described herein, the described techniques
potentially offer improved radio frequency performance, improved
yield and lower costs through economies of scale.
[0084] Various alterations, modifications and substitutions can be
made to the arrangements and techniques described herein, as would
be apparent to one skilled in the relevant art in the light of this
disclosure without departing form the scope and spirit of this
invention.
* * * * *