U.S. patent application number 11/067958 was filed with the patent office on 2005-07-21 for marks and method for multi-layer alignment.
This patent application is currently assigned to NANYA TECHNOLOGY CORPORATION. Invention is credited to Chen, Feng-Yi.
Application Number | 20050156335 11/067958 |
Document ID | / |
Family ID | 32228173 |
Filed Date | 2005-07-21 |
United States Patent
Application |
20050156335 |
Kind Code |
A1 |
Chen, Feng-Yi |
July 21, 2005 |
Marks and method for multi-layer alignment
Abstract
Marks and a method for multi-layer alignment. A first layer with
first alignment marks is formed on a semiconductor substrate,
wherein the first alignment marks are separated parallelly by a
predetermined distance. A second layer with second alignment marks
is formed on the first layer, wherein the second alignment marks
are separated parallelly by a predetermined distance. The shift
distance of each first alignment mark is measured to calculate a
first midpoint between the first alignments. The shift distance of
each second alignment mark is measured to calculate a second
midpoint between the second alignments. A third midpoint acting as
a datum point between the fist midpoint and the second midpoint is
calculated.
Inventors: |
Chen, Feng-Yi; (Taichung,
TW) |
Correspondence
Address: |
QUINTERO LAW OFFICE
1617 BROADWAY, 3RD FLOOR
SANTA MONICA
CA
90404
US
|
Assignee: |
NANYA TECHNOLOGY
CORPORATION
TAOYUAN
TW
|
Family ID: |
32228173 |
Appl. No.: |
11/067958 |
Filed: |
February 28, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11067958 |
Feb 28, 2005 |
|
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10684108 |
Oct 10, 2003 |
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Current U.S.
Class: |
257/797 ;
257/E23.179 |
Current CPC
Class: |
H01L 2223/54453
20130101; H01L 23/544 20130101; H01L 2924/0002 20130101; H01L
2223/5448 20130101; G03F 9/7076 20130101; H01L 2924/00 20130101;
H01L 2924/0002 20130101 |
Class at
Publication: |
257/797 |
International
Class: |
H01L 021/76 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 8, 2002 |
TW |
TW91132929 |
Claims
1-4. (canceled)
5. A marks for multi-layer alignment of a semiconductor substrate,
comprising: a first layer with first alignment marks, wherein the
first alignment marks are separated parallelly by a predetermined
distance; and a second layer with second alignment marks, wherein
the second alignment marks are separated parallelly by a
predetermined distance, the second alignment marks and the first
alignment marks are alternately disposed, and overlap completely.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to an alignment mark and alignment
method using the same, and more particularly to marks and method
for multi-layer alignment.
[0003] 2. Description of the Related Art
[0004] Electronic elements, such as MOS or capacitors, are
fabricated using integrated circuit fabrication comprising
deposition, photolithography, etching, diffusion, and ion
implantation.
[0005] In general photolithography, a photoresist layer is coated
on a wafer, and the wafer is exposed in an exposure system, and
then developed to transfer the pattern from the mask to the
photoresist layer. Photolithography may be repeated several times
to overlay multi-layer interconnect structures.
[0006] In the overlay step, inaccuracy of alignment must be
controlled within an allowable range. For example, each exclusive
mask used on a corresponding layer forms a predetermined pattern,
in which a target formed in each mask enables alignment of a
current layer with a previous layer.
[0007] Overlay error occurs easily during alignment and exposure
because the mask on the wafer in the exposure system is not stable
or temperature is not controlled.
[0008] FIGS. 1a to 1c are cross-sections of the conventional method
for multi-layer alignment.
[0009] In FIG. 1a, a semiconductor substrate, such as wafer 10, is
provided. A metal layer is formed on a chip of the wafer 10. A
photoresist layer is formed on the metal layer. A first mask 11
having a pattern is exposed to form the pattern on the photoresist
layer by a light source, and the photoresist layer is developed to
form a pattern on the photoresist layer. The metal layer is etched
to form a first metal wire layer 11a using the photoresist layer as
a mask. The photoresist layer is removed. The first metal wire
layer 11a matches the pattern of the first mask layer 11, wherein a
pair of first marks 111 and 112 in the first metal wire layer 11a
correspond to first marks 101 and 102 in the first mask layer
11.
[0010] FIG. 1b is a top view of multiple layers formed by the first
mask, wherein the layers are the metal wire layers 11a. FIG. 1c is
a C-C cross section of FIG. 1b. In FIG. 1b, first marks 101 and 102
are formed on the X and Y axes of the first mask layer 11
respectively. The first marks 101 and 102 align exactly with the
alignment mark of the wafer to form the corresponding first marks
111 and 112 of the metal wire layer 11a.
[0011] FIG. 1d is a top view of the multiple layers formed by the
second mask, comprising metal wire layers 11a. FIG. 1e is a top
view of the pattern formed by the second mask on the pattern formed
by the first mask. FIG. 1f is a C-C cross section of FIG. 1d.
[0012] In FIG. 1d, the second mask is exposed after the first mask
11. Second marks 121 and 122 are formed on the X and Y axes of the
second mask 12 respectively. The second marks 121 and 122 enable a
second metal wire layer 12a to correspondingly form on the first
metal wire layer 11a.
[0013] After photolithography, the wafer is deformed by high
temperature in oxidation or thermal process, and the alignment
marks of the metal wire layer are also deformed. In FIG. 1g, the
position of the first metal wire layer 11a varies from the second
metal wire layer 12a because of the difference in the direction of
deformation between the first metal wire layer 11a and the second
metal wire layer 12a.
[0014] In FIG. 1h, the third metal wire layer 13a is formed on the
second metal wire layer 12a and corresponds to the first metal wire
layer 11a. The third mask, forming the third metal wire layer 13a,
cannot align with the first metal wire layer 11a with the second
metal wire layer 12a because the position of the alignment mark has
changed.
[0015] In FIG. 1i, the third metal wire layer 13a is formed on the
second metal wire layer 12a and corresponds to the second metal
wire layer 12a but not the first wire layer 11a. The pattern is not
transferred well if layers are not aligned precisely before
exposure of the photoresist layer, making the chip unusable.
[0016] In ULSI fabrication, electronic element size is reduced
during various steps, such that the quality of resolution and
overlay accuracy of the conventional exposure process is
sufficient.
SUMMARY OF THE INVENTION
[0017] The present invention is directed to marks and a method for
multi-layer alignment. The marks align easily in the pattern
process, such that alignment errors are reduced.
[0018] Accordingly, the present invention provides a method for
multi-layer alignment of a semiconductor substrate with alignment
marks. A first layer with first alignment marks is formed on the
semiconductor substrate, wherein the first alignment marks are
separated parallelly by a predetermined distance. A second layer
with second alignment marks is formed on the first layer, wherein
the second alignment marks are separated parallelly by a
predetermined distance. The shift distance of each first alignment
mark is measured to calculate a first midpoint between the first
alignments. The shift distance of each second alignment mark is
measured to calculate a second midpoint between the second
alignments. A third midpoint acting as a datum point between the
fist midpoint and the second midpoint is calculated.
[0019] Accordingly, the present invention also provides a method
for multi-layer alignment for a semiconductor substrate with
alignment marks. A first layer with first alignment marks is formed
on the semiconductor substrate, wherein the first alignment marks
are separated parallelly by a predetermined distance. A second
layer with second alignment marks is formed on the first layer,
wherein the second alignment marks are separated parallelly by a
predetermined distance, and the second alignment marks and the
first alignment marks are alternately disposed. The shift distance
of each first alignment mark is measured to calculate a first
midpoint between the first alignments. The shift distance of each
second alignment mark is measured to calculate a second midpoint
between the second alignments. A third midpoint acting as a datum
point between the fist midpoint and the second midpoint is
calculated.
[0020] Accordingly, the present invention provides marks for
multi-layer alignment of a semiconductor substrate, comprising a
first layer with first alignment marks, wherein the first alignment
marks are separated parallelly by a predetermined distance, and a
second layer with second alignment marks, wherein the second
alignment marks are separated parallelly by a predetermined
distance, the second alignment marks and the first alignment marks
are alternately disposed and overlap completely.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] For a better understanding of the present invention,
reference is made to a detailed description to be read in
conjunction with the accompanying drawings, in which:
[0022] FIGS. 1a to 1i are cross-sections of a conventional method
for multi-layer alignment;
[0023] FIGS. 2a to 2h are cross-sections of a method for
multi-layer alignment of the present invention;
[0024] FIG. 3 is a flowchart of a method for multi-layer alignment
of the present invention;
[0025] FIG. 4 is a flowchart of another method for multi-layer
alignment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0026] FIGS. 2a to 2h are cross-sections of a method for
multi-layer alignment of the present invention.
[0027] FIG. 3 is a flowchart of a method for multi-layer alignment
of the present invention.
[0028] FIG. 4 is a flowchart of another method for multi-layer
alignment of the present invention.
[0029] In FIG. 2a, a semiconductor substrate, such as wafer 20, is
provided. A metal layer is formed on a chip of the wafer 20. A
photoresist layer is formed on the metal layer. A first mask 21
with a pattern is exposed to form the pattern on the photoresist
layer by a light source, and the photoresist is developed to form a
pattern on the photoresist layer. The metal layer is etched using
the photoresist layer as an etching mask to form a first metal wire
layer 21a. The photoresist layer is removed. The first metal wire
layer 21a matches the pattern of the first mask layer 21, wherein
first marks 211 and 212 in the first metal wire layer 21a
correspond to first marks 201 and 202 in the first mask layer
21.
[0030] FIG. 2b is a top view of multiple layers formed by the first
mask, wherein the layers are the metal wire layers 21a. FIG. 2c is
a C-C cross section of FIG. 2b. In FIG. 2b, first marks 201 and 202
are formed on the X and Y axes of the first mask 21 respectively.
The first marks 201 and 202 align exactly with the alignment mark
of the wafer to form the corresponding first marks 211 and 212 of
the metal wire layer 21a.
[0031] FIG. 2d is a top view of the multiple layers formed by the
second mask, comprising metal wire layers 21a, FIG. 2e is a top
view of the pattern formed by the second mask on the pattern formed
by the first mask. FIG. 2f is an f-f cross section of FIG. 2e.
[0032] In FIG. 2d, the second mask with two second marks on the X
and Y axes is exposed separately after the first mask 21. A second
metal wire layer 22a is formed on the first metal wire layer 21a.
The second marks 221 and 222 are formed on the second metal wire
layer 22a corresponding to the second marks. The first metal wire
layer 21a and second metal wire layer 22a are sequentially formed
on the wafer 20. The alignment marks 211, 212, 221 and 222 are
separated parallelly by a predetermined distance respectively, and
the alignment marks 221,222 and the alignment marks 211, 212 may
overlap completely, partially, or not at all.
[0033] After photolithography, the wafer is deformed by high
temperature in oxidation or thermal process, and the alignment
marks of the metal wire layer are also deformed.
[0034] FIG. 2g is a cross-section of FIG. 2f.
[0035] In FIG. 2g, the position of the first metal wire layer 21a
varies from the second metal wire layer 22a because of the
difference in the direction of deformation between the first metal
wire layer 21a and the second metal wire layer 22a. A third mask
cannot align with either the first metal wire layer 21a or the
second metal wire layer 22a because the position of the alignment
mark is changed. In the present invention, midpoints 211a and 221a
of the first mark 211 and the second mark 221 are measured, and a
midpoint 231a between the points 211a and 221a is calculated as
shown in FIG. 2g.
[0036] In FIG. 2h, a third metal wire layer is formed exactly on
the second metal wire layer, aligned by the midpoint 231a.
[0037] FIG. 4 is a flowchart of another method for multi-layer
alignment of the present invention.
[0038] In step S401, a semiconductor substrate, such as wafer, is
provided. A first layer, such as metal wire layer, with first marks
is formed on the semiconductor substrate by photolithography. The
first marks are separated parallelly by a predetermined
distance.
[0039] In step S402, a second layer, such as metal wire layer, with
second marks is formed on the first layer by photolithography. The
second marks are separated parallelly by a predetermined distance,
and the second marks and the first marks are alternately
disposed.
[0040] In step S403, a first midpoint and a second midpoint of the
first marks and the second marks on a semiconductor substrate
deformed by oxidation or thermal process is measured
respectively.
[0041] In step S404, a third midpoint between the first midpoint
and the second midpoint is calculated.
[0042] In step S405, the third midpoint is defined as a datum
point.
[0043] In step S406, a third layer is formed on the second layer by
alignment with the datum point, such that the third layer aligns
with both the first layer and the second layer.
[0044] A method for alignment of the present invention can be used
in a conventional metal wire layer as shown in FIG. 3.
[0045] FIG. 3 is a flowchart of a method for multi-layer alignment
of the present invention using the layers with marks shown in FIGS.
1a to 1c.
[0046] In step S301, a semiconductor substrate, such as a wafer, is
provided. A first layer, such as metal wire layer, with at least
two first marks is formed on the semiconductor substrate by
photolithography. The first marks are on the X and Y axes
respectively and separated parallelly by a predetermined
distance.
[0047] In step S302, a second layer, such as metal wire layer, with
at least two second marks is formed on the semiconductor substrate
by photolithography. The second marks are on the X and Y axes
respectively and separated parallelly by a predetermined
distance.
[0048] In step S303, a first midpoint and a second midpoint of each
first mark and each second mark on a semiconductor substrate
deformed by oxidation or thermal process are measured
respectively.
[0049] In step S304, midpoints of the deformed marks on the X and Y
axes are measured respectively. Four marks are formed on the first
layer and the second layer respectively, such that measurement of
the midpoint is performed at least four times for each layer.
Determination and calculation of the method in FIG. 3 is performed
twice as many times as in FIG. 4.
[0050] In step S305, midpoints between each first midpoint and each
second midpoint on the X and Y axes are calculated.
[0051] In step S306, the four midpoints between the first midpoints
and the second midpoints are defined as datum points.
[0052] In step S307, a third layer is formed on the second layer by
alignment with the datum points, such that the third layer aligns
both the first layer and the second layer.
[0053] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *