U.S. patent application number 11/050196 was filed with the patent office on 2005-07-14 for metal oxide semiconductor field-effect transistor and associated methods.
This patent application is currently assigned to STMicroelectronics S.r.I.. Invention is credited to Croce, Giuseppe, Moscatelli, Alessandro.
Application Number | 20050151207 11/050196 |
Document ID | / |
Family ID | 8184826 |
Filed Date | 2005-07-14 |
United States Patent
Application |
20050151207 |
Kind Code |
A1 |
Moscatelli, Alessandro ; et
al. |
July 14, 2005 |
Metal oxide semiconductor field-effect transistor and associated
methods
Abstract
A metal oxide semiconductor transistor integrated in a wafer of
semiconductor material includes a gate structure located on a
surface of the wafer and includes a gate oxide layer. The gate
oxide layer includes a first portion having a first thickness and a
second portion having a second thickness differing from the first
thickness.
Inventors: |
Moscatelli, Alessandro;
(Como, IT) ; Croce, Giuseppe; (Villasanta
(Milano), IT) |
Correspondence
Address: |
Christopher F. Regan, ESQUIRE
ALLEN, DYER, DOPPELT, MILBRATH & GILCHRIST, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.r.I.
Agrate Brianza (MI)
IT
|
Family ID: |
8184826 |
Appl. No.: |
11/050196 |
Filed: |
February 3, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11050196 |
Feb 3, 2005 |
|
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|
10325653 |
Dec 20, 2002 |
|
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6888205 |
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Current U.S.
Class: |
257/395 ;
257/E21.193; 257/E21.345; 257/E21.639; 257/E27.062;
257/E29.133 |
Current CPC
Class: |
H01L 29/42368 20130101;
H01L 29/66659 20130101; H01L 21/26586 20130101; H01L 29/0847
20130101; H01L 21/28167 20130101; H01L 29/7835 20130101; H01L
29/6656 20130101; H01L 21/28194 20130101; H01L 29/665 20130101;
H01L 27/092 20130101; H01L 21/823857 20130101; H01L 29/512
20130101 |
Class at
Publication: |
257/395 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 20, 2001 |
EP |
01830786.8 |
Claims
1-50. (canceled)
51. An integrated structure in a semiconductor wafer comprising: at
least one MOS field-effect transistor including an active region
defining an active area on a surface of the substrate; a silicide
surface layer which at least partially covers the first active
area, at least one LDMOS transistor including a first active region
which defines a first active area on the surface of the substrate;
and a first silicide surface layer which only partially covers the
first active area.
52. The integrated structure according to claim 51, wherein the
LDMOS transistor comprises a gate structure, and the first active
region of the LDMOS transistor comprises a drain region and a drift
region; the first silicide surface layer covering the drain region
and being interrupted in such a way that a portion of the drift
region adjacent to the gate structure is not covered with
silicide.
53. The integrated structure according to claim 52, wherein at
least one electrically insulating element is positioned on a
surface of the non-silicide-covered portion of the drift
region.
54. The integrated structure according to claim 52, wherein the
gate structure comprises a layer of conductive gate layer
superimposed on a gate oxide layer positioned on the surface of the
substrate; and wherein the LDMOS transistor comprises a second
active region including a body region and a source region, each of
the conductive gate layer and the second active region being
covered with a corresponding layer of silicide.
55. The integrated structure according to claim 54, wherein the
gate oxide layer includes a first portion having a first thickness
and a second portion having a second thickness different from the
first thickness.
56. The integrated structure according to claim 55, wherein the
first thickness of the first portion of the gate oxide layer is
greater than the second thickness, the first portion being adjacent
to the drift region and the second portion being adjacent to the
body region.
57. The integrated structure according to claim 51, wherein the
semiconductor substrate comprises a lower portion having a first
type of conductivity and an epitaxial layer thereon having the
first type of conductivity, the epitaxial layer having a
conductivity which is less than the conductivity of the lower
portion, and the first and the second active regions being formed
within the epitaxial layer.
58. A method of manufacturing at least one MOS field-effect
transistor and at least one LDMOS field-effect transistor
integrated in a semiconductor substrate, the method comprising:
forming, in the substrate, two active regions of the at least one
MOS transistor, the active regions defining corresponding active
areas on a surface of the substrate; forming, in the substrate, a
first and a second active region of the at least one LDMOS
transistor, the first and second active regions defining a first
and a second active area on the surface of the substrate, forming a
layer of silicide on at least one portion of each of the two active
areas of the at least one MOS transistor; and forming a first and a
second layer of silicide on the first and second active areas of
the at least one LDMOS transistor, the first layer of silicide only
partially covering the first active area.
59. The method according to claim 58, further comprising: forming,
on the substrate, a gate structure of the at least one LDMOS
transistor, the gate structure including a gate oxide layer and a
conductive gate layer; and forming a further layer of silicide on a
surface of the gate oxide layer.
60. The method according to claim 59, wherein the first active
region comprises a drain region and a drift region, and the second
active region comprises a body region and a source region; and
wherein forming the first and second layers of silicide comprises
forming the first layer of silicide to cover the drain region and
so that a portion of the drift region adjacent to the gate
structure is not silicidized.
61. The method according to claim 60, wherein forming the first and
second layers of silicide further comprises: shielding the portion
of the drift region via a protective element located at least on
the portion; depositing a layer of refractory metal on the first
active area, on the second active area and on the shielding
element; and heat treating the wafer so that the layer of
refractory metal reacts with portions of the first and second
active area on which it is deposited to form silicide.
62. The method according to claim 61, wherein shielding the portion
of the drift region comprises forming a layer of protective
material on the substrate and delimiting the protective element via
masking and etching the layer of protective material.
63. The method according to claim 60, wherein the gate structure of
the at least one LDMOS transistor comprises an insulating gate
layer positioned on the substrate and including a first portion
having a first thickness and a second portion having a second
thickness which is less than the first thickness, the first portion
being adjacent to the drift region.
64. The method according to claim 60, wherein forming the gate
structure comprises: forming at least one oxide layer on the
surface of the substrate, a portion of the oxide layer forming the
insulating gate layer; forming a layer of polysilicon on a surface
of the oxide layer, a portion of the layer of polysilicon forming
the conductive gate layer; masking and etching the layer of
polysilicon to form at least a first lateral wall of the conductive
gate layer and a first aperture in the polysilicon layer; and
further masking and etching the polysilicon layer to form at least
a second lateral wall of the conductive gate layer and a second
aperture in the polysilicon layer.
65. The method according to claim 64, further comprising inclined
ion implantation through the first aperture and through the second
aperture to form the body region and the drift region, the inclined
ion implantation providing for the body regions and the drift
regions to be extended into the wafer at least partially under the
gate structure.
66. The method according to claim 65, wherein, subsequent to the
inclined ion implantation, a heat treatment is applied to the
substrate to permit a further diffusion and activation of the drift
and body regions.
67. The method according to claim 66, wherein the heat treatment is
applied at a temperature of less than 1000.degree. C.
68. The method according to claim 67, wherein the masking and
further masking comprise forming photoresists and irradiating with
electromagnetic waves through a corresponding photomask.
69. The method according to claim 68, wherein the at least one
LDMOS transistor comprises an N-channel LDMOS transistor and a
P-channel LDMOS transistor; and wherein the N-channel transistor
and P-channel transistor are both produced by inclined ion
implantation through the first aperture and through the second
aperture.
70. The method according to claim 58, wherein the at least one
LDMOS transistor comprises an N-channel LDMOS transistor and a
P-channel LDMOS transistor.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to metal oxide semiconductor
field-effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
[0002] For the purposes of the present invention, the expression
"metal oxide semiconductor field-effect transistors" (MOSFET)
denotes various field-effect transistor structures, each including
a wafer of semiconductor material, also called the substrate or
body, a drain region and a source region integrated in the wafer,
and a gate structure including a layer of conductive material
separated from the wafer by a layer of insulating material
(typically an oxide, such as silicon dioxide). It should be noted
that the expression "metal oxide semiconductor" (MOS) is also used
for transistors in which the layer of conductive material of the
gate is formed by a layer of doped polysilicon, instead of metal.
It should also be mentioned that metal oxide semiconductor
transistors are also called insulated-gate field-effect transistors
(IGFET, insulated-gate FET), to emphasize that the gate electrode
is electrically insulated from the wafer or body.
[0003] For example, for the purposes of the present invention the
term MOSFET is applied not only to transistors having the standard
structure, such as the conventional NMOS and PMOS transistors, but
also lateral double-diffusion MOSFETs (LDDMOSFET or LDMOSFET), or
other possible MOSFET structures comprising a different number of
diffused regions and/or a different arrangement thereof in the
substrate, as well as different combinations of the dopants. It is
known that an LDMOSFET, referred to for brevity below as an LDMOS
transistor, comprises, in addition to the drain and gate regions, a
body region which is also diffused under the gate oxide and a drift
region associated with the drain.
[0004] As is known, one of the parameters characterizing a MOSFET
is the breakdown voltage BV. With reference to LDMOS transistors
for example, the breakdown voltage BV is the voltage of the drain
electrode at which the junction between the drain and body is
subject to an avalanche effect (avalanche breakdown). The breakdown
voltage BV is correlated with the dopants of the drain (or drift)
and body regions and with the curvature and denser spacing of the
lines of potential induced by the gate electrode. In the known art,
two different methods are used to obtain sufficiently high values
of breakdown voltage (BV) in MOS or LDMOS transistors.
[0005] In the first method, the doping of the drain and body
regions is appropriately determined, and, in particular, the doping
of the drain region is reduced. This method has the disadvantage of
decreasing the performance of the transistor, causing an increase
in its series resistance (Ron). The second conventional method
proposes the use of a relatively thick gate oxide layer. This
approach has the disadvantage of reducing the transconductance Gm
and the current-carrying capacity of the LDMOS transistor, thus
decreasing the performance of the transistor in terms of gain.
[0006] In the known art, therefore, in the case of LDMOS
transistors, the doping and thickness of the gate oxide must be
determined in such a way as to provide a compromise between the
requirements of a suitable breakdown voltage, a convenient gain and
an adequate series resistance, and this compromise cannot be
considered to be wholly satisfactory.
SUMMARY OF THE INVENTION
[0007] An object of the present invention is to provide a metal
oxide semiconductor field-effect transistor which overcomes the
limitations of conventional transistors.
[0008] An object of the present invention is achieved by a metal
oxide semiconductor integrated in a wafer of semiconductor material
and comprising a gate structure located on one surface of the wafer
and including a gate oxide layer. The gate oxide layer includes a
first portion having a first thickness and a second portion having
a second thickness that is different from the first thickness.
[0009] Another object of the present invention is to provide a
method for manufacturing such a metal oxide semiconductor
field-effect transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The characteristics and advantages of the present invention
will be more clearly understood from the following detailed
description of examples of its embodiment provided without
restrictive intent, and illustrated in the attached drawings, in
which:
[0011] FIGS. 1a to 4 are schematic cross-sectional views
illustrating different stages of production of an LDMOS transistor
according to a particular embodiment of the invention;
[0012] FIG. 5 is a schematic cross-sectional view illustrating an
LDMOS transistor having silicide surface layers according to a
first embodiment of the invention;
[0013] FIG. 6 is a schematic cross-sectional view illustrating an
LDMOS transistor having silicide surface layers according to a
second embodiment of the invention;
[0014] FIG. 7 is a schematic cross-sectional view illustrating an
N-channel MOS transistor according to a particular embodiment of
the invention;
[0015] FIG. 8 is a schematic cross-sectional view illustrating a
P-channel LDMOS transistor which can be constructed according to
the method of the invention; and
[0016] FIG. 9 is a graph illustrating the variation of the
transconductance and saturation current as a function of the
voltage Vgs relative to an N-channel LDMOS transistor and a
P-channel LDMOS transistor according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] In the figures to which the following description refers,
the same numerical references will be used to indicate identical or
similar elements.
[0018] With reference to FIGS. 1a to 4, a description will be given
of a particular example of a process of manufacturing an LDMOS
transistor integrated in a wafer 30 of semiconductor material
according to the invention. Preferably, the LDMOS transistor of
this example is of a type which can be used for radio-frequency
power applications. However, as mentioned above and as will be
evident to persons skilled in the art, the teachings of the present
invention are also applicable MOSFETs of types other than those
described here by way of example.
[0019] According to the example, the wafer 30 is of the
P.sup.+-P.sup.- type, in other words of the type normally used for
CMOS platforms, and comprises a P.sup.+-type silicon substrate 1
and a P.sup.--type epitaxial layer 2 grown on the substrate by
conventional methods. The epitaxial layer 2 forms a separating
surface 10a between the substrate 1 and an outer surface 1b opposed
to it. The epitaxial layer 2 has a conductivity of the same type as
that of the substrate 1, but smaller than this. For example, in
terms of resistivity, the silicon substrate 1 has a resistivity in
the range from 1 to 100 m.OMEGA./cm and a thickness in the range
from 10 .mu.m to 1000 .mu.m. In a particular example, at the end of
the production process the thickness of the substrate 1 is 200
.mu.m. The epitaxial layer 2 has a resistivity which is, for
example, in the range from 1 to 100 .OMEGA./cm, and has a thickness
which is, for example, in the range from 1 to 10 .mu.m.
[0020] The method according to the invention comprises the
formation of an insulating gate layer 3 on the surface 10b. The
insulating gate layer 3 can be made from any suitable dielectric
material. For example, the insulating gate layer 3 can be an oxide,
particularly silicon dioxide. The gate oxide 3 has a non-uniform
thickness and comprises a first portion 4 having a thickness t1 and
a second portion 5 having a thickness t2 which is different from
the thickness t1. As is shown clearly in FIG. 1b, the "thickness of
the gate oxide" denotes the distance between the surface of the
gate oxide facing the surface 10b of the wafer 30 and the opposite
surface of the gate oxide. In FIG. 1b, the first portion 4 and the
second portion 5 are located on opposite sides of an ideal
separating surface S.
[0021] In particular, the thickness t1 of the first portion 4 is
greater than the thickness t2 of the second portion 5. For example,
the thickness t1 is in the range from 20 .ANG. to 500 .ANG. and the
thickness t2 is in the range from 10 to 250 .ANG.. Preferably, for
radio-frequency power applications, the thickness t1 is in the
range from 100 .ANG. to 300 .ANG. and the thickness t2 is in the
range from 25 to 150 .ANG.. In one particular example, the
thickness t1 is approximately 180 .ANG. and the thickness t2 is
approximately 70 .ANG..
[0022] A description is given below (FIGS. 2a-2e) of a particularly
advantageous method which can be used, starting with the wafer 30
of FIG. 1a, to form a gate structure, a body region and a drift
region of the LDMOS transistor. In particular, according to the
example, the gate structure includes the gate oxide 3 and a layer
of conductive gate material such as, preferably, a layer of
polysilicon. A first layer of oxide 6, having a thickness t3 in the
range from t2 to t1 for example, is formed, preferably by growing,
on the surface 10b of the epitaxial layer 2. According to the
values given above, the layer 6 can have, for example, a thickness
of t3=160 .ANG..
[0023] The ideal surface S for separating the two portions 4 and 5
of the gate oxide 3 is then identified in the surface 6. The
surface S ideally separates the first layer of oxide 6 in a first
region 6a located above the part of the surface 10b on which the
first portion 4 of the gate oxide 3 will lie, and a second region
6b located above the part of the surface 10b on which the second
portion 4 of the gate oxide 3 will lie. The region 6b of the layer
6 is then removed. This removal can be carried out, for example, by
a conventional photolithographic method comprising a stage of
forming a photoresist mask and a stage of chemical etching. In
greater detail, the forming of the photoresist mask requires the
use of a layer of photoresist (not shown) placed on a surface 9 of
the layer of oxide 6 and the partial irradiation of this
photoresist with electromagnetic waves (ultraviolet waves or
X-rays, for example) which pass through a suitable photomask (not
shown). The irradiation of the photoresist polymerizes the portion
of the photoresist lying above the first region 6a of the oxide 6
which is not to be removed.
[0024] Chemical etching is then carried out to remove the
non-polymerized portion of the photoresist and the underlying
second region 6b of the oxide layer 6 in such a way as to expose a
surface 8 of the wafer 30. Finally, the removal of the photoresist
is completed. A layer of oxide 7 is then grown on the surface 8 of
the wafer 30 and on a surface 9 of the second region 6a. This
growing stage is carried out in such a way that the portion of the
layer of oxide 7 present on the surface 8 has a thickness of t2 and
the portion of the layer 7 grown on the surface 9 is such that the
layers 6a and 7 have a combined thickness of approximately t1. A
layer of polysilicon 500, suitably doped, is then deposited on top
of the oxide layer 7, as shown in FIG. 2d, in order to make it
conductive. A portion of this polysilicon layer 500 is designed to
form the gate polysilicon of the transistor.
[0025] A first layer of masking made from photoresist 501, or more
briefly a photoresist mask, is then formed on top of the
polysilicon layer 500. This first photoresist mask 501 is produced
from a layer of photoresist placed on the polysilicon layer 500 and
suitably irradiated with electromagnetic waves which pass through a
suitable photomask in such a way as to cause the polymerization of
some of the portions of the layer. With the aid of this first
photoresist mask 501, the polysilicon layer 500 is etched, by
conventional methods for example, to remove the portion of the
polysilicon which is not covered by the polymerized portions of
this mask 501. As shown in FIG. 2a, this etching makes it possible
to form a lateral wall W--S (facing the source side, for example)
of the polysilicon gate layer of the transistor. It should be noted
that, after the chemical etching, the first photoresist mask 501
and the polysilicon layer 500 have an aperture which exposes a
surface S1 of the oxide layer 7 having a thickness t2 in the
proximity of the lateral wall W-S.
[0026] According to the example, the method continues with a stage
of forming a P-type body region 12 which is developed within the
epitaxial layer 2. In particular, the region 12 is formed by ion
implantation. Preferably, boron ions are implanted with an ion beam
F1 of suitable energy and density (shown schematically by arrows in
FIG. 2a) which strikes the surface S1 exposed by the photoresist
mask 501, passing through the oxide layer 7.
[0027] Advantageously, an inclined implantation is carried out; in
other words, the wafer 30 is inclined at a suitable angle to the
ion beam F1 in such a way that the beam of ions can also pass
obliquely through the polysilicon layer 500, but at the same time
this polysilicon layer is shielded by the first photoresist mask
501. It should be noted that, advantageously, the first photoresist
mask 501 is automatically aligned with the underlying polysilicon
500 because it is the product of the same stage of masking (and, in
particular, of the same photomask) and etching as that carried out
to form the wall W-S.
[0028] This provides a highly accurate alignment between the layers
500 and 501, which could not be obtained by forming a separate
photoresist layer on the remaining portion of the polysilicon layer
500 after a stage of etching carried out to form the polysilicon
500. The correct alignment of the overlapping layers 500 and 501
makes the execution of the inclined implantation highly accurate.
This inclined implantation is used to form a body region 12
extending over the desired length (generally fractions of a .mu.m)
under the polysilicon layer 500. On completion of the implantation,
the first photoresist mask 501 is removed.
[0029] A second layer of masking made from photoresist 502, or more
briefly a second photoresist mask 502, is then formed on top of the
polysilicon layer 500 (FIG. 3a). This second photoresist mask 502
is produced from a layer of photoresist placed on the polysilicon
layer 500 and suitably irradiated with electromagnetic waves which
pass through a suitable photomask in such a way as to cause the
polymerization of some of the portions of the layer.
[0030] With the aid of this second photoresist mask 502, the
polysilicon layer 500 is etched, by conventional methods for
example, to remove the portion of the polysilicon which is not
covered by the polymerized portions of this mask 502. As shown in
FIG. 3a, this etching makes it possible to form a lateral wall W-D
(facing the drain side, for example) of the polysilicon gate layer
of the transistor. This second etching of the polysilicon layer 500
forms a polysilicon gate layer 11. It should be noted that, after
etching, the second photoresist mask 502 and the polysilicon layer
500 have an aperture which exposes a surface S2 of the oxide layer
7 having a thickness t1 in the proximity of the lateral wall W-D.
Additionally, the photoresist layer 502 shields the gate
polysilicon 11 and the surface of the oxide layer 7 having a
thickness t2.
[0031] According to the example, the method continues with a stage
of forming an N-type drift region 16 which is developed within the
epitaxial layer 2. In particular, the region 16 is formed by ion
implantation. Preferably, phosphorus ions are implanted with an ion
beam F2 of suitable energy and density (shown schematically by
arrows in FIG. 3a) which strikes the surface S2 exposed by the
photoresist mask 502, passing through the oxide layers 7 and 6a. In
particular, an inclined implantation is carried out in a similar
way to that described for the body region 12, in such a way that
the ion beam F2 can pass obliquely through the gate polysilicon 11,
but at the same time this polysilicon layer is shielded by the
second photoresist mask 502. Thus the implanted ions can occupy a
region extending for several fractions of a .mu.m under the gate
polysilicon 11. It should be noted that, advantageously and
similarly to the process described for the formation of the body
region 12, the implantation of the drift region 16 is carried out
with the same photoresist mask 502 as that made for the forming of
the polysilicon gate layer 11, and therefore with a mask
automatically aligned with the layer 11.
[0032] After the two stages of implantation of the body region 12
and the drift region 16, a stage of heat treatment is
advantageously carried out to enable the corresponding dopants to
be fully diffused and activated. It should be noted that this heat
treatment can be identical to one of those already specified by the
VLSI (Very Large Scale Integration) CMOS platform (carried out, for
example, at less than 1000.degree. C. and in particular at
approximately 900.degree. C.), and can therefore be such that there
is no effect on the electrical characteristics of the CMOS
components which can be formed on the said wafer 30. It should be
noted that, in the conventional manufacture of LDMOS transistors
not integrated with CMOS devices, the drift and body regions are
produced by a diffusion process which requires heat treatment at a
high temperature, generally above 1000.degree. C. In the particular
method described above according to the invention, the use of
inclined implantation enables the body region 12 and drift region
16 to be extended under the polysilicon 11 even without the heat
treatment.
[0033] According to a preferred example of embodiment of the
invention, CMOS devices (not shown), such as conventional N- and
P-channel MOSFETs, are formed on the wafer in addition to the LDMOS
transistor. It is clear from the above description that the method
according to the invention is compatible with the parallel
formation of CMOS devices on the same wafer 30. It should also be
noted that the advantages offered by inclined implantation and
those offered by using the same photoresist layers for forming the
polysilicon 11 and the subsequent implantation are also
considerable in the manufacture of an LDMOS with a gate oxide layer
having a uniform thickness.
[0034] FIG. 3b shows the polysilicon gate layer 11, produced by the
definition of the layer 500, and the gate oxide 3 produced after a
stage of removal of the photoresist 502 and of the layers of oxide
(7 and 6a) not lying under the polysilicon gate layer 11. In one
embodiment of the invention, the body region 12 has a concentration
of dopant impurities in the range from 10.sup.16 to 10.sup.19
ions/cm.sup.3.
[0035] According to the example described, and as shown in FIG. 3b,
the N.sup.--type region 18 is then formed, as is usually done for
CMOS devices, in other words as an N-type region indicated
conventionally by the symbol Nldd (region of weak doping) and
having, in the example, a doping in the range from 1015 to 1019
ions/cm.sup.3. The region 18 can be formed in a conventional way,
by the formation of photoresist masks, followed by ion
implantation.
[0036] Lateral spacers 13a and 13b, illustrated in FIG. 4, are
preferably formed on the lateral walls of the polysilicon gate
layer 11 and of the gate oxide 3. These lateral spacers are formed
by using prior art technologies comprising stages of chemical vapor
phase deposition (CVD) of a suitable material, followed by a stage
of reactive ion etching. The lateral spacers 13a and 13b can
consist of any suitable insulating material such as silicon oxide,
polysilicon, or, preferably, silicon nitride. As is known, lateral
spacers are commonly used in CMOS processes to create less doped
areas of the source and drain regions at the body/drain and
body/source junctions, to reduce the electrical fields, and more
doped areas of the source and drain regions, automatically aligned
with the former areas via the spacers, for more resistive
contacting.
[0037] A source region 14 and a drain region 15, both of the
N.sup.+ type, are then formed within the regions 18 and 16
respectively, by ion implantation through a photoresist mask, as is
usually done for the source and drain regions of CMOS devices. For
example, the source region 14, the drain region 15 and the drift
region 16 have a conductivity in the range from 10.sup.15 to
10.sup.19 ions/cm.sup.3 or, preferably, in the range from 10.sup.16
to 10.sup.18. Typically, the region 18 located on the source side
is more heavily doped than the drift region 16 on the drain
side.
[0038] A body contact region 17, of the P.sup.+ type for example,
is formed within the source region 14 in a similar way to that
described above. It should be noted that the signs of the P/N
conductivity of the regions 1, 2, 12, 14, 17, 18 and 15, 16 and the
intensity of the corresponding doping, expressed by the symbols
+/-, can differ from those indicated above by way of example and
shown in the figures. Moreover, the teachings of the present
invention are also applicable to LDMOS transistors having a
structure different from that of the CMOS platform described, such
as a structure comprising P or N substrates with or without buried
layers.
[0039] It is important to note that the method described above for
manufacturing an N-channel LDMOS transistor on a CMOS platform also
enables P-channel LDMOS transistors to be manufactured in parallel
on the same wafer 30. In other words, the method according to the
present invention can be used to form complementary LDMOS
transistors on a VLSI CMOS platform. A P-channel LDMOS transistor
600 which can be formed by the method described above is shown in
FIG. 8. It will be noted that its layout is similar to that of the
transistor of FIG. 4, except for the sign of the conductivity of
some doped regions. In greater detail, the transistor 600 comprises
an N.sup.+ body region 12', a P.sup.+ source region 14', an N.sup.+
source contact region 17', a weakly doped Nldd region 18', a
P.sup.- drift region 16', and a P.sup.+ drain region 15'.
[0040] In particular, the body region 12' and drift region 16' can
be produced with the same masks and implantation as those used for
the body and drain regions 12 and 16 of the N-channel transistor of
FIG. 4. It should be noted that the method according to the
invention which makes use of inclined implantation enables the
doping and the lengths of the body and drift regions to be defined
in such a way as to optimize the performance of the N-channel or
P-channel LDMOS.
[0041] We shall now return to the transistor of FIG. 4, indicated
as a whole by 100, in which we can distinguish a first active
region 26 and a second active region 27, which extend from the
surface of the epitaxial layer 2 towards the interior of the said
layer. The first active region 26 comprises the drain region 15 and
the drift region 16. The second active region 27 comprises the body
region 12, the source region 14, the body contact region 17 and the
N-type region 18 located under the source spacer 13a. The first and
second active regions are spaced apart from a region 25 included in
the epitaxial layer 2 in which part of the transistor's conducting
channel will be developed.
[0042] It should be noted that the gate oxide layer 3 extends
partially over the separating regions 25 and that its first portion
4 is close to the first active region 26 and its second portion 5
is close to the second active region 27. In other words, the first
portion 4 is located on the "drain side" of the transistor 100, and
the second portion 5 is located on the "source side" of the said
transistor. In particular, the first portion 4 and the second
portion 5 are superimposed, respectively, on at least one part of
the first active region 26 and at least one part of the second
active region 27.
[0043] In greater detail, the first portion 4 of the gate oxide 3
extends in such a way that it is superimposed on the separating
region 25 and on one part of the drift region 16, and the second
portion 5 of the gate oxide 3 extends in such a way that it is
superimposed on at least one part of the body region 12. It should
be noted that the first portion 4 of the gate oxide 3, close to the
drain region 15, has a thickness t1 which can be specified in such
a way as to obtain a desired breakdown voltage BV. In particular,
the breakdown voltage can be increased by increasing the thickness
t1. The breakdown voltage can always be varied by the selection of
the thickness t1, provided that the doping of the drain and body
regions is not such that the value of the breakdown voltage is
predetermined.
[0044] The increase of the breakdown voltage is correlated with an
increase in the distance between the gate polysilicon layer 11 and
the first active region 26. As this distance increases, there is a
decrease in the electrical field responsible for the breakdown
which can occur in the surface area of the epitaxial layer 2 facing
the gate oxide 3 and corresponding to a portion of the polysilicon
layer 11 close to the drain region 16.
[0045] Advantageously, the present invention can be used in the
field of radio-frequency power applications to obtain a breakdown
voltage BV which is higher than that obtainable with conventional
LDMOS transistors having uniform oxide. For example, for
low-voltage applications, with the values of the thicknesses t1 and
t2 indicated above (180 .ANG. and 70 .ANG.), and where the doping
of the body region 12 and drift region 16 is of the order of 1017
ions/cm.sup.3, breakdown voltages BV in the range from 16-20 V have
been obtained. For conventional LDMOS transistors with uniform gate
oxide, having a thickness of 70 .ANG., and doping comparable to
that indicated above, a breakdown voltage of approximately 10 V is
obtained, in other words one considerably lower than that
obtainable by applying the teachings of the present invention.
[0046] Additionally, the increase in the thickness t1, by
permitting a limitation of the surface electrical field, reduces
the undesired generation of "hot carriers" and enables the
gate-drain feedback capacity to be reduced, with a consequent
improvement in the performance of the transistor at high frequency.
It should be noted that the second portion 5 of the gate oxide 3
has a thickness t2 which can be selected in such away as to obtain
a predetermined value of the transconductance Gm of the LDMOS
transistor. The value of this transconductance is proportional to
the gate-body capacity C.sub.ox, which is inversely proportional to
the distance between the gate electrode and the body region, in
other words to the thickness t.sub.2 of the second portion 5. In
particular, decreasing the thickness of this portion 5 produces an
increase in the transconductance Gm and, therefore, an improvement
in the performance of the transistor in terms of amplification
gain. For example, with thicknesses t1 and t2 of 180 and 70 .ANG.
respectively, a Gm of approximately 200 mS/mm was obtained, as
against approximately 80 mS/mm which is obtainable with a uniform
thickness according to the prior art, and equal to 180 .ANG.=t1=t2
with equal breakdown voltage.
[0047] The possibility of selecting the thicknesses of the first
portion 4 and second portion 5 of the gate oxide 3 according to the
present invention is particularly advantageous. This is because
this possibility enables transistors to be produced with a high
breakdown voltage BV and a high transconductance, or, at any rate,
makes it unnecessary to accept a decrease of the transconductance
Gm of the transistor to achieve desired values of the breakdown
voltage. By applying the teachings of the invention, it is possible
to achieve a dual function of increasing the transconductance Gm
while maintaining the breakdown voltage BV at satisfactory
levels.
[0048] Advantageously, the method according to the invention
provides stages of formation of silicide on suitable surfaces of
the wafer 30 of FIG. 4. In FIG. 4, the reference numbers 19 and 20
indicate a first and a second area respectively, corresponding,
respectively, to the surface of the first active region 26 and that
of the second active region 27. FIG. 5 shows a transistor 200 with
a structure similar to that of the transistor 100. The transistor
200 comprises surface layers of silicide 21, 22 and 23, formed,
respectively, on the surface of the gate polysilicon 11, on the
first active area 19 and on the second active area 20. The surface
layers 21, 22 and 23 are, for example, formed from titanium
silicide (TiSi.sub.2), cobalt silicide (CoSi.sub.2) or tungsten
silicide (WSi.sub.2).
[0049] The siliciding of the surfaces of the gate 11 and of the
active areas 19 and 20 has the advantage of decreasing their
surface resistivity while improving the performance of the
transistor. Preferably, the siliciding is carried out by the
conventional method known as self-aligned siliciding, or formation
of a "salicide" (acronym of "self-aligned silicide") which permits
the formation of layers of silicide aligned with the underlying
regions of silicon or polysilicon (salicidizing). For example, the
layers of silicide 21, 22 and 23 are formed by a stage of
deposition (by spraying or "sputtering", for example) of a thin
layer of a refractory metal over the whole surface of the wafer 30,
and in particular over the active areas 19 and 20 and on the
surface of the polysilicon layer 11.
[0050] The wafer 30 is then subjected to heating, allowing a
chemical reaction to take place between the deposited metal and the
underlying silicon, resulting in the formation of the three regions
of silicide 21, 22 and 23. Preferably, the metal used for
siliciding is titanium or cobalt. For tungsten silicide, direct
deposition of WSi.sub.2 on the polysilicon 11 can be used, instead
of the self-aligned silicide method. It should be noted that the
transistor 200, provided with the three layers of silicide 21, 22
and 23, has a particularly good performance, since the resistances
of the gate, source and drain electrodes are significantly reduced.
It should also be noted that the transistor 200 can have a
sufficiently high breakdown voltage BV as a result of being
designed with a suitable thickness t1, without significant losses
in terms of transconductance.
[0051] FIG. 6 shows a transistor 300 according to a further
embodiment of the invention. In the transistor 300, the first
active area 19 of the first active region 26 is only partially
silicidized. In greater detail, the transistor 300 comprises a
layer of silicide 24 extending over the drain region 15 but not
over the portion of the drift region 16 closest to the gate
structure. The transistor of FIG. 6 provides a breakdown voltage
BV, for the same thickness of the first portion 4, greater than
that obtainable with the transistor 200. This is due to the fact
that the siliciding of the first active region is only partial, and
therefore increases the "distance" between the surface of the gate
polysilicon 11 and the more conductive area of the first active
region 26, thus reducing the value of the electrical field which
can be formed in the epitaxial layer 2 in the proximity of the gate
oxide layer 3 on the side of the drain 16, for the same applied
voltage. The increase in the breakdown voltage BV due to the
partial siliciding is possible if the doping of the drift region is
not so high as to impose a value of the breakdown voltage BV which
cannot be modified.
[0052] The structure of FIG. 6 not only provides a high breakdown
voltage, but also offers high performance (a high transconductance
Gm for example), since the resistance of the layers of silicide 21,
22 and 24 is reduced in any case. It should be noted that the
considerable advantages in terms of breakdown and performance
offered by partial siliciding as shown in the solution of FIG. 6
can also be obtained for LDMOS transistors which use a gate oxide
layer of the conventional type, in other words one of uniform
thickness.
[0053] The transistor 300 can be produced from the transistor 100
by forming a protective or shielding element 36. In particular, the
shielding element 36 is formed from electrically insulating
material such as an oxide, and preferably a silicon oxide. For
example, the forming of the element 36 comprises the formation of
an oxide layer (not shown) over the surface of the transistor 100,
the forming of a layer of photoresist positioned over this oxide
layer, and the partial irradiation of this photoresist with
ultraviolet rays through a suitable photomask to cause its
polymerization.
[0054] Chemical etching is then carried out to remove suitable
portions of the layer of photoresist and of the underlying oxide.
The chemical etching forms the oxide element 36 which is positioned
in such a way as to shield at least the part of the first active
area 19 which is to be kept free of silicide. In particular, the
precision achievable by the oxide masking process described above
is such that it is possible to prevent the oxide from covering only
the desired portion of the first active region 19. In this case, as
shown in FIG. 6, the oxide element 36 also extends over part of the
surface of the gate polysilicon 11.
[0055] After the formation of the oxide element 26, the layers of
silicide 21, 22 and 24 are formed in a similar way to that
described above with reference to the transistor 20 (sputtering of
the metal, followed by heat treatment). The oxide element 36
shields the underlying portion of the first active area 19, which
is therefore not covered by the refractory metal during the
sputtering. The oxide element 36 also acts as a lateral spacer. It
should be noted that the method described above for the partial
siliciding of the active area 19 for the LDMOS transistor is
particularly advantageous where the LDMOS transistor 300 is
integrated in the wafer 30 with CMOS devices. This is because, for
conventional CMOS devices, there is a known method of using total
siliciding of the active area and of the gate polysilicon. The
aforementioned method, in which the protective element 36 is used,
enables the total siliciding of the CMOS devices to be carried out
simultaneously with the partial siliciding for the LDMOS device
formed in the same wafer.
[0056] Additionally, it is possible to apply in an advantageous way
the process of total or partial siliciding of active areas 19' and
20' (similar to the active areas 19 and 20) and of the polysilicon
layer 11' to the P-channel LDMOS transistor 600 of FIG. 8, in a
similar way to that described with reference to FIGS. 5 and 6. In
particular, in the partial siliciding of the active area 19', the
portion of the active area 26' close to the polysilicon layer 11'
is kept free of silicide, via a protective element similar to the
element 36.
[0057] Additionally, computer simulation was used to compare the
performance in terms of saturation current Ids and transconductance
Gm of an N-channel LDMOS transistor similar to that of FIG. 6 (in
other words, having partial siliciding) with that of a P-channel
LDMOS transistor, similar to that of FIG. 8, having partial
siliciding of the active area 19'. With reference to this
comparison, FIG. 9 shows the variation of the gate-source voltage
(Vgs) due to the simulation of the transconductance of the
N-channel transistor (curve Gm-N), the transconductance of the
P-channel transistor (curve Gm-P), the Ids current of the N-channel
transistor (curve Ids-N), and the Ids current of the P-channel
transistor (curve Ids-P). These variations were obtained for a
drain-source voltage (Vds) of 5 V.
[0058] It should be noted that the threshold voltages Vt for both
transistors are very similar, being approximately 0.5 V in each
case. An N-channel transistor of the type shown in FIG. 6 was also
constructed and tested, showing a performance closely matching that
found by the simulations. In particular, a cut-off frequency of
more than 20 GHz was measured. For the P-channel transistor, since
the cut-off frequency is correlated with the maximum
transconductance and the gate capacities, which can be considered
similar to those of the N-channel transistor, the cut-off frequency
for the P-channel transistor can be estimated as approximately
14-15 GHz. Additionally, since the same parameters for the
implantation of the doped regions were assumed for the simulation
which was conducted, the P-channel transistor can be considered to
have a breakdown voltage of 15 V, in other words a value similar to
that of the N-channel transistor.
[0059] As stated above, the present invention is also applicable to
conventional P-channel or N-channel MOS transistors which can be
formed on the same wafer 30 or on a different wafer. In relation to
the above, in FIG. 7 the number 400 indicates an example of an
N-channel MOS transistor according to the present invention. The
transistor 400 comprises the wafer 30, a first and a second active
region 33 and 34, a gate oxide layer 32 formed over a surface 45 of
the epitaxial layer 2, a layer of conductive material 35
(polysilicon or metal, for example) and two lateral spacers 36a and
36b. The first active region 33 comprises a drain region 37 which
is strongly doped (N.sup.+) and a region 38 which is weakly doped
(N.sup.-). The second active region 34 comprises a source region 39
which is strongly doped (N+) and a region 40 which is weakly doped
(N.sup.-).
[0060] The gate oxide layer 32 has a first portion 41 having a
first thickness T1 and a second portion 42 having a second
thickness T2 which is different from the thickness T1. In
particular, the first portion 41 is close to the first active
region 33, and its thickness T1 is greater than the thickness T2.
The first portion 41 of the gate oxide 32 advantageously has a
thickness such that it is possible to obtain breakdown voltages
higher than those of conventional MOS transistors using a gate
oxide with uniform thickness. With reference to the
transconductance Gm of the transistor 400, it should be noted that
by using different thicknesses of the gate oxide the value of the
breakdown voltage can be increased at a cost in terms of
transconductance which is smaller than the cost incurred when the
uniform thickness is increased with the thickness of the gate oxide
in a conventional MOS.
[0061] Additionally, the process of siliciding the polysilicon
layer 35, a first active area 33 including the surfaces of the
regions 37 and 38, and a second active area 34 including the
surfaces of the regions 39 and 40 can also be applied to the
transistor 400, in a similar way to that described with reference
to FIGS. 5 and 6. In particular, it is possible to arrange for the
first active area 33 to be only partially silicidized. For example,
the weakly doped region 38 can be kept free of silicide by using a
protective oxide element (not shown) similar to the element 36 of
FIG. 6.
[0062] The method of manufacturing the transistors 100, 200, 300,
and 400 is completed with the formation of suitable metallic
contacts (not shown) on the corresponding drain and source regions,
and on the body contact region if present. Clearly, a person
skilled in the art may further modify and vary the method and
transistors according to the present invention, in order to meet
contingent and specific requirements, all such modifications and
variations being included within the scope of protection of the
invention as defined by the following claims.
* * * * *