U.S. patent application number 11/026542 was filed with the patent office on 2005-07-14 for semiconductor device and manufacturing method thereof.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Fujii, Osamu, Hiyama, Kaoru, Sanuki, Tomoya.
Application Number | 20050151163 11/026542 |
Document ID | / |
Family ID | 34737109 |
Filed Date | 2005-07-14 |
United States Patent
Application |
20050151163 |
Kind Code |
A1 |
Hiyama, Kaoru ; et
al. |
July 14, 2005 |
Semiconductor device and manufacturing method thereof
Abstract
A semiconductor device includes a substrate having a first area
and a second area adjacent to the first area, a first silicon layer
provided on the substrate in the first area, a relaxed layer which
is provided on the substrate in the second area and which has a
lattice constant greater than a lattice constant of the first
silicon layer, and a strained-Si layer which is provided on the
relaxed layer and which has a lattice constant substantially
equivalent to the lattice constant of the relaxed layer.
Inventors: |
Hiyama, Kaoru;
(Yokohama-shi, JP) ; Sanuki, Tomoya;
(Yokohama-shi, JP) ; Fujii, Osamu; (Yokohama-shi,
JP) |
Correspondence
Address: |
FOLEY AND LARDNER
SUITE 500
3000 K STREET NW
WASHINGTON
DC
20007
US
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
|
Family ID: |
34737109 |
Appl. No.: |
11/026542 |
Filed: |
January 3, 2005 |
Current U.S.
Class: |
257/190 ;
257/E21.633; 257/E21.645; 257/E21.66; 257/E27.016; 257/E27.081;
257/E27.092; 257/E29.342 |
Current CPC
Class: |
H01L 27/0629 20130101;
H01L 27/10829 20130101; H01L 21/823807 20130101; H01L 27/1052
20130101; H01L 27/10894 20130101; H01L 27/105 20130101; H01L 29/92
20130101 |
Class at
Publication: |
257/190 |
International
Class: |
H01L 029/10 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 6, 2004 |
JP |
2004-001075 |
Claims
What is claimed is:
1. A semiconductor device comprising: a substrate having a first
area and a second area adjacent to the first area; a first silicon
layer provided on the substrate in the first area; a relaxed layer
which is provided on the substrate in the second area and which has
a lattice constant greater than a lattice constant of the first
silicon layer; and a strained-Si layer which is provided on the
relaxed layer and which has a lattice constant substantially
equivalent to the lattice constant of the relaxed layer.
2. The semiconductor device according to claim 1, further
comprising a buffer film provided between the first silicon layer
and the relaxed layer.
3. The semiconductor device according to claim 1, wherein the
substrate is a silicon substrate, and the semiconductor device
further comprises a buffer layer provided between the relaxed layer
and the silicon substrate, a lattice constant of the buffer layer
becoming greater than a lattice constant of silicon toward a top
surface of the buffer layer.
4. The semiconductor device according to claim 1, wherein the
substrate is a SOI (Silicon On Insulator) substrate, and the
substrate includes an insulation layer and a second silicon layer
provided on the insulation layer.
5. The semiconductor device according to claim 1, further
comprising an insulation layer provided between the substrate and
the first silicon layer.
6. The semiconductor device according to claim 1, further
comprising an insulation layer provided between the substrate and
the relaxed layer.
7. The semiconductor device according to claim 1, wherein the
relaxed layer is formed of silicon germanium.
8. The semiconductor device according to claim 1, wherein the
buffer film is formed of SiN.
9. The semiconductor device according to claim 1, wherein the first
area is an area in which a memory device and/or an analog device is
formed, and the second area is an area in which a digital device is
formed.
10. The semiconductor device according to claim 9, wherein the
memory device includes at least one of a DRAM (Dynamic Random
Access Memory), an SRAM (Static Random Access Memory) and a flush
memory, the analog device includes at least one of a capacitor and
an amplifying element which processes a high-frequency signal, and
the digital device includes a CMOS (Complementary Metal Oxide
Semiconductor) device.
11. A semiconductor device comprising: a silicon substrate having a
first area, a second area adjacent to the first area, and a
protrusion arranged in the first area; a relaxed layer which is
provided on the silicon substrate in the second area and which has
a lattice constant greater than a lattice constant of the silicon
substrate; and a strained-Si layer which is provided on the relaxed
layer and which has a lattice constant substantially equivalent to
the lattice constant of the relaxed layer.
12. The semiconductor device according to claim 11, further
comprising a buffer film provided between the protrusion and the
relaxed layer.
13. The semiconductor device according to claim 11, further
comprising a buffer layer provided between the relaxed layer and
the silicon substrate, a lattice constant of the buffer layer
becoming greater than a lattice constant of silicon toward a top
surface of the buffer layer.
14. The semiconductor device according to claim 11, wherein the
silicon substrate is a SOI substrate, and the silicon substrate
includes an insulation layer and a silicon layer provided on the
insulation layer.
15. The semiconductor device according to claim 11, further
comprising an insulation layer provided in the silicon substrate
and below the protrusion.
16. A method of manufacturing a semiconductor device, comprising:
preparing a substrate having a first area and a second area
adjacent to the first area; forming on the substrate a relaxed
layer which has a lattice constant greater than a lattice constant
of silicon; coating the relaxed layer of the second area with a
resist film; etching the relaxed layer by using the resist film as
a mask; removing the resist film; forming a first silicon layer on
the substrate in the first area; and forming a strained-Si layer on
the relaxed layer by epitaxial growth.
17. The method according to claim 16, further comprising forming a
buffer film on each of side surfaces of the relaxed layer after
removing the resist film.
18. The method according to claim 16, wherein the substrate is a
SOI substrate.
19. A method of manufacturing a semiconductor device, comprising:
preparing a silicon substrate having a first area and a second area
adjacent to the first area; coating the silicon substrate in the
first area with a resist film; etching the silicon substrate by
using the resist film as a mask to form a protrusion on the silicon
substrate; removing the resist film; forming a relaxed layer which
has a lattice constant greater than a lattice constant of the
silicon substrate, on the silicon substrate in the second area; and
forming a strained-Si layer on the relaxed layer by epitaxial
growth.
20. The method according to claim 19, further comprising forming a
buffer film on each of both side surfaces after removing the resist
film.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2004-001075,
filed Jan. 6, 2004, the entire contents of which are incorporated
herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] This invention relates to a semiconductor device and a
manufacturing method thereof and, more particularly, to a
semiconductor device comprising a CMOS (Complementary Metal Oxide
Semiconductor) device, a memory device and the like on the same
substrate and a manufacturing method thereof.
[0004] 2. Description of the Related Art
[0005] Recently, a faster semiconductor device and a lower power
consumption thereof have been increasingly required. For example,
faster operations of a CMOS device provided in a semiconductor
device and lower power consumption thereof have been achieved by a
finer device structure.
[0006] However, as the device structure becomes finer, a pattern
smaller than an exposure wavelength needs to be formed by
lithography. For this reason, an adequate margin of process can
hardly be maintained in the lithographic step. Thus, there is a
limit to satisfying the requirement of faster semiconductor device
and a lower power consumption thereof by the finer device
structure.
[0007] To improve a current driving power of the MOS transistor,
development of providing a strained-Si layer on a semiconductor
substrate and forming a MOS transistor on the strained-Si layer has
been carried out. In the strained-Si layer, a banded structure of
Si is varied by applying a tensile strain to Si.
[0008] The strained-Si layer is formed by forming, for example, a
Si.sub.1-xGe.sub.x layer (hereinafter called a SiGe layer) having a
greater lattice constant than Si on a semiconductor substrate and
forming a Si layer thereon by epitaxial growth, to apply a
sufficiently great tensile strain to Si. If a MOS transistor is
formed on the strained-Si layer thus formed, carrier mobility is
improved.
[0009] In accordance with high integration of a semiconductor
device, a semiconductor device having a CMOS device with a memory
device or an analog device on the same substrate is manufactured.
If a semiconductor substrate having a strained-Si layer is used in
such a semiconductor device, the carrier mobility of the CMOS
device can be improved as explained above.
[0010] In the memory device or analog device, however, current leak
or noise occurs due to influences of the strained-Si layer whose
lattice constant is made greater than that of Si and the SiGe layer
whose lattice constant is greater than that of Si. The
characteristics of the memory device or the analog device are
thereby deteriorated.
[0011] Moreover, if a small-leak type transistor or capacitor in
which the current leak from a capacitor dielectric film or junction
leak causes problems is formed on a strained-Si layer, the device
characteristics are deteriorated. This is serious for the analog
device or DRAM (Dynamic Random Access Memory) including such a
device.
[0012] As for a related technique of this kind, a CMOS device
capable of compensating for high charge carrier mobility by using
strained silicon is disclosed (see Jpn. Pat. Appln. KOKAI
Publication No. 10-107294).
BRIEF SUMMARY OF THE INVENTION
[0013] According to an aspect of the present invention, there is
provided a semiconductor device comprising a substrate having a
first area and a second area adjacent to the first area, a first
silicon layer provided on the substrate in the first area, a
relaxed layer which is provided on the substrate in the second area
and which has a lattice constant greater than a lattice constant of
the first silicon layer, and a strained-Si layer which is provided
on the relaxed layer and which has a lattice constant substantially
equivalent to the lattice constant of the relaxed layer.
[0014] According to another aspect of the present invention, there
is provided a semiconductor device comprising a silicon substrate
having a first area, a second area adjacent to the first area, and
a protrusion arranged in the first area, a relaxed layer which is
provided on the silicon substrate in the second area and which has
a lattice constant greater than a lattice constant of the silicon
substrate, and a strained-Si layer which is provided on the relaxed
layer and which has a lattice constant substantially equivalent to
the lattice constant of the relaxed layer.
[0015] According to still another aspect of the present invention,
there is provided a method of manufacturing a semiconductor device,
comprising preparing a substrate having a first area and a second
area adjacent to the first area, forming on the substrate a relaxed
layer which has a lattice constant greater than a lattice constant
of silicon, coating the relaxed layer of the second area with a
resist film, etching the relaxed layer by using the resist film as
a mask, removing the resist film, forming a first silicon layer on
the substrate in the first area, and forming a strained-Si layer on
the relaxed layer by epitaxial growth.
[0016] According to further another aspect of the present
invention, there is provided a method of manufacturing a
semiconductor device, comprising preparing a silicon substrate
having a first area and a second area adjacent to the first area,
coating the silicon substrate in the first area with a resist film,
etching the silicon substrate by using the resist film as a mask to
form a protrusion on the silicon substrate, removing the resist
film, forming a relaxed layer which has a lattice constant greater
than a lattice constant of the silicon substrate, on the silicon
substrate in the second area, and forming a strained-Si layer on
the relaxed layer by epitaxial growth.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0017] FIG. 1 is a cross-sectional view showing main portions of a
semiconductor device according to a first embodiment of the present
invention;
[0018] FIG. 2 is a cross-sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 1;
[0019] FIG. 3 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 2;
[0020] FIG. 4 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 3;
[0021] FIG. 5 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 4;
[0022] FIG. 6 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 5;
[0023] FIG. 7 is a cross-sectional view showing devices provided on
the semiconductor device shown in FIG. 1;
[0024] FIG. 8 is a cross-sectional view showing a structure of a
SiGe layer 2 shown in FIG. 1;
[0025] FIG. 9 is a cross-sectional view showing the semiconductor
device of FIG. 1 having a SOI structure;
[0026] FIG. 10 is a cross-sectional view showing main portions of a
semiconductor device according to a second embodiment of the
present invention;
[0027] FIG. 11 is a cross-sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 10;
[0028] FIG. 12 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 11;
[0029] FIG. 13 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 12;
[0030] FIG. 14 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 13;
[0031] FIG. 15 is a cross-sectional view showing the semiconductor
device of FIG. 10 having a SOI structure;
[0032] FIG. 16 is a cross-sectional view showing the semiconductor
device of FIG. 15 in which SiGe layer 10 reaches a Si substrate
1;
[0033] FIG. 17 is a cross-sectional view showing main portions of a
semiconductor device according to a third embodiment of the present
invention;
[0034] FIG. 18 is a cross-sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 17;
[0035] FIG. 19 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 18;
[0036] FIG. 20 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 19;
[0037] FIG. 21 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 20;
[0038] FIG. 22 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 21;
[0039] FIG. 23 is a cross-sectional view showing the semiconductor
device of FIG. 17 further having a Si layer 9 on an insulation
layer 8;
[0040] FIG. 24 is a cross-sectional view showing main portions of a
semiconductor device according to a fourth embodiment of the
present invention;
[0041] FIG. 25 is a cross-sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 24;
[0042] FIG. 26 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 25;
[0043] FIG. 27 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 26;
[0044] FIG. 28 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 27;
[0045] FIG. 29 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 28;
[0046] FIG. 30 is a cross-sectional view showing the semiconductor
device of FIG. 24 having a SOI structure;
[0047] FIG. 31 is a cross-sectional view showing main portions of a
semiconductor device according to a fifth embodiment of the present
invention;
[0048] FIG. 32 is a cross-sectional view showing a method of
manufacturing the semiconductor device shown in FIG. 31;
[0049] FIG. 33 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 32;
[0050] FIG. 34 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 33;
[0051] FIG. 35 is a cross-sectional view showing the manufacturing
method subsequently to FIG. 34;
[0052] FIG. 36 is a cross-sectional view showing the semiconductor
device of FIG. 31 having a SOI structure;
[0053] FIG. 37 is a cross-sectional view showing the semiconductor
device of FIG. 36 in which the SiGe layer 10 reaches the Si
substrate 1; and
[0054] FIG. 38 is a cross-sectional view showing the semiconductor
device of FIG. 17 further having a buffer film 20.
DETAILED DESCRIPTION OF THE INVENTION
[0055] Embodiments of the present invention will be explained below
with reference to the accompanying drawings. Elements having like
or similar functions and structures are denoted by similar
reference numbers. Repeated explanations are made if necessary.
First Embodiment
[0056] FIG. 1 is a cross-sectional view showing main portions of a
semiconductor device according to a first embodiment of the present
invention.
[0057] A memory device and/or an analog device, and a digital
device are mounted together on the semiconductor device. The analog
device implies a device which gives a great influence to the
characteristics and reliability of the semiconductor device when
the current leak or noise occurs. The digital device implies a
device which gives a small influence to the characteristics and
reliability of the semiconductor device when the current leak or
noise occurs.
[0058] Specifically, the memory device includes a DRAM, an SRAM
(Static Random Access Memory), a flash memory and the like. The
analog device includes a capacitor, a small-leak type transistor or
amplifying element processing a greatly noise-influenced
high-frequency signal, and the like. The digital device includes a
CMOS device, a logic circuit and the like. In the present
embodiment, an area where the memory device and/or the analog
device (hereinafter referred to as "analog device and the like") is
formed is called an analog area, and an area where the digital
device is formed is called a digital area.
[0059] A Si layer 3 is formed on the analog area of a Si substrate
1 which is formed of, for example, silicon (Si). A SiGe layer 2
having a greater lattice constant than Si is formed on the digital
area of the Si substrate 1. A strained-Si layer 4 having
substantially the same lattice constant as the lattice constant of
the surface of the SiGe layer 2 is formed on the SiGe layer 2. The
semiconductor device shown in FIG. 1 is thus formed.
[0060] Next, a method of manufacturing the semiconductor device
shown in FIG. 1 will be explained with reference to FIG. 1 to FIG.
6. In FIG. 2, the SiGe layer 2 is formed on the Si substrate 1 by,
for example, epitaxial growth. The SiGe layer 2 has a thickness of,
for example, 0.3 to 0.5 .mu.m. Specifically, the thickness of the
SiGe layer 2 is great enough to apply an adequate tensile strain to
the strained-Si layer 4 and cause no defect in the SiGe layer
2.
[0061] A protection layer 5 is deposited on the SiGe layer 2. The
protection layer 5 is formed of, for example, SiN. The protection
layer 5 is used to prevent Si from being formed on the surface of
the SiGe layer 2 when the Si layer is formed during the
after-treatment. Next, a resist film 6 is applied to the surface of
the protection layer 5, and is subjected to patterning by
lithography so as to expose the protection layer 5 of the analog
area.
[0062] After that, the protection layer 5 is etched by wet etching
using the resist film 6 as a mask, in FIG. 3. In addition, the SiGe
layer 2 on the Si substrate 1 is entirely etched by using the
resist film 6 as a mask. The SiGe layer 2 is thus formed on the
digital area alone. Next, the resist film 6 is removed as shown in
FIG. 4.
[0063] Next, a Si layer 7 having a greater thickness than the SiGe
layer 2 is formed by epitaxial growth, on the Si substrate 1, as
shown in FIG. 5. After that, the protection layer 5 is etched by
wet etching as shown in FIG. 6. The surfaces of the SiGe layer 2
and the Si layer 7 are flattened by CMP (Chemical Mechanical
Polishing) to become plane. The CMP step may be omitted.
[0064] Next, Si is subjected to epitaxial growth on the SiGe layer
2 and the Si layer 7 in FIG. 1. The strained-Si layer 4 is thereby
formed on the SiGe layer 2. The Si layer 3 (including the Si layer
7) is formed on the Si layer 7. The semiconductor device shown in
FIG. 1 is thus formed.
[0065] In the semiconductor device having this structure, the Si
layer 3 and the strained-Si layer 4 having a greater lattice
constant than the Si layer 3 can be formed on the same substrate.
Thus, the leak current and noise can be reduced for the analog
device and the like while the carrier mobility can be improved for
the CMOS device, by forming the analog device and the like on the
Si layer 3 and forming the CMOS device and the like on the
strained-Si layer 4.
[0066] FIG. 7 is a cross-sectional view showing an example of the
semiconductor device comprising the devices. A device isolation
area including an STI (Shallow Trench Isolation) is formed on the
semiconductor device. The CMOS device is formed on the strained-Si
layer 4 (i.e. the digital area).
[0067] The CMOS device includes a P-type MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) and an N-type MOSFET. An
N-well 32 formed by diffusing a low-concentration N-type impurity
is provided in the strained-Si layer 4. A gate electrode 30A is
provided on the strained-Si layer 4 via a gate insulation film 30B.
A source/drain area 31 formed by implanting a high-concentration
P-type impurity is provided in the N-well 32 provided on each of
both sides of the gate electrode 30A. The P-type MOSFET is thus
formed.
[0068] In addition, a P-well 35 formed by diffusing a
low-concentration P-type impurity is provided in the strained-Si
layer 4. A gate electrode 33A is provided on the strained-Si layer
4 via a gate insulation film 33B. A source/drain area 34 formed by
implanting a high-concentration N-type impurity is provided in the
P-well 35 provided on each of both sides of the gate electrode 33A.
The N-type MOSFET is thus formed.
[0069] The DRAM is formed on the Si layer 3 (i.e. the analog area).
A trench capacitor 36 is provided on the Si layer 3. A MOSFET 37 is
also provided on the Si layer 3. A source area of the MOSFET 37 is
connected to the trench capacitor 36. A metal layer 39 (bit line)
is provided over the Si layer 3. The metal layer 39 is connected to
a drain area of the MOSFET 37 via a contact plug 38. A password
line 40 is also provided on the Si layer 3 through an insulation
film.
[0070] Furthermore, a junction capacitor is formed on the Si layer
3. A lower electrode 41 is provided in the Si layer 3. A capacitor
dielectric film 42 is provided on the lower electrode 41. An upper
electrode 43 is provided on the capacitor dielectric film 42 so as
to be exposed from the surface of the Si layer 3.
[0071] As shown in FIG. 7, the CMOS device, the DRAM and the like
can be formed on the same substrate, the leak current and noise can
be reduced for the DRAM and the capacitor while the carrier
mobility can be improved for the CMOS device.
[0072] Next, a structure of the SiGe layer 2 will be explained.
FIG. 8 is a cross-sectional view showing the structure of the SiGe
layer 2. The SiGe layer 2 of the present embodiment includes a
buffer layer 2A and a lattice-relaxed layer 2B.
[0073] The buffer layer 2A is formed of silicon germanium
S.sub.1-xGe.sub.x in which the concentration of Ge is increased in
the growth direction. In the buffer layer 2A, for example, the
composition ratio is varied in a range of x=0 to 0.3 from the Si
substrate 1 toward the top surface. The lattice-relaxed layer 2B is
formed of silicon germanium S.sub.1-xGe.sub.x including Ge at a
constant concentration. The lattice-relaxed layer 2B has, for
example, the composition ratio x=0.2 to 0.4. It is desirable that
the lattice-relaxed layer 2B should have the composition ratio
x=approximately 0.3.
[0074] The dislocation between the SiGe layer 2 and the Si
substrate 1 surface can be reduced by forming the SiGe layer 2 in
this manner. Similarly, the dislocation between the SiGe layer 2
and the strained-Si layer 4 can be reduced.
[0075] In a case where the dislocation hardly occurs between the Si
substrate 1 and the lattice-relaxed layer 2B, the lattice-relaxed
layer 2B may be formed on the Si substrate 1. In this case, the
buffer layer 2A may not be required.
[0076] In the present embodiment, too, the substrate may have a SOI
(Silicon On Insulator) structure. FIG. 9 is a cross-sectional view
showing the semiconductor device having the SOI structure. An
insulation layer 8 is provided on the Si substrate 1. The
insulation layer 8 is formed of, for example, SiO.sub.2.
[0077] A Si layer 9 is provided on the insulation layer 8. The
structure of the Si layer 3, the SiGe layer 2 and the strained-Si
layer 4 formed on the Si layer 9 is the same as that shown in FIG.
1. In addition, a method of forming the Si layer 3, the SiGe layer
2 and the strained-Si layer 4 are the same as the forming method
explained with reference to FIG. 1.
[0078] As for an example of the method of manufacturing the SOI
structure, the insulation layer 8 is first deposited on the Si
substrate 1. Then the Si layer 9 is formed on the insulation layer
8. An existing SOI substrate may be prepared and used.
[0079] In the semiconductor device shown in FIG. 9, too, the leak
current and noise can be reduced for the analog device and the like
while the carrier mobility can be improved for the CMOS device, by
forming the analog device and the like on the Si layer 3 and
forming the CMOS device and the like on the strained-Si layer
4.
[0080] Furthermore, the parasitic capacitance of the substrate can
be reduced by employing the SOI structure. The operation speed of
the CMOS device can be thereby enhanced.
[0081] In the present embodiment, as described above in detail, the
analog area where the analog device and the like are formed, and
the digital area where the digital device is formed are separated
on the same Si substrate 1. The Si layer 3 is formed in the analog
area of the Si substrate 1 while the strained-Si layer 4 is formed
in the digital area thereof.
[0082] According to the present embodiment, the analog device and
the like, and the digital device can be therefore formed on the
same substrate. If the analog device and the like, and the digital
device are formed on the same substrate, the leak current and noise
can be reduced for the analog device and the like while the carrier
mobility can be improved for the CMOS device.
[0083] The SiGe layer 2 includes the buffer layer 2A and the
lattice-relaxed layer 2B. The dislocation between the SiGe layer 2
and the layers which are in contact therewith can be therefore
reduced.
[0084] If the Si substrate 1 has the SOI structure, the operation
speed of the CMOS device can be further enhanced by reducing the
parasitic capacitance.
Second Embodiment
[0085] FIG. 10 is a cross-sectional view showing main portions of a
semiconductor device according to a second embodiment of the
present invention. The Si substrate 1 has a protrusion 1A. The
protrusion 1A is formed in the analog area of the Si substrate 1.
The protrusion 1A is also formed of the same material as the Si
substrate 1.
[0086] There is a digital area on each of both sides of the
protrusion 1A. A SiGe layer 10 is formed in the digital area of the
Si substrate 1. In other words, the SiGe layer 10 has a top surface
exposed, and is embedded in the Si substrate 1. The structure of
the SiGe layer 10 is the same as that of the SiGe layer 2 of the
first embodiment.
[0087] A Si layer 11 is formed on the protrusion 1A. A strained-Si
layer 12 having substantially the same lattice constant as the
lattice constant of the surface of the SiGe layer 10 is formed on
the SiGe layer 10. The semiconductor device shown in FIG. 10 is
thus formed.
[0088] Next, a method of manufacturing the semiconductor device
shown in FIG. 10 will be explained with reference to FIG. 10 to
FIG. 14. In FIG. 11, a protection layer 13 is deposited on the Si
substrate 1. The protection layer 13 is formed of, for example,
SiN. The protection layer 13 is used to prevent SiGe from being
formed on the surface of the Si substrate 1 when the SiGe layer is
formed during the after-treatment.
[0089] Next, a resist film 14 is applied to the surface of the
protection layer 13, and is subjected to patterning by lithography
so as to expose the protection layer 13 of the digital area.
[0090] After that, the protection layer 13 is etched by using the
resist film 14 as a mask, in FIG. 12. In addition, the Si substrate
1 is etched to a predetermined depth by using the resist film 14 as
a mask. The predetermined depth corresponds to the thickness of the
SiGe layer 10. The thickness of the SiGe layer 10 is great enough
to apply an adequate tensile strain to the strained-Si layer 12 and
cause no defect in the SiGe layer 10. The protrusion 1A is thus
formed. After that, the resist film 14 is removed.
[0091] Next, the SiGe layer 10 is formed on the Si substrate 1 of
the digital area by epitaxial growth such that the top surface of
the SiGe layer 10 is higher than the top surface of the protrusion
1A as shown in FIG. 13. The protection layer 13 is etched by wet
etching as shown in FIG. 14. The surfaces of the SiGe layer 10 and
the protrusion 1A are flattened by CMP (Chemical Mechanical
Polishing) to become plane. The CMP step may be omitted.
[0092] Next, Si is subjected to epitaxial growth on the SiGe layer
10 and the protrusion 1A in FIG. 10. The strained-Si layer 12 is
thereby formed on the SiGe layer 10. The Si layer 11 is formed on
the protrusion 1A. The semiconductor device shown in FIG. 10 is
thus formed.
[0093] In the semiconductor device having this structure, the Si
layer 11 and the strained-Si layer 12 having a greater lattice
constant than the Si layer 11 can be formed on the same substrate.
Thus, the leak current and noise can be reduced for the analog
device and the like while the carrier mobility can be improved for
the CMOS device, by forming the analog device and the like on the
Si layer 11 and forming the CMOS device and the like on the
strained-Si layer 12.
[0094] In addition, if the devices shown in FIG. 7 are formed on
the semiconductor device shown in FIG. 10, the characteristics of
the devices can be improved. The other advantage is also the same
as that of the first embodiment.
[0095] The structure of the semiconductor device according to the
present embodiment is substantially the same as that of the
semiconductor device according to the first embodiment. However,
the semiconductor device can be effectively manufactured by
selecting the manufacturing method of the first embodiment or that
of the second embodiment in accordance with the extent of the
analog area and the digital area.
[0096] In the present embodiment, the Si substrate 1 may have the
SOI (Silicon On Insulator) structure. FIG. 15 is a cross-sectional
view showing the semiconductor device having the SOI structure. The
insulation layer 8 is provided on the Si substrate 1. The
insulation layer 8 is formed of, for example, SiO.sub.2. The Si
layer 9 is provided on the insulation layer 8. The other
constituent elements are the same as those of FIG. 10.
[0097] In the semiconductor device shown in FIG. 15, the SiGe layer
10 may reach the Si substrate 1. FIG. 16 is a cross-sectional view
showing the semiconductor device of FIG. 15 in which the SiGe layer
10 reaches the Si substrate 1. An example of a method of
manufacturing the semiconductor device shown in FIG. 16 is
explained below.
[0098] For example, the Si layer 9 of the digital area is etched by
using the resist film 14 shown in FIG. 11 as a mask, on a SOI
substrate (not shown), and the insulation layer 8 is etched to
expose the Si substrate 1. Then the resist film 14 is removed.
[0099] Next, the SiGe layer 10 having a higher top surface than the
top surface of the Si layer 9 of the analog area is formed on the
Si substrate 1 of the digital area by epitaxial growth. The
following steps of the manufacturing method are the same as those
of the manufacturing method shown in FIG. 10.
[0100] In the semiconductor devices shown in FIG. 15 and FIG. 16,
too, the Si layer 11 and the strained-Si layers 12 having a greater
lattice constant than the Si layer 11 can be formed on the same
substrate. In addition, the parasitic capacitance can be reduced by
employing the SOI structure and the operation speed of the devices
formed on the Si layer 11 and the Si layer 9 can be thereby
enhanced.
Third Embodiment
[0101] FIG. 17 is a cross-sectional view showing main portions of a
semiconductor device according to a third embodiment of the present
invention. A Si layer 16 is provided in the analog area of the Si
substrate 1. The insulation layer 8 formed of, for example,
SiO.sub.2 is provided in the digital area of the Si substrate
1.
[0102] A SiGe layer 15 is provided on the insulation layer 8. The
structure of the SiGe layer 15 is the same as that of the SiGe
layer 2 of the first embodiment. A Si layer 17 having substantially
the same lattice constant as that of the top surface of the SiGe
layer 15 is provided on the SiGe layer 15. The semiconductor device
shown in FIG. 17 is thus formed.
[0103] Next, a method of manufacturing the semiconductor device
shown in FIG. 17 will be explained with reference to FIG. 17 to
FIG. 22. In FIG. 18, the insulation layer 8 is formed on the Si
substrate 1. The Si layer 9 is formed on the insulation layer 8. An
existing SOI substrate may be prepared and used.
[0104] Next, the SiGe layer 15 is formed on the Si layer 9 by
epitaxial growth. The protection layer 5 formed of SiN is deposited
on the SiGe layer 15.
[0105] The semiconductor device is annealed in FIG. 19. Ge in the
SiGe layer 15 is thermally diffused to the Si layer 9 and the Si
layer 9 becomes the SiGe layer 15, by the annealing. The resist
film 6 is applied to the surface of the protection layer 5, and is
subjected to patterning by lithography so as to expose the
protection layer 5 of the analog area.
[0106] After that, the protection layer 5 is etched by using the
resist film 6 as a mask, in FIG. 20. The SiGe layer 15 is also
etched by using the resist film 6 as a mask. Furthermore, the
insulation layer 8 is also etched by using the resist film 6 as a
mask. The surface of the Si substrate 1 in the analog area is thus
exposed.
[0107] The resist film 6 is removed as shown in FIG. 21. A Si layer
18 is formed on the Si substrate 1 by epitaxial growth such that
the top surface of the Si layer 18 is higher than the top surface
of the SiGe layer 15. In FIG. 22, the protection layer 5 is etched
by wet etching. The surfaces of the SiGe layer 15 and the Si layer
18 are flattened by the CMP to become plane.
[0108] Si is subjected to epitaxial growth on the SiGe layer 15 and
the Si layer 18 as shown in FIG. 17. The Si layer 17 is thereby
formed on the SiGe layer 15. The Si layer 16 (including the Si
layer 18) is formed on the Si substrate 1 of the analog area. The
semiconductor device of FIG. 17 is thus formed.
[0109] In the semiconductor device having this structure, the
insulation layer 8 can be formed below the Si layer 17 of the
digital area alone. Therefore, since the parasitic capacitance can
be reduced, the operation speed of the CMOS device can be
enhanced.
[0110] If the concentration of Ge in the SiGe layer 15 is low or
thermal diffusion of Ge does not largely occur, the Si layer 9 does
not entirely become the SiGe layer 15, but remains as it is. FIG.
23 is a cross-sectional view showing the semiconductor device
having the Si layer 9 on the insulation layer 8.
[0111] In the semiconductor device having this structure, too, the
same advantage as that of the present embodiment can be obtained.
Moreover, it is possible to prevent a defect from being caused in
an interface between the Si layer 9 and the SiGe layer 15 as
compared with a case where the SiGe layer 15 is stacked on the Si
layer 9.
Fourth Embodiment
[0112] FIG. 24 is a cross-sectional view showing main portions of a
semiconductor device according to a fourth embodiment of the
present invention. The Si layer 3 is provided in the analog area of
the Si substrate 1. The SiGe layer 2 is provided in the digital
area of the Si substrate 1.
[0113] A buffer film 19 is provided between the Si layer 3 and the
SiGe layer 2 to prevent a fault from being caused at a bonding
portion between the Si layer 3 and the SiGe layer 2. In other
words, the buffer film 19 is formed of a material such as SiN,
which can absorb the stress caused by the SiGe layer 2 or the fault
resulting from the SiGe layer 2.
[0114] The strained-Si layer 4 is provided on the SiGe layer 2. The
semiconductor device of FIG. 24 is thus formed.
[0115] Next, a method of manufacturing the semiconductor device
shown in FIG. 24 will be explained with reference to FIG. 24 to
FIG. 29. In FIG. 25, fort example, the SiGe layer 2 is formed on
the Si substrate 1 by epitaxial growth.
[0116] The protection layer 5 is deposited on the SiGe layer 2. The
resist film 6 is applied to the surface of the protection layer 5,
and is subjected to patterning by lithography so as to expose the
protection layer 5 of the analog area.
[0117] After that, the protection layer 5 is etched by using the
resist film 6 as a mask, in FIG. 26. The SiGe layer 2 is also
etched by using the resist film 6 as a mask. Then, the resist film
6 is removed. The buffer film 19 formed of, for example, SiN is
deposited on the entire surface of the semiconductor device.
[0118] The buffer film 19 on the Si substrate 1 and the protection
layer 5 is etched by anisotropic etching in FIG. 27. The buffer
film 19 is thereby formed on side surfaces of the SiGe layer 2
alone.
[0119] The Si layer 7 having a greater thickness than the SiGe
layer 2 is formed on the Si substrate 1 by epitaxial growth, as
shown in FIG. 28. In FIG. 29, the protection layer 5 is etched by
the wet etching. The surfaces of the SiGe layer 2 and the Si layer
7 are flattened by the CMP to become plane.
[0120] Next, Si is subjected to epitaxial growth on the SiGe layer
2 and the Si layer 7 as shown in FIG. 24. The strained-Si layer 4
is thereby formed on the SiGe layer 2. The Si layer 3 (including
the Si layer 7) is formed on the Si layer 7.
[0121] Si is not subjected to epitaxial growth on the buffer film
19. By thinning the buffer film 19, however, cavities are not
generated between the Si layer 3 and the strained-Si layer 4, due
to extension of Si from the SiGe layer 2 and the Si layer 7. The
semiconductor device shown in FIG. 24 is thus formed.
[0122] The composition ratio of Ge in the SiGe layer 2 becomes
larger toward the top surface of the layer. In other words, the
lattice constant of the SiGe layer 2 becomes larger toward the top
surface. Thus, if the composition ratio of Ge is made larger, a
fault may occur at the bonding portion between the SiGe layer 2 and
the Si layer 3.
[0123] In the present embodiment, however, the buffer film 19 is
provided between the SiGe layer 2 and the Si layer 3. The buffer
film 19 absorbs the stress caused by the SiGe layer 2 or the fault
resulting from the SiGe layer 2. The buffer film 19 also prevents
the stress caused by the SiGe layer 2 or the like from being
applied to the bonding portion between the SiGe layer 2 and the Si
layer 3. The fault between the SiGe layer 2 and the Si layer 3 can
be thereby reduced. The other advantages are the same as those of
the first embodiment.
[0124] In the present embodiment, too, the Si substrate 1 may have
the SOI structure. FIG. 30 is a cross-sectional view showing the
semiconductor device having the SOI structure. With this structure,
the same advantages as those of the semiconductor device described
with reference to FIG. 9 can be obtained.
Fifth Embodiment
[0125] FIG. 31 is a cross-sectional view showing main portions of a
semiconductor device according to a fifth embodiment of the present
invention. The Si substrate 1 has the protrusion 1A. The protrusion
1A is formed in the analog area of the Si substrate 1.
[0126] There is the digital area on each of both sides of the
protrusion 1A. The SiGe layer 10 is formed in the digital area of
the Si substrate 1. In other words, the SiGe layer 10 has a top
surface exposed, and is embedded in the Si substrate 1. In
addition, a buffer film 20 is provided between the protrusion 1A
and the SiGe layer 10. The buffer film 20 is formed of, for
example, SiN.
[0127] The Si layer 11 is formed on the protrusion 1A. The
strained-Si layer 12 is formed on the SiGe layer 10. The
semiconductor device shown in FIG. 31 is thus formed.
[0128] Next, a method of manufacturing the semiconductor device
shown in FIG. 31 will be explained with reference to FIG. 31 to
FIG. 35. In FIG. 32, the protection layer 13 is deposited on the Si
substrate 1. The resist film 14 is applied to the surface of the
protection layer 13, and is subjected to patterning by lithography
so as to expose the protection layer 13 of the digital area.
[0129] Next, the protection layer 13 is etched by using the resist
film 14 as a mask, in FIG. 33. In addition, the Si substrate 1 is
etched to a predetermined depth by using the resist film 14 as a
mask. The protrusion 1A is thus formed.
[0130] After that, the resist film 14 is removed. The buffer film
20 formed of, for example, SiN is deposited on the entire surface
of the semiconductor device.
[0131] In FIG. 34, the buffer film 20 on the Si substrate 1 and the
protection layer 13 is etched by anisotropic etching. The buffer
film 20 is thus formed on both sides of the protrusion 1A.
Furthermore, the SiGe layer 10 is formed on the Si substrate 1 of
the digital area by epitaxial growth such that the top surface of
the SiGe layer 10 is higher than the top surface of the protrusion
1A.
[0132] In FIG. 35, the protection layer 13 is etched by wet
etching. The surfaces of the SiGe layer 10 and the protrusion 1A
are flattened by the CMP to become plane.
[0133] Next, Si is subjected to epitaxial growth on the SiGe layer
10 and the protrusion 1A in FIG. 31. The strained-Si layer 12 is
thereby formed on the SiGe layer 10. The Si layer 11 is formed on
the protrusion 1A.
[0134] Si is not subjected to epitaxial growth on the buffer film
20. By thinning the buffer film 19, however, cavities are not
generated between the Si layer 11 and the strained-Si layer 12, due
to extension of Si from the SiGe layer 10 and the protrusion 1A,
The semiconductor device shown in FIG. 31 is thus formed.
[0135] In the present embodiment, as described above, the buffer
film 20 is provided between the SiGe layer 10 and the protrusion
1A. Therefore, the fault generated at the bonding portion between
the SiGe layer 10 and the protrusion 1A can be reduced.
[0136] In the present embodiment, too, the Si substrate 1 may have
the SOI structure. FIG. 36 is a cross-sectional view showing the
semiconductor device having the SOI structure. With this structure,
the same advantages as those of the semiconductor device described
with reference to FIG. 15 can be obtained.
[0137] In the semiconductor device shown in FIG. 36, the SiGe layer
10 may reach the insulation layer 8. FIG. 37 is a cross-sectional
view showing the semiconductor device of FIG. 36 in which the SiGe
layer 10 reaches the insulation layer 8. With this structure, the
same advantages as those of the semiconductor device described with
reference to FIG. 16 can be obtained.
[0138] Moreover, the semiconductor device of the third embodiment
shown in FIG. 17 may have the buffer film 20. FIG. 38 is a
cross-sectional view showing the semiconductor device of FIG. 17
further having the buffer film 20. With this structure, the fault
generated at the bonding portion between the Si layer 16 and the
SiGe layer 15 can be reduced.
[0139] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *