U.S. patent application number 10/878364 was filed with the patent office on 2005-06-23 for method of inhibiting degradation of gate oxide film.
This patent application is currently assigned to Hynix Semiconductor Inc.. Invention is credited to Yoo, Kyung Dong.
Application Number | 20050136688 10/878364 |
Document ID | / |
Family ID | 36181302 |
Filed Date | 2005-06-23 |
United States Patent
Application |
20050136688 |
Kind Code |
A1 |
Yoo, Kyung Dong |
June 23, 2005 |
Method of inhibiting degradation of gate oxide film
Abstract
A method of inhibiting degradation of a transistor gate oxide
film by high density plasma is disclosed. After a gate electrode is
formed, impurity is injected on the surface of an interlayer
insulating film, thereby changing surface characteristics of the
interlayer insulating film to scatter ultraviolet rays which are
factors of degradation of the interlayer insulating film.
Accordingly, the ultraviolet rays are prevented from being
permeated into a gate insulating oxide film.
Inventors: |
Yoo, Kyung Dong; (Seoul,
KR) |
Correspondence
Address: |
HELLER EHRMAN WHITE & MCAULIFFE LLP
1717 RHODE ISLAND AVE, NW
WASHINGTON
DC
20036-3001
US
|
Assignee: |
Hynix Semiconductor Inc.
Gyeonggi-do
KR
|
Family ID: |
36181302 |
Appl. No.: |
10/878364 |
Filed: |
June 29, 2004 |
Current U.S.
Class: |
438/783 ;
257/E21.248; 257/E21.275; 257/E21.276; 257/E21.576 |
Current CPC
Class: |
H01L 21/76801 20130101;
H01L 21/02321 20130101; H01L 21/02252 20130101; H01L 21/31155
20130101; H01L 21/76829 20130101; H01L 21/28247 20130101; H01L
21/02304 20130101; H01L 21/76825 20130101 |
Class at
Publication: |
438/783 |
International
Class: |
H01L 021/336; H01L
031/119; H01L 027/108; H01L 021/31 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 23, 2003 |
KR |
2003-0095301 |
Claims
1. A method for manufacturing a semiconductor device, comprising
the steps of: forming a gate oxide film and a gate electrode on a
semiconductor substrate; forming an interlayer oxide film on the
semiconductor substrate including the gate electrode; injecting an
impurity into a surface of the interlayer oxide film to form a
layer for preventing UV (Ultraviolet rays) generated by high
density plasma from penetrating the interlayer oxide film; and
forming a HDP oxide film on the interlayer oxide film.
2. (canceled)
3. The method according to claim 1, wherein the impurity is
selected from a group consisting of As, P, B, BF.sub.2, BF, Si and
Ge.
4. The method according to claim 1, wherein a concentration of the
impurity ranges from 1 e.sup.17/cm.sup.3 to 1
e.sup.22/cm.sup.3.
5. (canceled)
6. The method according to claim 1, wherein the step of injecting
the impurity is performed immediately after the formation of the
interlayer oxide film or prior to the formation of the HDP oxide
film.
7. The method according to claim 1, wherein the impurity is
injected to a depth of less than 1000 .ANG..
Description
CORRESPONDING RELATED APPLICATIONS
[0001] The present invention claims the benefit of and priority to
Korean Patent Application No. 10-2003-0095301, filed on Dec. 23,
2003.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention generally relates to a method of
inhibiting degradation of a transistor gate oxide film due to
ultraviolet rays in a High Density Plasma (hereinafter, referred to
as "HDP") process, and more specifically, to a method for
effectively preventing ultraviolet rays from permeating a gate
insulating oxide film by injecting impurity into the surface of an
interlayer insulating film so as to change a surface characteristic
of the interlayer insulating film.
[0004] 2. Description of the Prior Art
[0005] A HDP process utilizes high power plasma, which generates
ultraviolet rays (UV). The UV is known to have a predetermined
wavelength ranging from about 200 to 800 nm. According to the
Plank's Law on wavelength of light and its energy, the energy E is
proportional to frequency (E=hv; h=Plank's constant, v=frequency of
light). Since the frequency v is inversely proportional to the
wavelength of light, E becomes larger as the wavelength of light
becomes shorter. Accordingly, the UV having a wavelength ranging
from 200 to 800 nm has an energy ranging from about 5 eV to 1.5 eV
If such energy reaches a silicon substrate, an Electron-Hole Pair
is formed. The formation of the Electron-Hole Pair is generally
occurs when an energy larger than the Band-Gap energy of 1.1 eV in
the silicon is injected thereto. The electron is again trapped in a
gate oxide film, thereby degrading characteristics of the oxide
film.
[0006] A Plasma Induced Damage (hereinafter, referred to as "PID")
or a Plasma Induced Radiation Damage (hereinafter, referred to as
"PIRD") of the HDP cannot be controlled in the conventional
process. A method of inhibiting the use of HDP or reducing power of
plasma to reduce the PID has been proposed. However, the method
reduces the uniform deposition ability which is an advantage in
using HDP, resulting in short circuits in a subsequent process.
[0007] Recently, a method of depositing an amorphous silicon film
after formation of a transistor has been proposed to inhibit
degradation of a gate oxide film by PID or PIRD. In accordance with
the method, a formation process of contact for connecting wires
cannot be performed by a single etching process. In addition, a
possibility of a short circuit between wires by the amorphous
silicon film exists.
SUMMARY OF THE INVENTION
[0008] It is an object of the present invention to provide a method
of inhibiting degradation of a transistor gate oxide film by
HDP.
[0009] In an embodiment, a method for manufacturing a semiconductor
device is provided. The method comprises steps of forming a gate
oxide film and a gate electrode on a semiconductor substrate,
forming an interlayer oxide film on the semiconductor substrate
including the gate electrode, injecting an impurity into a surface
of the interlayer oxide film to form a layer for preventing UV
(ultraviolet rays) generated by high density plasma from
penetrating the interlayer oxide film, and forming a HDP oxide film
on the interlayer oxide film.
[0010] The impurity is selected from a group consisting of As, P,
B, BF.sub.2, BF, Si and Ge. A concentration of the impurity ranges
from 1 e.sup.17/cm.sup.3 to 1 e.sup.22/cm.sup.3. The impurity is
injected to a depth of less than 1000 .ANG..
[0011] The step of injecting an impurity is performed immediately
after the formation of the interlayer oxide film or prior to the
formation of the HDP oxide film, thereby obtaining the effect of
the present invention.
[0012] According to the method of the present invention, the
surface characteristics of the oxide film are changed so that UV
rays generated from the HDP process do not permeate into the gate
oxide film deposited on the semiconductor substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a mimetic diagram illustrating a principle
according to an embodiment of the present invention.
[0014] FIG. 2 is a graph illustrating a measurement result of an
antenna test pattern of a gate oxide film according to a
conventional process.
[0015] FIG. 3 is a graph illustrating a measurement result of an
antenna test pattern of a gate oxide film according to an
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] The present invention will be described in detail with
reference to the accompanying drawings.
[0017] FIG. 1 is a mimetic diagram illustrating a principle
according to an embodiment of the present invention.
[0018] A plurality of gate electrodes 12 having a stacked structure
of suicides such as polysilicon and tungsten silicide are formed on
a substrate 10 having various elements thereon. Then, a gate oxide
film (not shown) is formed at an interface of the substrate 10 and
the gate electrode 12, and a hard mask insulating film 14 is formed
on the gate electrode 12 for preventing a damage of the gate
electrode in a subsequent self-alignment etching process.
[0019] Thereafter, a spacer (not shown) such as a nitride film is
formed on a side wall of the gate electrode 12, and then an oxide
film 16 which is an interlayer insulating film is deposited on the
resulting structure.
[0020] Next, an impurity is injected into a surface of the oxide
film 16 to change the chemical state of the surface of the oxide
film 16, thereby oxide film 18 having the impurity therein is
formed.
[0021] Here, the impurity in the oxide film 18 scatters UV rays
generated from the HDP process to inhibit the UV from permeating
into the oxide film 16.
[0022] In order to compare the effect of the present invention with
that of the conventional method, FIGS. 2 and 3 show graphs
illustrating measurement results of antenna test patterns. An
antenna Ratio ("A.R") which refers to a ratio of an area of the
gate oxide film to that of gate that receives PID, and test
patterns ("Ref") having no separate antenna gate from 13000 times
are shown in FIGS. 2 and 3.
[0023] The measurement was done by applying a voltage of 3V to the
gate to measure a leakage current flowing into the silicon
substrate. The thickness of the gate oxide film is 37 .ANG., which
is a thickness sensitive to PID. After the formation of the gate
electrode, the oxide film 16 is deposited by using a low pressure
chemical vapor deposition method which does not generate a PID. The
leakage current is measured after the deposition of a HDP oxide
film on the oxide film 16 and various wiring process for test
patterns.
[0024] As seen in the measurement results, the amount of leakage
current flowing through the oxide film increases proportional to
the antenna ratio. In 50% cumulative distribution, the leakage
current of less than 1.0 pA is generated under the Ref condition
and an A.R condition of 333 times, and the leakage current of 10 nA
is generated under an A.R condition of 13000 times (see FIG.
2).
[0025] Contrary to the conventional method, leakage current of less
than 1.0 pA is generated in all cumulative distribution regardless
of A.R in accordance with the present invention (see FIG. 3). This
is because injected impurity forms a layer for inhibiting UV from
permeating into the surface of the insulating oxide film.
[0026] As discussed earlier, the degradation phenomenon of the gate
oxide film by PID is prevented even in high antenna ratio in
accordance with the present invention. Accordingly, yield may be
improved in an integrated circuit fabrication process, and
degradation of reliability such as HCD (Hot Carrier Degradation) by
degradation of the gate oxide film can be prevented.
* * * * *