U.S. patent application number 11/014483 was filed with the patent office on 2005-05-12 for floating gate and fabrication method therefor.
This patent application is currently assigned to NANYA TECHNOLOGY CORPORATION. Invention is credited to Chuang, Ying-Cheng, Huang, Chung-Lin, Lin, Chi-Hui.
Application Number | 20050101090 11/014483 |
Document ID | / |
Family ID | 29708525 |
Filed Date | 2005-05-12 |
United States Patent
Application |
20050101090 |
Kind Code |
A1 |
Chuang, Ying-Cheng ; et
al. |
May 12, 2005 |
Floating gate and fabrication method therefor
Abstract
A floating gate with multiple tips and a fabrication method
thereof. A semiconductor substrate is provided, on which a
patterned hard mask layer is formed, wherein the patterned hard
mask layer has an opening. A gate dielectric layer and a first
conducting layer with a first predetermined thickness are formed on
the bottom of the opening. A spacer is formed on the sidewall of
the opening. A conducting spacer is formed on the sidewall of the
spacer. The first conducting layer is etched to a second
predetermined thickness. A multi-tip floating gate is provided by
the first conducting layer and the conducting spacer. A protecting
layer is formed in the opening. The patterned hard mask layer, the
gate dielectric layer, a portion of the protecting layer, and a
portion of the first spacer are etched to expose the surface of the
first conducting layer.
Inventors: |
Chuang, Ying-Cheng; (Bade
City, TW) ; Huang, Chung-Lin; (Taichung, TW) ;
Lin, Chi-Hui; (Taipei, TW) |
Correspondence
Address: |
Richard P. Berg
c/o LADAS & PARRY
Suite 2100
5670 Wilshire Boulevard
Los Angeles
CA
90036-5679
US
|
Assignee: |
NANYA TECHNOLOGY
CORPORATION
|
Family ID: |
29708525 |
Appl. No.: |
11/014483 |
Filed: |
December 15, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11014483 |
Dec 15, 2004 |
|
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10441801 |
May 19, 2003 |
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6847068 |
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Current U.S.
Class: |
438/267 ;
257/E21.209; 257/E29.129 |
Current CPC
Class: |
H01L 29/42324 20130101;
H01L 29/40114 20190801 |
Class at
Publication: |
438/267 |
International
Class: |
H01L 021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 26, 2002 |
TW |
91116811 |
Claims
1-19. (canceled)
20. A floating gate, comprising: a conductive base, wherein a top
edge of the conductive base is tip-shaped; and a conductive
crescent-shaped protruding layer aligned with the tip-shaped
structure, wherein a bottom portion of the conductive protruding
layer is narrower than the conductive base, and a multi-tip
floating gate is provided by the conductive base and the conductive
protruding layer.
21. The floating gate of claim 20, wherein the conductive base is a
poly layer.
22. The floating gate of claim 20, wherein the conductive
protruding layer is a poly layer.
23. A floating gate, comprising: a conductive base, wherein a top
edge of the conductive base is tip-shaped, the conductive base has
a first sidewall and a second sidewall, the first sidewall parallel
to the second sidewall; and a conductive protruding layer having a
crescent-shaped structure, wherein the crescent-shaped structure is
aligned with the tip-shaped structure, a bottom portion of the
conductive protruding layer is connected to a top portion of the
conductive base, the bottom portion of the conductive protruding
layer is narrower than the conductive base, and a multi-tip
floating gate is provided by the conductive base and the conductive
protruding layer.
24. The floating gate of claim 23, wherein the conductive base is a
poly layer.
25. The floating gate of claim 23, wherein the conductive
protruding layer is a poly layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention is relates to a floating gate, and more
particularly to a floating gate with multiple tips and a
fabrication method thereof.
[0003] 2. Description of the Related Art
[0004] Memory devices for non-volatile storage of information are
currently in widespread use, in a myriad of applications. A few
examples of non-volatile semiconductor memory include read only
memory (ROM), programmable read only memory (PROM), erasable
programmable read only memory (EPROM), electrically erasable
programmable read only memory (EEPROM) and flash EEPROM.
[0005] An advantage of EPROM is electrical programmability, but for
erasing, EPROM requires exposure to ultraviolet (UV) light.
[0006] In many circuit designs it is desirable to have a
non-volatile memory device that can be erased and reprogrammed
in-circuit, without the need to remove the device.
[0007] EEPROM devices have the advantage of electrical programming
and erasing, achieved by charging and discharging actions
controlled by the control gate. The actions also affect the
conductivity of the channel between source and drain.
[0008] One of the advantages of flash memory is its capacity for
block-by-block memory erasure. Furthermore, memory erasure is fast,
normally taking just 1 to 2 seconds for the complete removal of a
whole block of memory. Another advantage of the flash memory is low
power consumption. The voltages of a control gate, a source, and a
drain are adjusted to program or erase in a split gate flash
memory.
[0009] FIGS. 1a to 1c are cross-sections of the conventional method
of fabricating a floating gate of a split gate flash memory.
[0010] In FIG. 1a, a silicon substrate 101 is provided. A gate
oxide layer 102, a doped polysilicon layer 103, and a nitride layer
104 having an opening 105 are sequentially formed on the silicon
substrate 101.
[0011] In FIG. 1b, the doped polysilicon layer 105 exposed by the
opening 105 is oxidized to form an oxide layer 106 with a Bird's
Beak shape edge.
[0012] In FIG. 1c, the nitride layer 104 is removed. The doped
polysilicon layer 103 is anisotropically etched to form a floating
gate 103a using the oxide layer 106 as an etching mask.
[0013] A split gate flash memory is completed after a control gate
is formed on the floating gate and the silicon substrate 101 is
implanted to form source/drain devices.
[0014] In the program step, high voltage is applied between the
source and drain. Another high voltage is applied to the control
gate and goes to the floating gate because of the electric capacity
coupling, and a high electric field is produced on the film gate
oxide layer. The electricity is injected into the floating gate
through the film gate oxide layer from the drain.
[0015] In the erase step, a high voltage is applied between the
drain and the control gate. A high electric field is produced on
the film gate oxide layer because of the electric capacity
coupling. The electricity injects into the drain through the film
gate oxide layer from the floating gate, such that the gate oxide
layer is damaged by the high voltage.
[0016] When the edge of the floating gate is a tip, the electric
field is easily concentrated in the tip, and the point is easily
discharged. If the point discharge is increased, the erase effect
is strong.
[0017] In addition, die size is larger due to the addition of
programming circuitry and there are more processing and testing
steps involved in the manufacture of these types of memory
devices.
SUMMARY OF THE INVENTION
[0018] The present invention is directed to a floating gate with
multiple tips and a fabrication method thereof.
[0019] Accordingly, the present invention provides a method for
forming a floating gate. A semiconductor substrate is provided. A
patterned hard mask layer with an opening is formed on the
semiconductor substrate. A gate dielectric layer and a first
conducting layer with a first predetermined thickness are formed on
the bottom of the opening. A spacer is formed on the sidewall of
the opening. A conducting spacer is formed on the sidewall of the
spacer. The first conducting layer is etched to a second
predetermined thickness. A multi-tip floating gate is provided by
the first conducting layer and the conducting spacer. A protecting
layer is formed in the opening. The patterned hard mask layer is
removed. The gate dielectric layer, the portion of the protecting
layer, and the portion of the first spacer are removed to expose
the surface of the first conducting layer.
[0020] Accordingly, the present invention also provides a method
for forming a floating gate. A semiconductor substrate is provided,
with a dielectric layer, a hard mask layer, and a patterned resist
layer sequentially formed thereon. The hard mask layer is etched to
form an opening using the patterned resist layer as a mask, wherein
the opening exposes the surface of the semiconductor substrate. The
patterned resist layer is removed. A gate dielectric layer is
formed on the exposed surface of the semiconductor substrate. A
first poly layer is formed on the hard mask layer, and the opening
is filled with the first poly layer. The first poly layer is
chemical mechanical polished to expose the surface of the hard mask
layer. The first poly layer in the opening is etched to a first
predetermined thickness. An insulating layer is conformally formed
on the surface of the hard mask layer and the opening. The
insulating layer is anisotropically etched to form a first spacer
on the sidewall of the opening. A second poly layer is conformally
formed on the surface of the hard mask layer and the opening. The
second poly layer is anisotropically etched to form a second spacer
on the sidewall of the first spacer, wherein the second spacer
covers the surface of the first spacer. The first conducting layer
is etched to a second predetermined thickness. A multi-tip floating
gate is provided by the first conducting layer and the second
spacer. A protecting layer is formed in the opening. The patterned
resist layer is removed. A protecting layer is formed in the
opening. The patterned resist layer, the first oxide layer, the
portion of the protecting layer, and the portion of the first
spacer are removed to expose the surface of the first conducting
layer.
[0021] Accordingly, the present invention provides a floating gate.
The floating gate comprises a conductive base and a conductive
protruding layer, wherein the edge of the conductive base is
tip-shaped, and the conductive protruding layer is crescent-shaped.
The crescent-shaped structure is aligned with the tip-shaped
structure, the bottom portion of the conductive protruding layer is
narrower than the top portion of the conductive base, and a
multi-tip floating gate is provided by the conductive base and the
conductive protruding layer.
[0022] Accordingly, the present invention also provides a floating
gate. The floating gate comprises a conductive base and a
conductive protruding layer. The top edge of the conductive base is
tip-shaped. The conductive base has a first sidewall and a second
sidewall, wherein the first sidewall is parallel to the second
sidewall. The conductive protruding layer is crescent-shaped,
wherein the crescent-shaped structure is aligned with the
tip-shaped structure. The bottom portion of the conductive
protruding layer connects to the top portion of the conductive
base, wherein the bottom portion of the conductive protruding layer
is narrower than the conductive base, and a multi-tip floating gate
is provided by the conductive base and the conductive protruding
layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] For a better understanding of the present invention,
reference is made to a detailed description to be read in
conjunction with the accompanying drawings, in which:
[0024] FIGS. 1a to 1c are cross-sections of a conventional method
for fabricating a floating gate of a split gate flash memory;
[0025] FIGS. 2a to 2m are cross-sections of a method for
fabricating a floating gate of a split gate flash memory of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0026] A method for forming a multi-tip floating gate according to
the present invention is shown in FIGS. 2a to 2m.
[0027] In FIG. 2a, a semiconductor substrate 201, such as silicon
substrate, is provided. A dielectric layer 202, such as pad oxide
layer, a hard mask layer 203, such as silicon nitride layer, and a
patterned resist layer 204 having an opening 205 are sequentially
formed on the surface of the semiconductor substrate 201, wherein a
multi-tip floating gate is formed in the opening 205 in subsequent
process. The surface of the hard mask layer 203 is exposed by the
opening 205.
[0028] In FIG. 2b, the hard mask layer 203 and the dielectric layer
are sequentially etched to form an opening 206 using the patterned
resist layer 204 as a mask, and the opening 206 exposes the surface
of the semiconductor substrate 201.
[0029] In FIG. 2c, a gate dielectric layer 207, such as gate oxide
layer, is formed on the exposed surface of the semiconductor
substrate 201. The gate oxide layer is a high quality oxide layer,
and the gate oxide layer is usually formed by thermal
oxidation.
[0030] In FIG. 2a first conducting layer 208, such as a poly layer,
is formed on the surface of the hard mask layer 203, wherein the
opening 206 is filled with the first conducting layer 208.
[0031] In FIG. 2e, the first conducting layer 208 is planarized to
expose the surface of the hard mask layer 203, and the first
conducting layer 208a in the opening 206 remains. Planarization
uses chemical mechanical polishing (CMP).
[0032] In FIG. 2f, the first conducting layer 208a is etched to
form a first conducting layer 208b and an opening 209, wherein the
thickness of the first conducting layer 208b is a predetermined
thickness determined as required, but does not expose the surface
of the gate dielectric layer 207.
[0033] An insulating layer 210 is conformally formed on the surface
of the hard mask layer 203, such as silicon oxide layer, and the
opening 209, wherein the material of the insulating layer 210 is
different from that of the hard mask layer 203.
[0034] In FIG. 2g, the insulating layer 210 is anisotropically
etched to form a first spacer 210a, wherein the hard mask layer 203
is not damaged.
[0035] In FIG. 2h, a second conducting layer 211, such as a poly
layer, is formed on the surface of the hard mask layer 203, wherein
the opening 209 is filled with the second conducting layer 211, and
the second conducting layer 211 connects to the exposed first
conducting layer 208b.
[0036] In FIG. 2i, the second conducting layer 211 is
anisotropically etched to form a second spacer 211a, and the
exposed first conducting layer 208b is etched to a predetermined
thickness to form a concave first conducting layer 208c. The second
spacer 211a covers the sidewall of the first spacer 210a and
connects to the first conducting layer 208c.
[0037] In FIG. 2j, a protecting layer 212, such as a silicon oxide
layer, is formed on the hard mask layer 203, wherein the opening
209 is filled with the protecting layer 212, and the material of
the protecting layer 212 is different from that of the hard mask
layer 203.
[0038] In FIG. 2k, the protecting layer 212 is planarized to expose
the surface of the hard mask layer 203, wherein the protecting
layer 212 in the opening 209 remains, and the hard mask layer 203
is removed.
[0039] In FIG. 2l, the first oxide layer 202, the portion of
protecting layer 212, and the portion of first spacer 210 are
removed to expose the end of the second spacer 211a, such that a
multi-tip floating gate 213 is provided by the first conducting
layer 208c and the second conducting layer 211.
[0040] The floating gate 213 comprises a conductive base 208c and a
conductive protruding layer 211a. The edge of the conductive base
208c is tip-shaped. The conductive base 208c has a first sidewall
and a second sidewall, wherein the fist sidewall is parallel to the
second sidewall. The conductive protruding layer 211a is formed on
the conductive base 208c, wherein the bottom portion of the
conductive protruding layer 211a connects to the top portion of the
conductive base 208c, and the bottom portion of the conductive
protruding layer 211a is narrower than the top portion of the
conductive base 208c. The top portion of the conductive protruding
layer 211a is crescent-shaped, and the crescent-shaped structure is
aligned with the tip-shaped structure.
[0041] In FIG. 2m, a gate dielectric layer 214, such as oxide
layer, and a control gate 215 are sequentially formed on the
multi-tip floating gate 213 as shown in FIG. 2l, and fabrication of
the flash memory is thus complete.
[0042] Electric field concentration easily occurs at the tip, and
the point is easily discharged. The effect of point discharge is
increased by the floating gate's multiple tips in the present
invention. Therefore, data erase for the flash memory having the
floating gate with multiple tips is increased.
[0043] While the invention has been described by way of example and
in terms of the preferred embodiments, it is to be understood that
the invention is not limited to the disclosed embodiments. To the
contrary, it is intended to cover various modifications and similar
arrangements (as would be apparent to those skilled in the art).
Therefore, the scope of the appended claims should be accorded the
broadest interpretation so as to encompass all such modifications
and similar arrangements.
* * * * *