U.S. patent application number 11/003204 was filed with the patent office on 2005-05-12 for method and system for minimizing differential amplifier power supply sensitivity.
Invention is credited to Perner, Frederick, Smith, Kenneth.
Application Number | 20050099234 11/003204 |
Document ID | / |
Family ID | 21797570 |
Filed Date | 2005-05-12 |
United States Patent
Application |
20050099234 |
Kind Code |
A1 |
Perner, Frederick ; et
al. |
May 12, 2005 |
Method and system for minimizing differential amplifier power
supply sensitivity
Abstract
The invention includes an apparatus and a method for minimizing
power supply sensitivity of a differential amplifier. The apparatus
includes a current source providing a differential amplifier bias
current to a common source node of the differential amplifier. A
voltage sensor senses variations of a power supply associated with
the current source. Variations sensed by the voltage sensor control
a magnitude of the differential amplifier bias current. The method
includes a current source providing the source current. A voltage
potential of the common source node is sensed. The current source
is adjusted depending upon the sensed voltage potential of the
common source node, thereby adjusting a magnitude of the source
current.
Inventors: |
Perner, Frederick; (Palo
Alto, CA) ; Smith, Kenneth; (Boise, ID) |
Correspondence
Address: |
HEWLETT-PACKARD COMPANY
Intellectual Property Administration
P. O. Box 272400
Fort Collins
CO
80527-2400
US
|
Family ID: |
21797570 |
Appl. No.: |
11/003204 |
Filed: |
December 3, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11003204 |
Dec 3, 2004 |
|
|
|
10020255 |
Dec 14, 2001 |
|
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Current U.S.
Class: |
330/261 ;
G9B/27.026; G9B/27.029 |
Current CPC
Class: |
G11B 27/22 20130101;
H04N 21/4305 20130101; G11B 27/28 20130101; G11B 27/034
20130101 |
Class at
Publication: |
330/261 |
International
Class: |
H03F 003/45 |
Claims
1-16. (canceled)
17. A method for minimizing power supply sensitivity of a
differential amplifier, the differential amplifier conducting a
source current at a common source node, the method comprising: a
current source providing the source current; sensing a voltage
potential of the common source node; adjusting the current source
depending upon the sensed voltage potential of the common source
node, thereby adjusting a magnitude of the source current.
18. The method for minimizing power supply sensitivity of a
differential amplifier of claim 17, wherein the current source
comprises a current mirror, adjusting the current source comprises
adjusting a bias current of the current mirror.
19. The method for minimizing power supply sensitivity of a
differential amplifier of claim 18, wherein the current mirror
comprises an amplifier bias current transistor and a mirror
transistor.
20. The method for minimizing power supply sensitivity of a
differential amplifier of claim 19, wherein adjusting the current
source comprises adjusting at least one of an amplifier bias
current transistor back gate bias, and a mirror transistor back
gate bias.
21. The method for minimizing power supply sensitivity of a
differential amplifier of claim 19, wherein adjusting the current
source comprises adjusting characteristics of the amplifier bias
current transistor.
22. The method for minimizing power supply sensitivity of a
differential amplifier of claim 21, wherein the amplifier bias
current transistor comprises a plurality of sub-bias current
transistors, and adjusting characteristics of the amplifier bias
current transistor comprises controlling an inclusion of a number
of parallel sub-bias current transistors, wherein each included
sub-bias current transistors contributes to the differential
amplifier bias current.
23. The method for minimizing power supply sensitivity of a
differential amplifier of claim 21, wherein the amplifier bias
current transistor comprises a plurality of sub-bias current
transistors, and adjusting characteristics of the amplifier bias
current transistor comprises adjusting a bias of the parallel bias
current transistor, wherein the parallel bias current transistor
contributes to the differential amplifier bias current.
24. (canceled)
25. (canceled)
Description
FIELD OF THE INVENTION
[0001] The invention relates generally to electronic amplifiers.
More particularly, the invention relates to a method and apparatus
for minimizing differential amplifier power supply sensitivity.
BACKGROUND OF THE INVENTION
[0002] Computing devices require memory. The memory can include
read only memory (ROM) or random access memory (RAM). Generally,
memory includes memory cells that are arranged in rows and columns.
The individual memory cells are accessed through the use of row
select lines and column select lines, typically referred to as word
lines and bit lines.
[0003] Typically, sense amplifiers are connected to the bit lines
for sensing a state of memory cells connected to the bit lines. The
sense amplifiers generally each include a differential amplifier.
FIG. 1 shows a differential amplifier 100 and an associated current
source 130.
[0004] The typical differential amplifier of FIG. 1 includes four
transistors 110, 112, 114, 116. Input transistors 110, 112 receive
differential voltage inputs (VIN+, VIN-). An output (VOUT) is
generated across an output transistor 114. The differential
amplifier conducts current through a common source node 120.
[0005] Generally, the current source 130 is connected to the common
source node 120 to provide the differential amplifier with a proper
bias current. The current source 130 can include a current mirror.
A first transistor 132 mirrors current flowing through a second
transistor 134. A current source 136 determines the current flowing
through the second transistor 134, and therefore, the current
flowing through the first transistor 132, and therefore, the
current flowing through the common source node 120. As a result,
the current source 136 (ISOURCE) sets the bias current of the
differential amplifier 100.
[0006] The current source 130 and the differential amplifier
implementation shown in FIG. 1 include P-channel transistors. An
analogous N-channel current source and differential amplifier
implementation is also possible.
[0007] A liability of the current source 130, differential
amplifier combination of FIG. 1, is that variations of the power
supply VDD tend to cause variations of a voltage potential of the
common source node 120. The bias current provided by the current
source 130 can vary as the power supply voltage VDD varies. The
current variance of the current source 130 causes the voltage
potential of the common source node 120 to vary. Variations of the
voltage potential of the common source node 120 tend to cause
voltage variations of the output (VOUT). The net result is that the
output (VOUT) is sensitive to variations of the power supply
voltage VDD.
[0008] The previously mentioned MRAM sense amplifiers require a
minimization of power supply sensitivity. MRAM circuitry selects
and isolates individual MRAM memory cells within large
two-dimensional arrays of MRAM cells. An embodiment of an MRAM
sense amplifier is similar to the differential amplifier of FIG. 1,
and interfaces with the MRAM selection circuitry. The MRAM sense
amplifier relies on sensitivity and power supply rejection. Small
voltage variations of the common source node 120 can cause errors
or system correction actions that affect the performance of the
sense operations of the MRAM circuits. Minimizing the power supply
sensitivity improves the reliability and performance of the MRAM
sense circuits.
[0009] It should be noted that other types of RAM (for example,
SRAM and DRAM) do not require the power supply sensitivity required
by MRAM because other types of memory generally operate with much
larger sense signals.
[0010] It is desirable to have a method and apparatus for
minimizing power supply sensitivity of differential amplifiers. It
is desirable that the method and apparatus be adaptable for use
with MRAM sense amplifiers.
SUMMARY OF THE INVENTION
[0011] The invention includes an apparatus and method for
minimizing power supply sensitivity of differential amplifiers. The
method and apparatus are adaptable for use with MRAM sense
amplifiers.
[0012] An embodiment of the invention includes an apparatus for
minimizing power supply sensitivity of a differential amplifier.
The apparatus includes a current source providing a differential
amplifier bias current to a common source node of the differential
amplifier. A voltage sensor senses variations of a power supply
associated with the current source, and the differential amplifier.
Variations sensed by the voltage sensor control a magnitude of the
differential amplifier bias current.
[0013] Another embodiment of the invention includes a method for
minimizing power supply sensitivity of a differential amplifier.
The differential amplifier conducts a source current at a common
source node. The method includes a current source providing the
source current. A voltage potential of the common source node is
sensed. The current source is adjusted depending upon the sensed
voltage potential of the common source node, thereby adjusting a
magnitude of the source current.
[0014] Other aspects and advantages of the present invention will
become apparent from the following detailed description, taken in
conjunction with the accompanying drawings, illustrating by way of
example the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 shows a prior art differential amplifier and an
associated current source supply.
[0016] FIG. 2 shows a differential amplifier and corresponding
current source according to an embodiment of the invention.
[0017] FIG. 3 shows a differential amplifier and corresponding
current source according to another embodiment of the
invention.
[0018] FIG. 4A shows a P-channel differential amplifier and a
corresponding P-channel current source according to another
embodiment of the invention.
[0019] FIG. 4B shows an N-channel differential amplifier and a
corresponding N-channel current source according to another
embodiment of the invention.
[0020] FIG. 5 shows a differential amplifier and corresponding
current source according to another embodiment of the
invention.
[0021] FIG. 6 shows a differential amplifier and corresponding
current source according to another embodiment of the
invention.
[0022] FIG. 7 shows a substrate that includes a P-channel
transistor and an N-channel transistor in which the transistors
include a back gate bias.
[0023] FIG. 8 shows a differential amplifier and corresponding
current source according to another embodiment of the
invention.
[0024] FIG. 9 shows a differential amplifier and corresponding
current source according to another embodiment of the
invention.
[0025] FIG. 10 shows acts according to an embodiment of the
invention.
[0026] FIG. 11 shows an MRAM system according to an embodiment of
the invention.
[0027] FIG. 12 shows a computer system according to an embodiment
of the invention.
DETAILED DESCRIPTION
[0028] As shown in the drawings for purposes of illustration, the
invention is embodied in a method and apparatus for reducing supply
voltage sensitivity of a differential amplifier.
[0029] FIG. 2 shows a differential amplifier 210 and corresponding
current source 220 according to an embodiment of the invention. The
current source 220 of this embodiment provides a differential
amplifier bias current (ISOURCE) to a common source node 230 of the
differential amplifier 210. A voltage sensor 240 senses variations
of a voltage potential of a power supply (VDD) associated with the
current source 220. Voltage potential variations sensed by the
voltage sensor 240 control a magnitude of the differential
amplifier bias current. The current source 220 is adjustable. That
is, the current flowing to or from the current source 220 can be
adjustably varied.
[0030] As previously described, voltage potential variations of the
power supply voltage (VDD) generally causes a corresponding voltage
potential variation of the common source node 230. The voltage
potential variation of the common source node 230 subsequently
causes a voltage variation to be coupled to the output (VOUT) of
the differential amplifier 210. Voltage potential variations of the
common source node 230 can be contradicted by the current source
220.
[0031] Generally, the differential amplifier 210 includes at least
a pair of transistors. The transistors are typically connected to
the common source node 230, and conduct current from the common
source node 230. Current is provided to the common source node 230
by the current source 220. The current source 220 can include a
current mirror that mirrors a current mirror bias current. The
current mirror bias current can be adjustable.
[0032] The voltage sensor 240 includes a reference voltage VREF.
The voltage sensor compares a received voltage potential (here, the
received voltage potential is VDD) with the reference voltage VREF,
and generates an output control that is proportional to the voltage
potential difference. Therefore, variations of the received voltage
potential influence the output control. Voltage sensors are well
know in the art of electronics.
[0033] The following described embodiments of the invention include
the received voltage potential being the power supply voltage VDD.
It is to be understood that any voltage potential that
proportionally represents the power supply voltage VDD can be
substituted as the received voltage potential.
[0034] An adjustable current source, like the adjustable current
source 220, is well know in the art of electronics.
[0035] Generally, power supply (VDD) sensitivity of the
differential amplifier 210 is dependent upon the power supply
sensitivity of the current source 220 connected to the differential
amplifier 210. Variations of the current source 220 due to the
power supply VDD cause voltage potential variations of the common
source node 230 of the differential amplifier 210, which in turn,
cause voltage potential variations in the output (VOUT) of the
differential amplifier 210.
[0036] The relationships between the power supply VDD, the current
source 220 and variations in the differential amplifier output
(VOUT) can modeled by the following equation:
delta Vs=KV*(delta VDD)+KI*(delta I),
[0037] where delta Vs represents the variations in the differential
amplifier output voltage, KV is a multiplier relationship between
the power supply voltage VDD and the differential amplifier output
voltage (VOUT), delta VDD represents variations in the power supply
voltage VDD, KI is a multiplier relationship between the current
source 220 and the differential amplifier output voltage (VOUT),
and delta I represents variations in the current source 220.
[0038] The invention includes controlling KI to minimize delta Vs.
For example, if KI can be controlled to be:
KI=-KV((delta VDD)/(delta I),
[0039] then delta Vs in the above equation is forced to zero,
thereby minimizing the sensitivity of the differential amplifier
output to variations of the power supply. The invention includes
several different methods for controlling KI.
[0040] FIG. 3 shows a differential amplifier 210 and corresponding
current source according to another embodiment of the invention.
The current source of this embodiment includes a current mirror.
The current mirror includes an amplifier bias current transistor
330 and a mirror transistor 320.
[0041] Current flowing through the mirror transistor 320 is
determined by a current source 310. As previously described, the
voltage sensor 240 generates a control output that is dependent
upon variations of the power supply voltage VDD.
[0042] Variations of the power supply voltage cause the output of
the voltage sensor 240 to adaptively vary the bias current (IBIAS)
of the current source 310. The current flowing through the mirror
transistor 320 is proportionally varied. Therefore, the current
flowing through the amplifier bias current transistor 330 also
proportionally varies, which proportionally varies the current
(ISOURCE) flowing through the common source node (VNODE) of the
differential amplifier 210.
[0043] The inclusion of the current mirror providing current to the
common source node (VNODE) rather than the current source providing
current directly to the common source node provides an advantage
that current can be provided to many common source nodes
simultaneously. That is, many amplifier bias current transistors
330 can simultaneously source current to a corresponding common
source node of many different differential amplifiers.
Additionally, the current mirror and current source combination of
FIG. 3 is easy to control, and provides a wide dynamic range for
the bias control.
[0044] FIG. 4A shows a P-channel differential amplifier and a
corresponding P-channel current source according to another
embodiment of the invention. This embodiment is similar to the
embodiment of FIG. 3, but includes details of an embodiment of the
differential amplifier 210.
[0045] FIG. 4B shows an N-channel differential amplifier and a
corresponding N-channel current source according to another
embodiment of the invention. This embodiment is similar to the
embodiment of FIG. 3, but includes details of an embodiment of the
differential amplifier 210, and depicts an N-channel implementation
of the current source.
[0046] The embodiments of FIG. 4A and FIG. 4B have been included to
show that all of the embodiments of the invention can be
implemented with either P-channel or N-channel transistors. The
following embodiments include P-channel transistors. Analogous to
the embodiments of FIG. 4A and FIG. 4B, corresponding N-channel
transistor implementations are possible with the following
embodiments.
[0047] FIG. 5 shows a differential amplifier 210 and corresponding
current source according to another embodiment of the invention.
This embodiment includes additionally controlling current flow
through mirror transistor by controlling a back bias of the mirror
transistor 510.
[0048] The back bias of the mirror transistor 510 provides
additional control of the current conducted by the mirror
transistor 510. The current conducted by the mirror transistor 520
is initially determined by the fixed current source 505. The
voltage sensor 240 provides additional control of the current
conducted by the mirror transistor by controlling the back gate
bias of the mirror transistor 510. As previously described, the
voltage sensor 240 control is determined by variation of the power
supply voltage VDD.
[0049] Current conducted by the amplifier bias current transistor
520 mirrors the current conducted by the mirror transistor 510. The
current conducted by the amplifier bias current transistor 520
determines the common source node current (ISOURCE) of the
differential amplifier 210, which influences the cornrnon source
node (VNODE) voltage potential. As previously described, the common
source node (VNODE) voltage potential influences the voltage
potential VOUT.
[0050] The voltage sensor 240 control of the back gate of the
mirror transistor 510 indirectly controls the common source current
(ISOURCE), and therefore, the voltage potential of the common
source node (VNODE), and therefore, the voltage potential of the
output voltage (VOUT), based upon variations of the power supply
voltage VDD.
[0051] FIG. 6 shows a differential amplifier and corresponding
current source according to another embodiment of the invention.
This embodiment includes controlling current flow through the
amplifier bias current transistor 620 by controlling a back bias of
the amplifier bias current transistor 620.
[0052] The back bias of the amplifier bias current transistor 620
provides additional control of the current conducted by the
amplifier bias current transistor 620. The current conducted by the
amplifier bias current transistor 620 is initially determined by
the current conducted by the mirror transistor 610, and therefore,
by the fixed current source 605. The voltage sensor 240 provides
additional control of the current conducted by the amplifier bias
current transistor 620 by controlling the back gate bias of the
amplifier bias current transistor 620. As previously described, the
voltage sensor 240 control is determined by variation of the power
supply voltage VDD.
[0053] Current conducted by the amplifier bias current transistor
620 mirrors the current conducted by the mirror transistor 610. The
current conducted by the amplifier bias current transistor 620
determines the common source node current (ISOURCE) of the
differential amplifier 210, which influences the common source node
(VNODE) voltage potential. As previously described, the common
source node (VNODE) voltage potential influences the voltage
potential VOUT.
[0054] The voltage sensor 240 control of the back gate of the
amplifier bias current transistor 620 directly controls the common
source current (ISOURCE), and therefore, the voltage potential of
the common source node (VNODE), and therefore, the voltage
potential of the output voltage (VOUT), based upon variations of
the power supply voltage VDD.
[0055] Back Gate Bias
[0056] FIG. 7 shows a substrate that includes a PMOS 710 and an
NMOS transistor 720, in which voltages applied to back gate control
terminals 712, 722 provide a back gate bias to each of the
transistors 710, 720. Voltages applied to the back gate control
terminal can be biased to influence current flow through each of
the transistors 710, 720.
[0057] As with most transistors, a voltage potential can be applied
to the gates 713, 723 of the transistors 710, 720 to cause charge
to be collected in the channels 714, 724 of the transistors 710,
720 causing the transistors to conduct current.
[0058] A voltage potential can be applied to the back gates 712,
722 (or bulk) of the transistors 710, 720 to additionally control
the charge collected by the channels 714, 724 of the transistors
710, 720, which additionally controls the current conducted by the
transistors 710, 720.
[0059] The embodiments of FIG. 5 and FIG. 6, utilize the back gate
bias of the mirror transistor or the amplifier bias current
transistor to provide additional control of the common source
current (ISOURCE).
[0060] FIG. 8 shows a differential amplifier 210 and corresponding
current source according to another embodiment of the invention.
For this embodiment, the amplifier bias current transistor 820 is
implemented in parallel with several sub-amplifier bias current
transistors 810.
[0061] The output control of the voltage sensor 240 is connected to
the sub-amplifier bias current transistors 810. The connection can
include several control lines in which each control line is
connected to a corresponding sub-amplifier bias current transistor.
The control line determines which of the sub-amplifier bias current
transistors 810 are conducting, and which of the sub-amplifier bias
current transistors 810 are not conducting. The conducting
sub-amplifier bias current transistors 810 contribute to the common
source current (ISOURCE). The voltage sensor 240 controls the
common source current (ISOURCE), determining which of the
sub-amplifier bias current transistors 810 are turned on to
conduct.
[0062] The common source current (ISOURCE) is initially determined
by the current source 805 through the current mirror formed by the
mirror transistor 830 and the amplifier bias current transistor
820. The common source current (ISOURCE) is additionally controlled
by the voltage sensor 240 controlling which of the sub-amplifier
bias current transistors 810 are conducting. The connection between
the voltage sensor 240 and the sub-amplifier bias current
transistors 810 can be a digital bus.
[0063] FIG. 9 shows a differential amplifier 210 and corresponding
current source according to another embodiment of the invention.
This embodiment is similar to the embodiment of FIG. 8. However,
rather than several sub-amplifier bias current transistors 810
providing control of the common source current (ISOURCE), a single
sub-amplifier bias current transistor 910 is included. The single
sub-amplifier bias current transistor 910 is controlled by an
analog control line ftom the voltage sensor 240. The voltage sensor
240 provides a voltage potential to the gate of the single
sub-amplifier bias current transistor 910, and therefore,
determines the amount of current conducted by the single
sub-amplifier bias current transistor 910.
[0064] The common source current (ISOURCE) is initially determined
by the current source 905 through the current mirror formed by the
mirror transistor 930 and the amplifier bias current transistor
920. The common source current (ISOURCE) is additionally controlled
by the voltage sensor 240 controlling how much current is conducted
by the single sub-amplifier bias current transistor 910. The
connection between the voltage sensor 240 and the sub-amplifier
bias current transistors 910 can be an analog line.
[0065] FIG. 10 shows acts according to an embodiment of the
invention. The embodiment includes a method for minimizing power
supply sensitivity of a differential amplifier. The differential
amplifier conducts a source current at a common source node.
[0066] A first step 1010 includes a current source providing a
source current.
[0067] A second step 1020 includes sensing a voltage potential of a
common source node.
[0068] A third step 1030 includes adjusting the current source
depending upon the sensed voltage potential of the common source
node, thereby adjusting a magnitude of the source current.
[0069] FIG. 11 shows an MRAM system according to an embodiment of
the invention. The MRAM system includes an array 1210 of MRAM cells
arranged in rows and columns. A particular MRAM cell is selected by
a row select unit 1220 and a column select unit 1230. Row and
column selection of MRAM cells is known in the art of electronics.
A sense line or bit line associated with a column selection within
the MRAM array 1210 can be connected to a differential sense
amplifier that includes a differential amplifier, current source
combination according to an embodiment of the invention.
[0070] As previously mentioned, the sense signals of MRAM typically
include voltage amplitudes that are much smaller than other types
of RAM (such as, DRAM and SRAM). The small amplitudes make the
sensed signals more susceptible to noise, distortion and
interference. Therefore, the voltage sensitivity and power supply
rejection provided by embodiments of the invention are very useful
in MRAM sensing applications.
[0071] FIG. 12 shows a computer system according to an embodiment
of the invention. This system includes a central processing unit
1310 that interfaces with an MRAM system of FIG. 11. MRAM provides
features that are desirable in computer systems. For example, MRAM
is non-volatile, which is useful in some computer applications.
[0072] Although specific embodiments of the invention have been
described and illustrated, the invention is not to be limited to
the specific forms or arrangements of parts so described and
illustrated. The invention is limited only by the appended
claims.
* * * * *