U.S. patent application number 10/994027 was filed with the patent office on 2005-04-21 for low latency buffer control system and method.
Invention is credited to Kahn, Opher D., Naveh, Alon, Wilcox, Jeffrey R..
Application Number | 20050086420 10/994027 |
Document ID | / |
Family ID | 29249096 |
Filed Date | 2005-04-21 |
United States Patent
Application |
20050086420 |
Kind Code |
A1 |
Wilcox, Jeffrey R. ; et
al. |
April 21, 2005 |
Low latency buffer control system and method
Abstract
A memory controller (MC) includes a buffer control circuit (BCC)
to enable/disable buffers coupled to a terminated bus. The BCC can
detect transactions and speculatively enable the buffers before the
transaction is completely decoded. If the transaction is targeted
for the terminated bus, the buffers will be ready to drive signals
onto the terminated bus by the time the transaction is ready to be
performed, thereby eliminating the "enable buffer" delay incurred
in some conventional MCs. If the transaction is not targeted for
the terminated bus, the BCC disables the buffers to save power. In
MCs that queue transactions, the BCC can snoop the queue to find
transactions targeted for the terminated bus and begin enabling the
buffers before these particular transactions are fully decoded.
Inventors: |
Wilcox, Jeffrey R.; (Folsom,
CA) ; Kahn, Opher D.; (Zichron-Yacov, IL) ;
Naveh, Alon; (Ramat Hasharon, IL) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD
SEVENTH FLOOR
LOS ANGELES
CA
90025-1030
US
|
Family ID: |
29249096 |
Appl. No.: |
10/994027 |
Filed: |
November 19, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10994027 |
Nov 19, 2004 |
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10133908 |
Apr 25, 2002 |
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6842831 |
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Current U.S.
Class: |
711/100 ;
710/310 |
Current CPC
Class: |
Y02D 10/00 20180101;
G06F 13/1615 20130101; Y02D 10/14 20180101 |
Class at
Publication: |
711/100 ;
710/310 |
International
Class: |
G06F 012/00 |
Claims
What is claimed is:
1. A method, comprising: monitoring a first bus for transactions;
enabling at least one buffer when a transaction is detected, the at
least one buffer to drive a signal on a second bus; determining
whether the detected transaction is a memory transaction; and
disabling the at least one buffer if the transaction is not a
memory transaction.
2. The method of claim 1, further comprising decoding the detected
transaction.
3. The method of claim 1, further comprising storing the detected
transaction in a storage element.
4. The method of claim 1, terminating the second bus to a mid-range
voltage.
5. An apparatus, comprising: means for monitoring a first bus for
transactions; a buffer to drive a signal on a targeted memory bus;
means for enabling the buffer when a transaction is detected; means
for determining whether the detected transaction is a transaction
for a device coupled to the targeted memory bus; and means for
disabling the buffer if the detected transaction is determined not
to be a transaction for a device coupled to the targeted memory
bus.
6. The apparatus of claim 5, further comprising means for receiving
the transaction.
7. The apparatus of claim 6, wherein the means for receiving
includes a storage device.
8. The apparatus of claim 5, wherein the second bus is terminated
to a mid-range voltage.
9. A method, comprising: monitoring a transaction queue; decoding a
transaction in the transaction queue; determining whether the
decoded transaction is a memory transaction; and disabling at least
one buffer coupled to a memory bus if the transaction is not a
memory transaction.
10. The method of claim 9, further comprising presenting a high
impedance to the memory bus when the buffer is disabled.
11. The method of claim 9, further comprising terminating the
memory bus to a mid-range voltage.
12. A method, comprising: monitoring a first bus to detect
transactions; storing detected transactions in a queue; decoding a
transaction being output by the queue; determining whether the
decoded transaction is targeted for a memory bus; enabling at least
one buffer if not already enabled if the decoded transaction is
targeted for the memory bus, the at least one buffer being coupled
to the memory bus; and disabling the at least one buffer if the
decoded transaction is not targeted for the memory bus.
13. The method of claim 12, further comprising delaying performance
of the decoded transaction until after enabling the at least one
buffer.
14. The method of claim 13, further comprising: performing the
decoded transaction; and disabling the at least one buffer after
performing the decoded transaction.
15. A method, comprising: monitoring a first bus to detect
transactions; storing detected transactions in a queue; decoding a
transaction being output by the queue; determining whether the
transaction is a memory transaction; determining whether a
plurality of buffers are enabled, wherein the plurality of buffers
are coupled to a second bus; enabling the plurality of buffers if
the transaction is a memory transaction; determining whether the
transactions stored in queue are memory transactions; and disabling
the plurality of buffers if the transaction is not a memory
transaction.
16. The method of claim 15, further comprising disabling the
plurality of buffers after performing the memory transaction.
17. The method of claim 16, further comprising the plurality of
buffers presenting a high impedance to the memory bus.
18. The method of claim 17, further comprising terminating the
memory bus to a mid-range voltage.
19. The method of claim 16, further comprising decoding the memory
transaction.
20. The method of claim 19, further comprising enabling the
plurality of buffers while the memory transaction is being
decoded.
21. A system comprising: a processor; a synchronous dynamic random
access memory (SDRAM); a memory controller coupled to the processor
and to the SDRAM, wherein the memory controller includes: a
plurality of buffers coupled to a terminated memory bus; a decoder
to decode a transaction sent by the processor; and a buffer control
circuit, coupled to the decoder and the plurality of buffers, to
detect the transaction and, in response thereto, to enable the
plurality of buffers before the decoder completes decoding the
transaction, wherein the buffer control circuit is configurable to
determine whether the transaction is a memory transaction and to
disable the plurality of buffers if the transaction is not a memory
transaction.
22. The system of claim 21, wherein the memory controller further
comprises a transaction store coupled to the decoder.
23. The system of claim 22, wherein the transaction store comprises
a queue.
24. A system comprising: a processor; a synchronous dynamic random
access memory (SDRAM); a memory controller coupled to the processor
and the SDRAM, wherein the memory controller includes: a plurality
of buffers coupled to a memory bus, the memory bus being terminated
to a mid-range voltage; a transaction store to store transactions
sent by the processor; a decoder coupled to the transaction store
to decode a transaction being output by the transaction store; and
a buffer control circuit coupled to the transaction store and the
plurality of buffers, wherein the buffer control circuit is
configurable to disable the plurality of buffers after the
transaction is performed if the transaction store does not contain
other transactions targeted for the terminated memory bus, wherein
the buffer control circuit is further configurable to determine
whether a decoded transaction from the transaction store is
targeted for the memory bus and in response thereto enable the
plurality of buffers if they are not already enabled.
25. The system of claim 24, wherein the buffer control circuit is
further configurable to allow the plurality of buffers to remain
enabled after the transaction is performed if the transaction store
does contain a transaction targeted for the memory bus.
26. The system of claim 24, wherein the transaction store comprises
a queue.
27. The system of claim 24, wherein the buffer control circuit is
further configurable to delay performance of the decoded
transaction after enabling the plurality of buffers.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present invention is a Continuation of Application Ser.
No. 10/133,908, filed Apr. 25, 2002.
FIELD OF THE INVENTION
[0002] The present invention relates to electronic circuitry and,
more particularly, to buffer circuits for use with memories.
BACKGROUND
[0003] Memory controller circuits can be used in a variety of
computer systems (e.g., desktop personal computers, notebook
computers, personal digital assistants, etc.) to facilitate the
computer system's processor in accessing memory chips. These memory
chips generally include the main memory of the computer system,
which typically includes several dynamic random access memory
(DRAM) chips. DRAM chips include, for example, synchronous DRAM
(SDRAM), extended data out (EDO) DRAM, Rambus (R)DRAM, DDR (double
data rate) and DRAM chips. The memory controller typically includes
a memory interface for communicating with one or more of such DRAM
chips via a memory bus. The memory controller includes buffers to
drive signals onto the memory bus. In addition, the memory
controller typically includes a system interface to communicate
with system processor(s) via a system bus. The memory controller
uses these interfaces to route data between the processor and the
DRAM chips using appropriate address, control and data signals.
[0004] In some systems, the memory bus is terminated with resistors
to a mid-range voltage. As a result, if the output buffers are
enabled (i.e., pulling up or pulling down the voltage of the memory
bus lines) during idle periods, the buffers dissipate power during
the idle periods. This power dissipation is undesirable in many
applications.
[0005] One method of reducing power dissipation by the buffers
during idle periods is to implement the buffers as three-state
buffers that present a high impedance to the memory bus when
disabled. Once the idle period ends, the buffers are enabled,
allowing them to drive signals onto the memory bus. However,
driving the voltage levels of the memory bus lines takes a finite
amount of time. Thus, such systems typically have a time period
between when the buffers are enabled and when the signals on the
memory bus are at valid logic levels. This "buffer enable" delay if
large enough can undesirably increase latency in accessing the
memory in some memory designs.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Non-limiting and non-exhaustive embodiments of the present
invention are described with reference to the following figures,
wherein like reference numerals refer to like parts throughout the
various views unless otherwise specified.
[0007] FIG. 1 is a block diagram illustrating a system with memory
output buffer control, according to one embodiment of the present
invention.
[0008] FIG. 2 is a flow diagram illustrating the operation of the
system depicted in FIG. 1, according to one embodiment of the
present invention.
[0009] FIG. 3 is a block diagram illustrating a portion of the
memory controller depicted in FIG. 1, according to one embodiment
of the present invention.
[0010] FIG. 4 is a flow diagram illustrating the operation of the
memory controller depicted in FIG. 3, according to one embodiment
of the present invention.
[0011] FIG. 5 is a block diagram illustrating a portion of the
memory controller depicted in FIG. 1, according to another
embodiment of the present invention.
[0012] FIG. 6 is a flow diagram illustrating the operation of the
memory controller of FIG. 5, according to one embodiment of the
present invention.
[0013] FIG. 7 is a flow diagram illustrating the operation of the
memory controller of FIG. 5, according to another embodiment of the
present invention.
DETAILED DESCRIPTION
[0014] FIG. 1 illustrates a system 10 having low latency buffer
control, according to one embodiment of the present invention. In
particular, this embodiment of system 10 includes a processor 11, a
memory controller 12 and a memory 13. Memory 13 is a DRAM memory in
the illustrated embodiment, but can be any type of memory used with
a memory bus for which power dissipation is reduced when buffers
driving the memory bus are disabled.
[0015] In addition, this embodiment of memory controller 12
includes a buffer control circuit 14 and a set of N buffers 16.
FIG. 1 shows a buffer 16.sub.1 of the N buffers, with the remaining
buffers being omitted for clarity. Buffer control circuit 14
typically includes circuitry (e.g., combinatorial logic circuits)
to provide enable signals to buffers 16, timed to reduce latency in
memory accesses.
[0016] The elements of this embodiment of system 10 are
interconnected as follows. Memory controller 12 is connected to
memory 13 and processor 11 via system bus 18 and memory bus 17,
respectively. More particularly, buffer 16 of memory controller 12
are connected to memory bus 17. In this embodiment, memory bus 17
has N bus lines, each being resistively terminated to a mid-range
voltage, and system bus 18 has M bus lines.
[0017] In this embodiment of memory controller 12, buffer control
circuit 14 is connected to buffers 16. In particular, buffer
control circuit 14 is connected to the enable input terminals of
buffers 16. Further, in some embodiments, buffer control circuit 14
is connected to detect transactions being communicated on system
bus 18.
[0018] FIG. 2 illustrates the operational flow of system 10 (FIG.
1) in selectively enabling buffers 16 to reduce latency, according
to one embodiment of the present invention. Referring to FIGS. 1
and 2, system 10 operates as follows.
[0019] The system bus is monitored for transactions. In one
embodiment, memory controller 12 monitors system bus 18 for
transactions. More particularly, buffer control circuit 14 of
memory controller 12 monitors system bus 18 to detect transactions.
This operation is represented by blocks 21 and 22.
[0020] If a transaction is detected in block 22, the operational
flow proceeds to a block 24; however, if no transaction is detected
in block 22, the operational flow returns to block 21.
[0021] As shown in block 24, buffers 16 are enabled. In one
embodiment, buffer control circuit 14 provides enable signals to
the N buffers of buffers 16. In this embodiment, buffers 16 are
conventional three-state buffers that present a high impedance to
memory bus 17 when disabled, and either pull up or pull down the
voltages of the bus lines of memory bus 17 when enabled. Thus, in
this embodiment, buffers 16 are enabled before the transaction is
decoded; thereby ensuring the buffers are enabled before they are
needed to drive signals on memory bus 17. In this way, the latency
effects of the aforementioned "buffer enable" delay can be
significantly reduced or even eliminated for memory accesses.
[0022] The detected transaction is then decoded. In one embodiment,
decode circuitry in memory controller 12 decodes the transaction.
One function of the decode circuitry is to determine the "target
agent" of the transaction. For example, for memory transactions,
the targeted agent would be memory 13. Other types of transactions
(e.g., PCI transactions), the targeted agent would be a different
element (e.g., a PCI card). In one embodiment, the "buffer enable"
delay transpires concurrently with the delay of the decode process,
which, as described above, reduces or eliminates the impact of the
"buffer enable" delay on memory access latency. A block 25
represents this operation.
[0023] The decoded transaction is then evaluated to determine
whether the transaction is a memory transaction. In one embodiment,
buffer control circuit 14 determines whether the transaction is a
memory transaction by determining whether the decoded address is
within an address range allocated to memory. A block 26 represents
this operation.
[0024] If the transaction is a memory transaction, memory
controller 12 performs the memory transaction as represented by a
block 27. Buffers 16 are then disabled. In one embodiment, buffer
controller circuit 14 disables the buffers by de-asserting the
aforementioned enable signals. A block 28 represents this
operation.
[0025] However, if in block 26 the transaction is determined to be
a non-memory transaction (e.g., a PCI transaction), the transaction
is handled by the targeted agent as represented by a block 29. For
example, memory controller 12 can ignore the transaction, which
will also be received by the targeted agent, thereby allowing the
target agent to perform the transaction. The operational flow then
returns to block 21, with buffers 16 being disabled.
[0026] FIG. 3 illustrates a portion of memory controller 12 (FIG.
1), according to one embodiment of the present invention. In this
embodiment, memory controller 12 includes a transaction store 31
and a decoder 32. In addition, buffer control circuit 14 (FIG. 1)
includes a logic circuit 33.
[0027] In this embodiment, transaction store 31 stores transactions
received from system bus 18. In one embodiment, transaction store
31 is implemented with a register. Decoder 32 determines, as one of
its functions, the targeted agent of a received transaction. In one
embodiment, decoder 32 is substantially similar to transaction
decoders used in existing memory controllers. In this embodiment,
logic circuit 33 includes standard logic gates to generate the
enable signals provided to buffers 16 with the desired timing.
[0028] Transaction store 31 is connected to receive transactions
from system bus 18. Decoder 32 is connected to the output port of
transaction store 31. In addition to buffers 16, logic circuit 33
is connected to an output port of decoder 32. Further, in this
embodiment, logic circuit 33 is connected to monitor transactions
received by transaction store 31. As previously described, buffers
16 have output leads connected to memory bus 17. The operation of
this embodiment of memory controller 12 in enabling buffers 16 is
described below in conjunction with FIG. 4.
[0029] FIG. 4 illustrates the operational flow of memory controller
12 (FIG. 3) in enabling its memory interface buffers, according to
one embodiment of the present invention. Referring to FIGS. 3 and
4, this embodiment of memory controller 12 operates as follows.
[0030] This embodiment of memory controller 12 operates in general
as described above in conjunction with FIG. 2, with block 24 being
described in more detail. Although previously described, blocks 21,
22 and 24-29 are described again to include the interactions with
the elements of FIG. 3.
[0031] Memory controller 12 performs blocks 21 and 22 to monitor
and detect transactions being sent over the system bus. In this
embodiment, logic circuit 33 of memory controller 12 monitors
system bus 18 to detect transactions.
[0032] If logic circuit 33 does not detect a transaction in block
22, the operational flow returns to block 21. However in this
embodiment, if logic circuit 33 does detect a transaction, logic
circuit 33 asserts enable signals provided to buffers 16. The
asserted enable signals enables the buffers as described above for
block 24. A block 41 represents this operation.
[0033] In addition, the transaction is received by the memory
controller. In this embodiment, transaction store 31 receives and
stores the transaction. A block 42 represents this operation.
Blocks 41 and 42 of this embodiment are operations of block 24
(FIG. 1). Although block 42 is shown in FIG. 4 as being performed
after block 41, in practice block 42 may be performed before or
concurrently with block 41.
[0034] As previously described, because buffers 16 are enabled
before the transaction is decoded; the buffers are enabled before
they are needed to drive signals on memory bus 17. Thus, the
latency effects of the aforementioned "buffer enable" delay can be
significantly reduced or even eliminated for memory accesses.
[0035] Memory controller 12 then performs block 25 to decode the
received transaction. In this embodiment, decoder 32 of memory
controller 12 decodes the transaction, which includes determining
the "target agent" of the transaction.
[0036] Memory controller 12 then performs block 26 to determine
whether the transaction is a memory transaction. In this
embodiment, decoder 32 determines the targeted agent of the
transaction.
[0037] If the transaction is a memory transaction, memory
controller 12 performs block 27. In one embodiment, memory
controller 12 performs the memory transaction using circuitry (not
shown) similar to that in existing memory controllers. Then memory
controller 12 performs block 28 to disable buffers 16. In this
embodiment, logic circuit 33 disables the buffers by de-asserting
the aforementioned enable signals.
[0038] However, if in block 26 the transaction is not a memory
transaction, memory controller 12 performs block 29, allowing the
targeted agent to handle the transaction. In one embodiment, memory
controller 12 simply ignores the non-memory transaction. The
operational flow then proceeds to block 21, with buffers 16
remaining disabled. Although block 28 is shown as being performed
after block 29 under these circumstances, in some embodiments block
28 is performed before or concurrently with block 29.
[0039] FIG. 5 illustrates a portion of memory controller 12 (FIG.
1), according to another embodiment of the present invention. This
embodiment is similar to the embodiment of FIG. 3, except that the
transaction store is implemented as a queue or pipeline and the
buffer control circuit includes a memory transaction detector
connected to monitor transaction via the transaction store instead
of directly. More particularly, in this embodiment, memory
controller 12 includes a transaction queue 31A and decoder 32. In
addition, buffer control circuit 14 (FIG. 1) includes a logic
circuit 33A and a memory transaction detector 51. In one
embodiment, memory transaction detector 51 is implemented as a
decoder configured to decode only the address signals needed
determine whether the transaction is a memory transaction.
[0040] In this embodiment, transaction queue 31A stores multiple
transactions received from system bus 18. In one embodiment,
transaction queue 31A is implemented with a FIFO (first in first
out) buffer. Decoder 32 operates as described above in conjunction
with FIG. 3. Logic circuit 33A is used in generating the enable
signals provided to buffers 16, responsive to the output signal of
memory transaction detector 51.
[0041] Transaction queue 31A is connected to receive transactions
from system bus 18. In addition, transaction queue 31A is connected
to decoder 32 and to memory transaction detector 51. Memory
transaction detector 51 is connected to logic circuit 33A, which in
turn is connected to buffers 16. The operation of this embodiment
of memory controller 12 in enabling buffers 16 is described below
in conjunction with FIG. 6.
[0042] FIG. 6 illustrates the operation of memory controller 12
(FIG. 5) in enabling its memory interface buffers, according to one
embodiment of the present invention. Referring to FIGS. 5 and 6,
this embodiment of memory controller 12 operates as follows.
[0043] Memory controller 12 performs blocks 21 and 22 to monitor
and detect transactions being sent over the system bus. In this
embodiment, transaction queue 31A of memory controller 12 monitors
system bus 18 to detect transactions.
[0044] If transaction queue 31A does not detect a transaction in
block 22, the operational flow returns to block 21. However in this
embodiment, if transaction queue 31A does detect a transaction,
transaction queue 31A receives and stores the transaction.
Transaction queue 31A can store more than one transaction. A block
61 represents this operation.
[0045] Memory controller 12 then performs block 25 to decode a
transaction stored in transaction queue 31A. More particularly,
decoder 32 receives the "oldest" transaction stored in the
transaction queue and decodes it as previously described.
[0046] Memory controller 12 then performs block 26 to determine
whether the transaction is a memory transaction. In this
embodiment, decoder 32 determines the targeted agent of the
transaction. In the transaction is not a memory transaction, memory
controller performs block 29 (as described above) and the
operational flow returns to block 21.
[0047] However, if the transaction is a memory transaction, memory
controller 12 determines whether buffers 16 are enabled. In this
embodiment, logic circuit 33A determines whether these buffers are
enabled. A block 62 represents this operation.
[0048] If the buffers are not enabled, memory controller 12
performs block 41 (described above) to enable the buffers. In this
embodiment, logic circuit 33A asserts the enable signals to enable
buffers 16. In one embodiment, memory controller 12 enables the
buffers as previously described in conjunction with FIG. 4 by
monitoring transaction queue 31A.
[0049] After the buffers are enabled (either after performing block
41 or if the buffers were already enabled as found in block 62),
memory controller 12 then receives the memory transaction from
transaction queue 31A, as represented by a block 63. In this
embodiment, decoder 32 receives the memory transaction from
transaction queue 31A. Then memory controller 12 performs block 27
(as described previously) to execute the memory transaction.
[0050] Memory controller 12 then checks the contents of transaction
queue 31A and determines whether it contains any unexecuted memory
transactions. In this embodiment, memory transaction detector 51
checks each transaction stored in transaction queue 31A to
determine whether the transaction is a memory transaction. In one
embodiment, memory transaction detector 51 provides a signal to
logic circuit 33A that indicates whether transaction queue 31A
contains a memory transaction. Blocks 64 and 65 represent these
operations. In some embodiments, memory transaction detector 51 can
be configured to check a subset of the transactions stored in
transaction queue 31A rather than all of the transactions. For
example, only the next transaction (or some small number of
transactions) to be performed is checked in one embodiment. This
embodiment may be advantageous for relatively large transaction
queues by allowing the buffers to be disabled if the next few
transactions in the queue are non-memory transactions.
[0051] If transaction queue 31A does not contain a memory
transaction, memory controller 12 performs block 28 to disable
buffers 16. In this embodiment, logic circuit 33A receives the
output signal from memory transaction detector 51 and if the signal
indicates that there are no pending memory transaction, logic
circuit 33A de-asserts the enable signals.
[0052] However, if transaction queue 31A does contain a memory
transaction, the operational flow returns to block 63 to receive
the next transaction (which need not be a memory transaction) from
transaction queue 31A, leaving buffers 16 enabled.
[0053] FIG. 7 illustrates the operation of memory controller 12
(FIG. 5), according to another embodiment of the present invention.
Referring to FIGS. 5 and 7, memory controller 12 operates as
follows to enable buffers 16.
[0054] The transactions received and stored by memory controller 12
are monitored for memory transactions. In one embodiment, memory
transaction detector 51 monitors the contents of transaction queue
31A for transactions. A block 71 represents this operation.
[0055] The stored transactions are then checked to determine
whether any are memory transactions. In one embodiment, memory
transaction detector 51 decodes a stored transaction to determine
whether it is a memory transaction. For example, memory transaction
detector 51 may be configured to determine whether the transaction
to be outputted by transaction queue 31A during the next cycle is a
memory transaction. A block 72 represents this operation.
[0056] If the transaction checked in block 72 is not a memory
transaction, the operational flow returns to block 71. However, if
the transaction is a memory transaction, block 41 is performed as
described above to enable the buffers. In this embodiment, memory
transaction detector 51 provides a signal to logic circuit 33A to
assert the enable signals provided to buffers 16.
[0057] Memory controller 12 then performs block 25 to decode a
transaction stored in transaction queue 31A. More particularly,
decoder 32 receives the "oldest" transaction stored in the
transaction queue and decodes it as previously described.
[0058] Memory controller 12 then performs block 26 to determine
whether this transaction is a memory transaction. In this
embodiment, decoder 32 determines this targeted agent of the
transaction to determine whether the transaction is a memory
transaction.
[0059] If this transaction is a memory transaction, memory
controller 12 performs block 27 as previously described to execute
the memory transaction and then block 28 to disable buffers 16. In
this embodiment, logic circuit 33A de-asserts the enable signals to
disable buffers 16. However, if the transaction is not a memory
transaction, memory controller 12 performs block 29 as previously
described, allowing the targeted agent to perform the
transaction.
[0060] Reference throughout this specification to "one embodiment"
or "an embodiment" means that a particular feature, structure, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the present invention. Thus,
the appearances of the phrases "in one embodiment" or "in an
embodiment" in various places throughout this specification are not
necessarily all referring to the same embodiment. Furthermore, the
particular features, structures, or characteristics may be combined
in any suitable manner in one or more embodiments.
[0061] In addition, embodiments of the present description may be
implemented not only within a semiconductor chip but also within
machine-readable media. For example, the designs described above
may be stored upon and/or embedded within machine readable media
associated with a design tool used for designing semiconductor
devices. Examples include a netlist formatted in the VHSIC Hardware
Description Language (VHDL) language, Verilog language or SPICE
language. Some netlist examples include: a behavioral level
netlist, a register transfer level (RTL) netlist, a gate level
netlist and a transistor level netlist. Machine-readable media also
include media having layout information such as a GDS-II file.
Furthermore, netlist files or other machine-readable media for
semiconductor chip design may be used in a simulation environment
to perform the methods of the teachings described above.
[0062] Thus, embodiments of this invention may be used as or to
support a software program executed upon some form of processing
core (such as the CPU of a computer) or otherwise implemented or
realized upon or within a machine-readable medium. A
machine-readable medium includes any mechanism for storing or
transmitting information in a form readable by a machine (e.g., a
computer). For example, a machine-readable medium can include such
as a read only memory (ROM); a random access memory (RAM); a
magnetic disk storage media; an optical storage media; and a flash
memory device, etc. In addition, a machine-readable medium can
include propagated signals such as electrical, optical, acoustical
or other form of propagated signals (e.g., carrier waves, infrared
signals, digital signals, etc.).
[0063] Although the present invention has been described in
connection with a preferred form of practicing it and modifications
thereto, those of ordinary skill in the art will understand that
many other modifications can be made to the invention within the
scope of the claims that follow. Accordingly, it is not intended
that the scope of the invention in any way be limited by the above
description, but instead be determined entirely by reference to the
claims that follow.
* * * * *