U.S. patent application number 11/003177 was filed with the patent office on 2005-04-21 for ball grid array resistor network.
Invention is credited to Ernsberger, Craig, Langhorn, Jason B., Tu, Yinggang.
Application Number | 20050085013 11/003177 |
Document ID | / |
Family ID | 32467911 |
Filed Date | 2005-04-21 |
United States Patent
Application |
20050085013 |
Kind Code |
A1 |
Ernsberger, Craig ; et
al. |
April 21, 2005 |
Ball grid array resistor network
Abstract
A ball grid array resistor network has a planar substrate formed
of an organic material. The substrate preferably is a printed
circuit board. The substrate has a top and bottom surface. A ball
pad is located on the bottom surface. A low temperature resistor is
located on the bottom surface and is connected to the ball pad. A
solder mask is located over the first surface except for the ball
pads. A conductive ball is attached to the ball pad. A reflowed
solder paste connects the conductive ball to the ball pad. Several
embodiments of the invention are shown.
Inventors: |
Ernsberger, Craig; (Granger,
IN) ; Langhorn, Jason B.; (South Bend, IN) ;
Tu, Yinggang; (Elkhart, IN) |
Correspondence
Address: |
CTS CORPORATION
905 W. BLVD. N
ELKHART
IN
46514
US
|
Family ID: |
32467911 |
Appl. No.: |
11/003177 |
Filed: |
December 3, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11003177 |
Dec 3, 2004 |
|
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10309704 |
Dec 4, 2002 |
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Current U.S.
Class: |
438/108 |
Current CPC
Class: |
H05K 3/184 20130101;
H05K 3/28 20130101; H05K 3/3436 20130101; H05K 2201/0355 20130101;
H01C 1/028 20130101; H05K 2203/1453 20130101; H05K 2203/0361
20130101; H01C 17/06 20130101; H05K 1/167 20130101; H05K 2203/041
20130101 |
Class at
Publication: |
438/108 |
International
Class: |
H01L 021/44 |
Claims
We claim:
1. A method of making a resistor network comprising the steps of:
a) providing a conductive layer and a resistive layer laminated to
a first surface of an organic substrate, the resistive layer
located between the organic substrate and the conductive layer; b)
forming at least one ball pad from the conductive layer; c) forming
at least one resistor from the resistive layer; d) coating the
first surface with a solder mask except for the pad; e) screening
solder paste onto the pad; f) placing a solder sphere onto the pad;
and g) reflowing the solder paste such that the solder sphere is
joined to the pad.
2. The method of claim 1, wherein forming the ball pad and resistor
further comprises: a) depositing a first layer of photoresist over
the conductive layer; b) exposing the ball pads and resistors onto
the first layer of photoresist; c) developing the photoresist to
form a first pattern; d) etching the conductive and resistive
layers; e) striping the photoresist; f) depositing a second layer
of photoresist over the conductive layer and the substrate; g)
exposing the resistor onto the second layer of photoresist; h)
developing the second layer of photoresist to form a second
pattern; i) etching the conductive layer; and j) removing the
photoresist.
3. The method of claim 1, wherein the resistor is cut with a laser
to adjust the resistance of the resistor.
4. A method of making a resistor network comprising the steps of:
a) providing a conductive layer mounted to a first surface of an
organic substrate; b) etching a first and second ball pad from the
conductive layer; c) electroplating at least one resistor between
the ball pads; d) laser trimming the resistor to a pre-determined
resistance value; e) coating the first surface with a solder mask
except for the pads; f) screening solder paste onto the pads; g)
placing a solder sphere onto the pads; and h) reflowing the solder
paste such that the solder sphere is attached to the pad.
5. The method of claim 4, wherein forming the ball pads and
resistor further comprises: a) depositing a first layer of
photoresist over the conductive layer; b) exposing a first pattern
of ball pads onto the first layer of photoresist; c) developing the
photoresist to form the first pattern; d) etching the conductive
layer; e) removing the photoresist; f) depositing a second layer of
photoresist over the conductive layer and the substrate; g)
exposing a second pattern onto the second layer of photoresist; h)
developing the second layer of photoresist; i) plating the
resistor; and j) removing the second layer of photoresist.
6. A method of making a resistor network comprising the steps of:
a) providing a conductive layer; b) screen printing a plurality of
resistors on the conductive layer; c) firing the conductive layer
and resistors in an oven; d) depositing a laser reflective layer
over the conductive layer and resistors; e) laminating the
conductive layer and resistors to a substrate; f) etching a first
and second ball pad from the conductive layer; g) coating the first
surface with a solder mask except for the ball pads; h) screening
solder paste onto the pads; i) placing a solder sphere onto the
pads; and j) reflowing the solder paste such that the solder sphere
is attached to the pad.
7. The method of claim 6, wherein an adhesive layer is used to
laminate the conductive layer and the resistors to the
substrate.
8. The method of claim 6, wherein the resistors are cut with a
laser to adjust the resistance of the resistor.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention pertains generally to resistor networks for
terminating transmission lines and electronic devices and more
specifically to a resistor network that is formed on an organic
substrate.
[0003] 2. Description of the Related Art
[0004] Transmission lines are used in a diverse array of electronic
equipment to accommodate transmission of electrical or electronic
signals. These signals may have a diverse set of characteristics,
which might, for example, include direct or alternating currents,
analog or digitally encoded content, and modulation of any of a
diverse variety of types. Regardless of the characteristics of the
signal, an ideal transmission line will conduct the signal from
source to destination without altering or distorting the signal.
Distance is inconsequential to this ideal transmission line, other
than delays which might be characteristic of the transmission
medium and the distance to be traversed.
[0005] At low frequencies and with direct current transmissions,
many transmission lines perform as though they are nearly ideal,
even over very great distances. Unfortunately, as the frequency of
the signal increases, or as the frequency of component signals that
act as a composite increases, the characteristics of most common
transmission lines decay and signal transmission progressively
worsens. This is particularly true when signals reach the radio
frequency range or when transmission lines become longer. One
common phenomenon associated with high frequency, long distance
transmission lines is a loss of the signal's high frequency
components and the introduction of extraneously induced interfering
high frequency signals. Another common phenomenon is echo or line
resonance, where a signal may be reflected from one end of the
transmission line back to the other. In the case of a digital
pulse, the effect will lead to corrupted data, since additional
pulses may be received that were not part of the original
transmission, and reflected pulses may cancel subsequent
pulses.
[0006] To prevent echo within a transmission line, it is possible
to terminate the line with a device which is referred to in the art
as an energy dissipating termination. The termination must have an
impedance which is designed to match the characteristic impedance
of the transmission line as closely as possible over as many
frequencies of interest as possible. Transmission lines generally
have an impedance which is based upon the inductance of the
conductor wire, capacitance with other signal lines and ground
planes or grounding shields, and resistance intrinsic in the wire.
With an appropriate transmission line, the sum of the individual
impedance components is constant and described as the
"characteristic impedance." To match the transmission line
characteristic impedance over a wide frequency range, a termination
must also address each of the individual impedance components. The
effect of inductance is to increase impedance with increasing
frequency, while capacitance decreases impedance with increasing
frequency. Intrinsic resistance is independent of frequency.
[0007] In the particular field of data processing, transmission
lines typically take the form of busses, which are large numbers of
parallel transmission lines along which data may be transmitted.
For example, an eight bit data bus will contain at least eight
signal transmission lines that interconnect various components
within the data processing unit. The data bus is actually a
transmission line having to accommodate, with today's processor
speeds, frequencies which are in the upper radio frequency band
approaching microwave frequencies. These high frequency busses are,
in particular, very susceptible to inappropriate termination and
transmission line echo.
[0008] Terminations used for these more specific applications such
as the data processor bus serve several purposes. A first purpose
is to reduce echoes on the bus by resistively dissipating any
signals transmitted along the bus. This first purpose is found in
essentially all termination applications. A second purpose, more
specific to data busses or other similar electronic circuitry, is
to function as what is referred to in the art as a "pull-up" or
"pull-down" resistor. The termination resistor will frequently be
connected directly to either a positive power supply line or
positive power supply plane, in which case the termination resistor
is a "pull-up" resistor, or the resistor may be connected to either
a negative or ground line or plane, in which case the resistor is
referred to as a "pull-down" resistor. When no signal is present on
the line, the voltage on the transmission line will be determined
by the connection of the termination resistor to either a power
supply line or a ground or common line. Circuit designers can then
work from this predetermined bus voltage to design faster, more
power-efficient components and circuits.
[0009] The prior art has attempted to address signal line
termination in a number of ways which were suitable at lower
operating speeds and frequencies, but which have not proven fully
desirable as frequencies and components thereof increase.
[0010] One of several processes may be used to fabricate resistors.
One such process is referred to as thin film, which might include
vapor deposition techniques, sputtering, semiconductor wafer type
processing, and other similar techniques. An example of a thin film
component is found in U.S. Pat. No. 5,216,404 to Nagai et al.
[0011] Another process is to use thick film components, herein
considered to be components that are formed from a layer of
semi-conductive metal oxide, cermet or a dielectric material
deposited upon a non-conductive substrate, are most commonly formed
from screen printing techniques. For the purposes of this
application, thick films are defined as films formed when specially
formulated pastes or inks are applied and fired or sintered onto a
substrate at a high temperature of around 900 degrees Centigrade in
a definite pattern and sequence to produce a set of individual
components, such as resistors and capacitors, or a complete
functional circuit. The substrates can be either pre-fired or can
be in a green un-fired state. The pastes are usually applied using
a screen printing method and may typically have a thickness of from
0.2 to 1 mil or more, and are well known in the industry. Cermet
materials are materials comprising ceramic or glass in combination
with metal compositions, where the first three letters: CER &
MET make the word CERMET.
[0012] TCR stands for Temperature Coefficient of Resistance, which
is a measure of the amount of change in resistance over some
temperature range. Sheet resistance for the purposes of this
disclosure is measured in the units of ohms per square. This will
be considered herein to be the resistance of a film of equal length
and width.
[0013] Low TCR thick film resistors may be readily manufactured
that are both durable and have excellent TCR. These resistors may
have sheet resistances that vary from fractions of an Ohm to
millions of Ohms per square with a TCR less than.+-.100
ppm/.quadrature.C. Inductance increases with length. Therefore, to
minimize inductance in the termination, signal lines should be kept
as short as possible. Furthermore, shorter line lengths decrease
the undesirable cross-talk described hereinabove. Stray capacitance
should be minimized, since this stray capacitance is frequently
variable with temperature due to temperature related variations in
ordinary dielectrics.
[0014] In the prior art, transmission line terminations were
initially constructed using large Cermet resistors which were
formed by thick film techniques upon alumina (aluminum oxide)
substrates. These components were then mounted into a circuit board
in a Single-In-line Package (SIP) format. Later, Ball Grid Array
(BGA) packages were developed for integrated circuit packages. In
this package, the connection between a printed circuit board and
the BGA component is achieved through the use of a number of solder
balls. These balls are not limited to placement around the
periphery of the device, as was the case in the chip resistors of
the prior art, but instead the BGA has terminations distributed in
the array across the entire package resulting in a higher packaging
density. Examples of BGA type terminations are found in U.S. Pat.
Nos. 4,332,341 to Minetti; 4,945,399 to Brown et al; 5,539,186 to
Abrami et al; 5,557,502 to Banerjee et al; 5,661,450 to Davidson;
6,097,277 to Ginn; 6,326,677 to Bloom; 6,005,777 to Bloom;
5,977,863 to Bloom; 6,246,312 to Poole and 6,194,979 to Bloom. Each
of these patents illustrate various types of BGA components and
packages, the contents and teachings which are incorporated herein
by reference. These prior art BGA devices have a high cost of
production due to the fact that they are manufactured either one at
a time or in small arrays and many manufacturing steps are
required.
[0015] While the prior art has provided devices suitable as
resistor networks, there is a current unmet need for a lower cost
resistor network with low inductance that can be fabricated using
an efficient manufacturing process.
SUMMARY OF THE INVENTION
[0016] It is a feature of the invention to provide a high density
resistor network utilizing the benefits of printed circuit board
technology and a solder bump or sphere connection.
[0017] It is a feature of the invention to provide a resistor
network that minimizes connection inductance from the network to a
circuit board by keeping connection wiring as short as
possible.
[0018] It is a feature of the invention to provide an economical
solution to transmission line termination at high frequencies.
[0019] It is a feature of the invention to provide a resistor
network that includes a planar substrate formed of an organic
material having a first and second surface. A resistor is located
on the first surface. A ball pad is located on the first surface.
The ball pad is connected to the resistor. An organic solder mask
is located over the first surface. The solder mask has apertures
located over the ball pads. A conductive ball is attached to the
ball pad. A reflowed solder paste attaches the conductive ball to
the ball pad. The reflowed solder paste connects the conductive
ball to the ball pad.
[0020] It is a feature of the invention to provide a resistor
network that includes a planar substrate formed of an organic
material having a first and second surface. A resistor is located
on the first surface. A ball pad is located on the first surface.
The ball pad is connected to the resistor. An organic solder mask
is located over the first surface except for the ball pads. A
conductive bump is formed on the ball pads by a reflowed solder
paste.
[0021] It is a feature of the invention to provide a resistor
network that includes an metal substrate having an insulative layer
thereon. The insulative layer having a first surface. A resistor is
located on the first surface. A ball pad is located on the first
surface. The ball pad is connected to the resistor. An organic
solder mask is located over the first surface except for the ball
pads. A conductive bump is formed on the ball pads by a reflowed
solder paste.
[0022] It is a feature of the invention to provide a method of
making a resistor network. The method includes providing a
conductive layer and a resistive layer laminated to a first surface
of an organic substrate. The resistive layer is located between the
organic substrate and the conductive layer. A ball pad is formed
from the conductive layer. A resistor is formed from the resistive
layer. The first surface is coated with a solder mask except for
the pad. A solder paste is screened onto the pad. A solder sphere
is placed onto the pad. The solder paste is reflowed such that the
solder sphere is joined to the pad.
[0023] It is a feature of the invention to provide a method of
making a resistor network. The method includes providing a
conductive layer laminated to a first surface of an organic
substrate. A ball pad is formed from the conductive layer. A
resistor is plated onto the ball pad and the substrate. The first
surface is coated with a solder mask except for the pad. A solder
paste is screened onto the pad. A solder sphere is placed onto the
pad. The solder paste is reflowed such that the solder sphere is
joined to the pad.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1 is a cross-sectional view of a ball grid array
resistor network according to the present invention along section
line A-A of FIG. 2.
[0025] FIG. 2 is a perspective view of the ball grid array resistor
network of FIG. 1.
[0026] FIG. 3 is a flow chart of the manufacturing steps using an
etched resistor for producing the ball grid array resistor network
of FIG. 1.
[0027] FIG. 4 is a cross-sectional view of an alternative
embodiment of a ball grid array resistor network.
[0028] FIG. 5 is a cross-sectional view of an another embodiment of
a ball grid array resistor network.
[0029] FIG. 6 is a flow chart of the manufacturing steps using a
plated resistor for producing the ball grid array resistor network
of FIG. 5.
[0030] FIG. 7 is a cross-sectional view of an another embodiment of
a ball grid array resistor network.
[0031] FIG. 8 is a flow chart of the manufacturing steps using a
laminated thick film resistor for producing the ball grid array
resistor network of FIG. 7.
[0032] FIG. 9 is a bottom view of a ball grid array resistor
network used for a computer circuit simulation.
[0033] FIG. 10 is a Smith chart plot of S11 for the resistor
network of FIG. 9 without metal layer 102.
[0034] FIG. 11 is a Smith chart plot of S11 for the resistor
network of FIG. 9 with metal layer 102.
[0035] It is noted that the drawings are not to scale.
[0036] Like components have been numbered as similarly as possible
between drawings to simplify reference purposes.
DETAILED DESCRIPTION
Preferred Embodiment
[0037] Referring to FIGS. 1 and 2, a Ball Grid Array Resistor
Network (BGA) 20 is shown. Network 20 has a planar substrate or
printed wiring board 21 formed from an organic polymer material.
Substrate 21 has a top surface 23 and a bottom surface 24.
Substrate 21 can be formed from various organic materials such as
FR4, Polyimide and other insulative dielectrics.
[0038] Printed wiring board 21 includes a non-conductive substrate
and copper traces. The non-conductive substrate is preferably a
composite material, for example, epoxy-glass, phenolic-paper, or
polyester-glass; and typical composites used in circuit board
manufacturing include polyimides for flexible circuitry or
high-temperature applications; paper/phenolic which can be readily
punched: National Electrical Manufacturers Association (NEMA) grade
FR-2; paper/epoxy which has better mechanical properties than the
paper/phenolic: NEMA grade FR-3; glass/epoxy and woven glass fabric
which have good mechanical properties: NEMA grade FR-4, FR-5; and
random glass/polyester which is suitable for some applications:
NEMA grade FR-6. NEMA FR-4 material is preferred.
[0039] The glass/epoxy layers are bonded together using adhesive
layers, which are conventionally called "prepreg" because they are
partially cured before lamination. For a discussion of wiring board
fabrication methods, including lamination techniques, see, Shaw,
Sam R. and Alonzo S. Martinez Jr. "Rigid And Flexible Printed
Wiring Boards And Microvia Technology" in Harper, Charles A., Ed.
Electronic Packaging And Interconnection Handbook, 3rd Ed., Chapter
11, McGraw-Hill, New York, N.Y. (2000), the relevant portions of
which are herein incorporated by reference.
[0040] Substrate 21 typically would have dimensions of 0.16 inches
by 0.6 inches. A low temperature resistor 26 is attached to
substrate 21. Resistor 26 has ends 26A and 26B. Copper ball pads 28
are located over resistor ends 26A and 26B. Resistor 26 is
electrically connected to ball pads 28. Resistor 26 can be formed
from several different materials using different process. For
example, resistor 26 can be a vacuum deposited thin film of nickel
chromium or nickel chromium aluminum silicide. Resistor 26 can also
be made of doped platinum that is formed by chemical vapor
deposition. The thin film would have a typical thickness of 100 to
1000 angstroms. Resistors 26 would have a typical sheet resistance
of 50 to 5000 ohms per square. The term low temperature resistor
refers to the fact that the resistor is not processed at high
temperature of 900 Celsius as is required of thick film cermet
resistors. This allows the use of an organic substrate such as a
printed circuit board. The resistor 26 can be laser trimmed in
order to improve the accuracy of their resistance value. The
dimensions of resistor 26 are on the order of 16 mils by 9 mils.
Ball pads 28 can be formed from a conductor layer such as a 1/2
ounce copper foil and have a typical thickness of 0.015 mm. It is
noted that the resistor layer 26 extends under ball pads 28. If
desired, circuit lines (not shown) can be made from the conductor
layer. The conductor lines would be connected between the ball pads
and the resistor. A solder mask layer 32 is located over all of
surface 24 except for ball pads 28. This leaves an aperture in the
solder mask surrounding each ball pad. Solder mask layer 32 is
screened or sprayed and photodefined on surface 24 and then cured.
Solder mask layer 32 prevents shorting during soldering and
protects resistor 26. The processing steps for making ball grid
array resistor network 20 are detailed below.
[0041] Conductive bumps, spheres or balls 34 are attached to ball
pads 28. Conductive spheres 34 are preferably made from a high
melting point solder having a composition of 10% tin and 90% lead.
Conductive bumps 34 can also be a solder paste that is reflowed
into a hump or bump shape. The composition of the conductive
spheres 34 can range from 80 to 95 percent lead and 5 to 20 percent
tin. The conductive spheres 34 are preferably held to ball pads 28
by a low temperature reflowed solder paste 36. The reflowed solder
paste has a composition between 30 to 40 percent lead and 60 to 70
percent tin with a preferred composition of 63% tin and 37%
lead.
[0042] By using a preformed conductor such as the conductive
spheres illustrated, it is possible to achieve consistent
dimensional control over the components, where a reflowed extension
could be more difficult to control during manufacture. So while
preforms are preferred, other cost effective methods of forming
electrical attachment points to the terminators and networks of the
present invention are contemplated and included herein, to the
extent such terminations are known or would be obvious to those
skilled in the art.
[0043] These conductive balls serve to electrically connect the
ball pads to a mother board or other printed circuit or carrier
substrate. These solder balls may be manufactured to be quite
small, substantially only limited by the smallest sizes that may be
produced. These balls may, in fact, be measured in thousandths or
hundredths of an inch in diameter. Since all of surface 24 is
covered by the ball grid array, there is no wasted surface
real-estate on the carrier circuit board, such as a mother board,
to which this component is attached. In addition, the signals that
the ball pads interact with must only pass along a short lead
length reducing inductance and cross-talk noise.
[0044] Referring to FIG. 3, a flow chart of the manufacturing steps
used for producing ball grid array resistor network 20 is shown. At
step 48, an organic substrate is laminated to a conductive layer
such as a copper layer or foil that has a thin film resistive layer
coated on one side. The resistive layer can be a vacuum deposited
thin film of nickel chromium or nickel chromium aluminum silicide.
The resistive layer can also be a doped platinum formed by chemical
vapor deposition. The copper foil with resistive layer is attached
to the substrate using conventional printed circuit board
fabrication techniques. Nickel chromium and nickel chromium
aluminum silicide thin film coated copper resistive foils are
commercially available from Gould Electronics Corporation,
Eastlake, Ohio. Doped platinum coated copper foil is commercially
available from Shipley Corporation, Marlboro, Mass. The substrate
or board used during fabrication has typical overall dimensions of
12 inches by 18 inches or larger. At step 50 a photoresist is
applied over the copper layer. The photoresist can be coated or
sprayed or can be laminated with a dry film resist. At step 52, the
ball pads are exposed in the photoresist. This is done by shining a
UV light through a mask that has the desired pattern. At step 54,
the photoresist is developed. The ball pads are defined by etching
at step 56. The etching process here will be illustrated using a
nickel chromium resistor material. Different etch chemicals and
processes can be used for different types of resistive films.
Substrate 21 is placed into a solution of cupric chloride that
removes the exposed copper and resistor layers. Next, at step 58
the photoresist is removed using a photoresist stripper.
Photoresist is re-applied to the substrate at step 60, exposed at
step 62 to define low temperature resistors 26 and developed at
step 64. At step 66, the copper is selectively etched using an
ammoniacal etching solution to define the resistors. The
photoresist is then stripped off at step 68. The resistor may be
laser trimmed to value. Surface 24 is coated with a solder mask at
step 70. The solder mask covers all of surface 24 except for the
ball pad areas 28. The solder mask protects the resistors and
prevents shorts during soldering. The solder mask is preferably
P6280C polymer overcoat that is commercially available from Ferro
Corporation of Montgomeryville, Pa. The solder mask is screen
printed onto surface 24 and then cured at 150 degrees centigrade
for 30 minutes.
[0045] The substrates are then loaded onto a stainless steel Auer
boat for transport through the ball attach machine. The loaded Auer
boats are cycled from the input buffer to the elevator. The parts
are then captured and lifted to present them to the bottom side of
the solder screening station. At step 72, a low melting point
solder paste is screened onto ball pads 28. The solder paste has a
composition between 30 to 40 percent lead and 60 to 70 percent tin
with a preferred composition of 63% tin and 37% lead which melts at
167 degrees centigrade.
[0046] Next, at step 74, spheres or balls 34 are placed onto ball
pads 28. Conductive spheres 34 are preferably made from a high
melting point solder having a composition of 10% tin and 90% lead.
The balls are placed using a ball placer, which incorporates a
precision machined ball mask to locate and hold the solder balls
while this assembly is inverted over the substrates with the solder
paste. Once the ball mask is in position the solder balls are
released into the solder paste. The ball attach machine then uses a
vision system to inspect the pre-reflow condition of the solder
balls before the Auer boat with the assembled units is allowed to
proceed through the solder reflow and wash portions of the ball
attach cell.
[0047] At step 76, substrate 21 is placed into an oven where the
solder paste 36 is reflowed which attaches solder ball 34 to ball
pad 28. Substrate 21 is cleaned and singulated or cut into
individual pieces at step 78. A diamond saw, laser or water jet can
be used to cut the individual BGA networks. The individual parts
are electrically tested at step 80.
[0048] Alternatively, placing the solder spheres can be omitted and
the solder paste reflowed into a conductive bump or hump shape.
[0049] BGA network 20 has many advantages. Network 20 provides a
resistor that can be used to terminate transmission lines and other
electronic devices that require a matched termination that
minimizes reflections and has low inductance. Since, BGA resistor
network 20 is fabricated in a large panel of 12.times.18 inches or
larger and then cutup into individual networks 20, the process is
very cost efficient. Large numbers of networks and resistors can be
fabricated. Each 18.times.20 printed circuit board panel can
contain over 37,000 resistors and 1300 networks. Since, network 20
can be fabricated in a large panel format, the individual cost of
each BGA resistor network 20 can be kept low. Another advantage of
BGA resistor network 20 is that since substrate 21 is formed from
the same material (FR4) as the printed circuit board that it is
mounted to, stress to the solder joints from thermal mis-match is
eliminated. Both the underlying printed circuit board and substrate
21 will expand and contract at the same rate during temperature
changes in the surrounding environment. Since, the expansion rates
are matched, the ball pads and solder balls can have smaller
dimensions without causing excessive stress in the reflowed solder
paste during thermal excursions.
1.sup.st Alternative Embodiment
[0050] Referring to FIG. 4, another embodiment of a Ball Grid Array
Resistor Network 100 is shown. Network 100 is similar to network 20
except that a heat dissipating metal layer 102 has been attached to
surface 23. Layer 102 has an outer surface 108. Metal layer 102 can
be copper or aluminum or any other heat dissipating metal of
varying thickness. Metal layer 102 can be another layer of copper
foil. If desired more than one layer of heat dissipating metal can
be used to form a multi-layered structure. Substrate 21 can be FR4
or Polyimide or another polymeric laminate. For improved thermal
performance, substrate 21 can be formed from a thermally conductive
material such as Thermal Clad LT or HT dielectric which is
commercially available from Bergquist Corporation of Chahassen,
Minn. These thermally conductive materials are formed from metal
oxide filled epoxies. The thermally conductive material conducts
heat generated by resistor 26 through substrate 21 to be dissipated
by metal layer 102. The thermally conductive material has a thermal
conductivity of 2.2 W/m degree K (watts per meter degree Kelvin).
The thermal impedance of this dielectric is 0.45 degrees C/watt at
3 mils thickness. Bergquist Corporation also has CML material that
has a thermal conductivity of 1.1 W/m*K and a thermal impedance of
1.1 C/W at 6 mils thickness. As a comparison, the thermal
conductivity of conventional FR4 material is {fraction (1/10)} that
of the Bergquist HT material.
[0051] The manufacturing processing of network 100 is similar to
that of network 20 except that a photoresist would be applied over
surface 108 in order to prevent the chemicals used during etching
from removing or degrading layer 102.
2.sup.nd Alternative Embodiment
[0052] Referring to FIG. 5, another embodiment of a Ball Grid Array
Resistor Network 200 is shown. Network 200 is similar to network 20
except that resistor 26 has been replaced by a low temperature
additive plated resistor 202. Resistor 202 has ends 202A and 202B
that overlap ball pads 28. Resistors 202 have a sheet resistivity
of 25 to 250 ohms per square. The middle portion of resistor 202 is
attached to substrate 21. Resistor 202 can be additively plated
using plating baths commercially available from Macdermid
Corporation of Waterbury, Conn. Details of the design and
manufacture of such resistors 202 are shown in U.S. Pat. No.
6,281,090. The contents of which are herein incorporated by
reference. Resistor 202 can be formed from an electrolessly
deposited nickel phosphorous material. Resistor 202 would have
typical dimensions of 16 mils by 9 mils. The plated resistor 202
has a thickness of 50-1000 angstroms. If desired, the metal layer
202 of FIG. 2 may be attached to surface 23 of network 200 in order
to improve thermal performance.
[0053] Referring to FIG. 6, a flow chart of the manufacturing steps
used for producing ball grid array resistor network 200 are shown.
At step 210, a photoresist is applied over a conventional FR4
copper foil/fiberglass printed circuit board. The photoresist can
be sprayed or can be a dry film resist. The substrate or board has
typical dimensions of 12 inches by 18 inches. At step 212, resistor
areas and ball pads are exposed in the photoresist. This is done by
shining a UV light through a mask that has the desired pattern. At
step 214, the photoresist is developed. The ball pads are etched at
step 216. Substrate 21 is placed into a solution of cupric chloride
that removes the exposed copper areas. Next, at step 218 the
photoresist is removed using a photoresist stripper. At step 220,
the substrate 21 surface is activated for plating by dipping the
board into an activation bath such as palladium chloride.
Photoresist is re-applied to the substrate at step 222 and exposed
at step 224 to define areas for resistors 202. At step 226, the
photoresist is developed. The resistors are plated at step 228
using an electroless nickel phosphorous bath. Such baths are
commercially available from Macdermid Corporation of Waterbury,
Conn. Details of the design and manufacture of such resistors are
shown in U.S. Pat. No. 6,281,090. The contents of which are herein
incorporated by reference in entirety. The plated resistor 202 has
a typical thickness of 50 to 1000 angstroms. The photoresist is
then stripped off at step 230. The resistor is laser trimmed to
value at step 232. Surface 24 is also coated with a solder mask at
step 232. The solder mask covers all of surface 24 except for the
ball pad areas 28. The solder mask protects the resistors and
prevents shorts during soldering. At step 234, a low melting point
solder paste is screened onto ball pads 28. The solder paste has a
composition between 30 to 40 percent lead and 60 to 70 percent tin
with a preferred composition of 63% tin and 37% lead which melts at
167 degrees centigrade. Next, at step 236, conductive bumps,
spheres or balls 34 are placed onto ball pads 28. Conductive
spheres 34 are preferably made from a high melting point solder
having a composition of 10% tin and 90% lead. Alternatively,
placing the solder spheres can be omitted and the solder paste
reflowed into a conductive bump or hump shape. At step 238,
substrate 21 is placed into an oven where the solder paste 36 is
reflowed which attaches solder ball 34 to ball pad 28. Substrate 21
is cleaned and singulated or cut into individual pieces at step
240. The individual parts are tested at step 242.
[0054] BGA network 200 has the same advantages as network 20.
3.sup.rd Alternative Embodiment
[0055] Referring to FIG. 7, another embodiment of a Ball Grid Array
Resistor Network 400 is shown. Network 400 has a planar substrate
21 formed from an organic material. Substrate 21 has a top surface
23 and a bottom surface 24. Substrate 21 can be formed from various
organic materials such as FR4, Polyimide and other insulative
dielectrics. An adhesive layer 402 is attached to substrate 21.
[0056] A resistor 26 has ends 26A and 26B. Copper ball pads 28 are
located over resistor ends 26A and 26B. Resistor 26 is electrically
connected to ball pads 28. Resistor 26 is formed by screen printing
a resistive paste onto a copper foil, then firing in an oven. This
resistor paste has a resistivity of 10 to 100,000 ohms per square.
The resistors would have typical dimensions of 15 mils by 15 mils
by 2 to 20 microns thick. The copper foil can be 1/2 to 10 ounce
copper foil. The copper foil is later etched to form copper pads
28. The resistor 26 can be laser trimmed in order to improve the
accuracy of their resistance value. A laser reflective layer 404 is
placed over the resistor 26. Reflective layer 404 can be a silver
filled epoxy resin. The purpose of reflective layer 404 is to
prevent the laser used during laser trimming from burning the
substrate 21. The laser reflective layer 404 is attached to the
adhesive 402. A solder mask layer 32 is located over all of surface
24 except for ball pads 28. Solder mask layer 32 is screened or
sprayed on surface 24 and then cured. Solder mask layer 32 prevents
shorting during soldering and protects resistor 26.
[0057] Conductive bumps, spheres or balls 34 are attached to ball
pads 28. Conductive spheres 34 are preferably made from a high
melting point solder having a composition of 10% tin and 90% lead.
Conductive bumps 34 can also be a solder paste that is reflowed
into a hump or bump shape. The composition of the conductive
spheres 34 can range from 80 to 95 percent lead and 5 to 20 percent
tin. The conductive spheres 34 are preferably held to ball pads 28
by a low temperature reflowed solder paste 36. The reflowed solder
paste has a composition between 30 to 40 percent lead and 60 to 70
percent tin with a preferred composition of 63% tin and 37% lead.
If desired, the metal layer 202 of FIG. 2 may be attached to
surface 23 of network 400 in order to improve thermal
performance.
[0058] Referring to FIG. 8, a flow chart of the manufacturing steps
used for producing ball grid array resistor network 400 are shown.
At step 410, an adhesion promoter (not shown) is screen printed
onto a sheet of copper foil and fired at 900 degrees centigrade in
a reducing atmosphere furnace. The furnace would typically contain
200 ppm of hydrogen to prevent the copper from oxidizing. The
adhesion promoter is a mixture of finely divided copper and glass
particles. The adhesion promoter increases the adhesion of the
resistor to the copper foil. Next, at step 412, a resistor paste is
screen printed onto the adhesion promoter and fired in a reducing
atmosphere furnace to form resistor 26. The resistor paste can be a
Lanthanum Boride that is commercially available from Dupont
Corporation of Wilmington, Del. Details of the design and
manufacture of such resistors are shown in U.S. Pat. Nos. 6,317,023
and 4,655,965. The contents of which are herein incorporated by
reference in entirety. The resistor can also be formed from a
mixture of glass frit and Tin Oxide. At step 414, a laser
reflective layer 404 is screen printed onto the resistors and
copper foil and cured. Laser reflective layer 404 is a titanium
dioxide filled epoxy resin. The purpose of reflective layer 404 is
to prevent the laser used during laser trimming from burning
completely through substrate 21. At step 416, the copper foil with
resistors and laser reflective layer are laminated onto the FR4
substrate 21 with an adhesive 402. Adhesive 402 can be a prepreg
layer such as an epoxy resin or can be an acrylic. Examples of some
commercially available adhesives are Vialux and Pyralux from Dupont
Corporation of Wilmington, Del. A photoresist is applied over the
copper foil and resistors at step 418. The photoresist can be
sprayed or can be a dry film resist. At step 420, the circuit lines
and ball pads are exposed in the photoresist and developed. This is
done by shining a UV light through a mask that has the desired
pattern. The circuit lines and ball pads are etched at step 422.
Substrate 21 is placed into a solution cupric chloride that removes
the exposed copper areas. Next, at step 424 the photoresist is
removed using a photoresist stripper. At step 426, resistor 26 is
laser trimmed to value. The resistors 26 and exposed layer 404 are
coated with a solder mask at step 428. The solder mask protects the
resistors and prevents shorts during soldering. At step 430, a low
melting point solder paste is screened onto ball pads 28. The
solder paste has a composition between 30 to 40 percent lead and 60
to 70 percent tin with a preferred composition of 63% tin and 37%
lead which melts at 167 degrees centigrade. Next, at step 432,
conductive bumps, spheres or balls 34 are placed onto ball pads 28.
Conductive spheres 34 are preferably made from a high melting point
solder having a composition of 10% tin and 90% lead. Alternatively,
placing the solder spheres can be omitted and the solder paste
reflowed into a conductive bump or hump shape. At step 434,
substrate 21 is placed into an oven where the solder paste 36 is
reflowed which attaches solder ball 34 to ball pad 28. BGA network
400 is cleaned and singulated or cut into individual pieces at step
436. The individual parts are electrically tested at step 438.
Analysis of Electrical Performance
[0059] A circuit analysis simulation was performed using BGA
resistor network 100 of the present invention. FIG. 9 shows a
bottom view of the resistor, ball pads and solder sphere layout
that was used in the simulation.
[0060] The substrate 21 used an FR4 material with a dielectric
constant of 4 and a loss tangent of 0.02. The substrate has a
thickness of 3 mils. The ball pad conductivity was 47000000 s/m at
0.7 mil thickness. The resistor material is 100 ohm/square at 500
angstroms thickness. The port characteristic impedance was set at
50 .OMEGA.. Metal layer 102 is floating and not grounded.
[0061] Agilent Momentum Simulation Software was used for the
resistor network simulation. S parameters were obtained through the
simulation. The S parameters were converted into Z and Y matrices
to obtain the resistor value and parasitic inductance and coupling
capacitance. The parasitic parameter of two adjacent resistors was
estimated as a two port network.
[0062] The following table shows the resistor inductance is
significantly reduced with the presence of top conductive layer
102. It is believed that the self capacitance between the resistor
and metal layer 102 cancels with the self inductance of the
resistor giving a lower inductance value.
1 parasitic coupling inductance* capacitance* Port1 resistor with
top 0.727 nH 0.23 pF conductive layer Port1 resistor without top
1.595 nH 0.18 pF conductive layer *parasitic parameters@ 2 GHz.
[0063] Referring to FIGS. 10 and 11, a smith chart of the
simulation is shown. FIG. 10 shows S11 without the top metal layer
102 and FIG. 11 shows S11 with metal layer 102. As can be seen, the
resistor inductance is significantly reduced with the top
conductive layer 102. Metal layer 102 does not affect coupling
capacitance significantly between the resistors.
[0064] By manipulating various parameters of the resistor network
design, the inductance values of the resistors can be minimized.
For example, the substrate thickness and dielectric constant can be
adjusted to help reduce the inductance. Changing the dimensions and
thickness of the ball pads and resistors also influences the
inductance.
Variations of the Invention
[0065] While the figures illustrate possible constructions of the
invention, variations are certainly possible. One possible
variation is to place resistors onto surface 23 and use a plated
through hole (PTH) to provide an electrical connection to solder
sphere 34. It is also apparent that many different numbers of
resistors may be used in accord with the present teachings for any
given application, and particular numbers of components may lend
special significance to only one or a few of the preferred specific
applications. Several different resistor material systems were
shown. Other resistor material systems could also be used in
conjunction with the present invention. For example, a polymer
thick film resistor system could be used. While the invention was
directed to a resistor termination network, it is contemplated that
the invention could be directed to other applications. For example,
the BGA resistor network could be used as a fuse array or could be
combined with inductors or capacitors to form a filter array. The
BGA resistor network could further be fabricated with a PTC
resistor material to form a resetable fuse.
[0066] While the foregoing details what is felt to be the preferred
embodiment of the invention, no material limitations to the scope
of the claimed invention are intended. Further, features and design
alternatives that would be obvious to one of ordinary skill in the
art upon a reading of the present disclosure are considered to be
incorporated herein. The scope of the invention is set forth and
particularly described in the claims hereinbelow.
* * * * *