U.S. patent application number 10/984250 was filed with the patent office on 2005-04-21 for adjustment of a clock duty cycle.
This patent application is currently assigned to Multilink Technology Corporation, a Somerset, New Jersey corporation. Invention is credited to Gu, Gong, Lakshmikumar, Kadaba R..
Application Number | 20050083091 10/984250 |
Document ID | / |
Family ID | 32107350 |
Filed Date | 2005-04-21 |
United States Patent
Application |
20050083091 |
Kind Code |
A1 |
Lakshmikumar, Kadaba R. ; et
al. |
April 21, 2005 |
Adjustment of a clock duty cycle
Abstract
Circuits for adjusting the duty cycle of a clock(s) signal
include a negative feedback loop for applying an offset signal to
the uncorrected clock signal(s). The offset signal, which
corresponds to a duty cycle error of the corrected clock signal(s),
adjusts the slicing level of the uncorrected clock signal(s) to
cause the duty cycle error to converge toward a predetermined
value, for example, zero. The techniques may be used to adjust the
duty cycle error of differential clock signals as well as
single-ended clock signals.
Inventors: |
Lakshmikumar, Kadaba R.;
(Basking Ridge, NJ) ; Gu, Gong; (Bridgewater,
NJ) |
Correspondence
Address: |
FISH & RICHARDSON P.C.
CITIGROUP CENTER 52ND FLOOR
153 EAST 53RD STREET
NEW YORK
NY
10022-4611
US
|
Assignee: |
Multilink Technology Corporation, a
Somerset, New Jersey corporation
|
Family ID: |
32107350 |
Appl. No.: |
10/984250 |
Filed: |
November 9, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10984250 |
Nov 9, 2004 |
|
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10282398 |
Oct 29, 2002 |
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6833743 |
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Current U.S.
Class: |
327/157 |
Current CPC
Class: |
H03K 5/1565 20130101;
H03K 5/082 20130101 |
Class at
Publication: |
327/157 |
International
Class: |
H03B 019/00 |
Claims
1-18. (canceled)
19. A method comprising: obtaining one or more corrected clock
signals based on one or more uncorrected clock signals; obtaining a
DC offset signal corresponding to a duty cycle error of the one or
more corrected clock signals; and adjusting a slicing level for the
one or more uncorrected clock signals based on the DC offset
signal, wherein the adjusting includes adding the DC offset signal
to the one or more uncorrected clock signals.
20. The method of claim 19 including repeating said obtaining one
or more corrected clock signals, obtaining a DC offset signal and
adjusting a slicing level, wherein adjusting the slicing level
causes the duty cycle error to converge toward a predetermined
value.
21. The method of claim 20 wherein the duty cycle error converges
toward zero.
22. The method of claim 21 wherein the duty cycle error is a
differential duty cycle error for a pair of corrected clock
signals.
23. A method comprising: receiving an uncorrected clock signal as
an input to a negative feedback loop; producing an integrated
charge signal that is proportional to a clock duty cycle error;
producing an offset voltage signal based on the integrated charge
signal; and adjusting a slicing level for the uncorrected clock
signal based on the offset voltage, wherein the adjusting includes
adding the offset voltage signal to the uncorrected clock
signal.
24. The method of claim 23 wherein adjusting the slicing level
includes adding the offset voltage signal to the uncorrected clock
signal.
25. The method of claim 24 including: amplifying a signal
representing a sum of the uncorrected clock signal and the offset
signal; clamping the amplified signal; and producing a corrected
clock signal based on the clamped signal.
26. The method of claim 25 wherein the integrated charge signal is
proportional to a duty cycle error of the corrected clock
signal.
27. The method of claim 25 including producing a corrected clock
signal having a duty cycle that converges toward a predetermined
value.
28. The method of claim 25 including producing a corrected clock
signal having a duty cycle that converges toward about 50%.
29. The method of claim 25 including repeatedly producing an offset
voltage signal based on the integrated charge signal and adjusting
a slicing level for the uncorrected clock signal based on the
offset voltage.
30. The method of claim 25 wherein producing an integrated charge
signal includes producing a signal indicative of a time difference
between high and low states of the clock signal, wherein the
integrated charge signal is proportional to an integrated value of
a deviation of the clock signal from a predetermined duty
cycle.
31. A method comprising: receiving a plurality of uncorrected clock
signals as input to a negative feedback loop; producing a net
integrated charge that is proportional to a duty cycle error;
producing an offset voltage signal based on the net integrated
charge; and adjusting a slicing level for the uncorrected clock
signals based on the offset voltage, wherein the adjusting includes
adding the offset voltage signal to the uncorrected clock
signals.
32. The method of claim 31 wherein adjusting the slicing level
includes adding the offset voltage signal to the uncorrected clock
signals.
33. The method of claim 32 including: amplifying signals each of
which represents, respectively, a sum of one of the uncorrected
clock signals and the offset signal; clamping the amplified
signals; and producing corrected clock signals based on the clamped
signals.
34. The method of claim 33 wherein the net integrated charge signal
is proportional to a differential duty cycle error of the corrected
clock signals.
35. The method of claim 33 including producing corrected clock
signals having a differential duty cycle that converges toward a
predetermined value.
36. The method of claim 33 including producing corrected clock
signals having a differential duty cycle that converges toward
about 50%.
37. The method of claim 33 including repeatedly producing an offset
voltage signal based on the net integrated charge and adjusting a
slicing level for the uncorrected clock signals based on the offset
voltage.
38. The method of claim 33 wherein producing an integrated charge
signal includes producing a signal indicative of a time difference
between high and low states of the clock signal, wherein the
integrated charge signal is proportional to an integrated value of
a deviation of the clock signal from a predetermined duty cycle.
Description
BACKGROUND
[0001] The present disclosure relates to adjustment of a clock duty
cycle.
[0002] Clock signals may be used in electronic circuits to provide
timing information. An important aspect of a clock signal in many
applications is the clock duty cycle, which may be defined as the
ratio of the time the clock pulse is at a high level to the clock
period. For example, a clock signal that is at the high level for
one-half of the clock period and the low level for one half the
clock period has a 50% duty cycle.
[0003] A 50% duty cycle is desirable for many applications. For
example, in clock-driven digital systems requiring high speed
operation, both the rising and falling edges of the clock signal
may be used to increase the total number of operations. Such
systems may require a 50% duty cycle to help prevent or reduce
jitter and other timing related distortions. In such systems, the
duty cycle may be critical to proper performance of the system.
Unfortunately, the duty cycle of the clock signal may become
distorted or degraded, for example, as a result of semiconductor
process errors. Other conditions also may cause the duty cycle to
deviate from the desired value. Duty cycle correction circuits may
be used to correct or adjust such distortions.
BRIEF DESCRPTION OF THE DRAWINGS
[0004] FIG. 1 is a diagram of a circuit for adjusting the duty
cycle of differential clock signals.
[0005] FIGS. 2(a) through 2(d) are examples of timing diagrams for
FIG. 1.
[0006] FIG. 3 illustrates further details of the circuit of FIG. 1
according to one implementation.
[0007] FIG. 4 illustrates details of a charge pump that may be used
in the circuit of FIG. 1 according to one particular
implementation.
[0008] FIG. 5 is a diagram of a circuit for adjusting the duty
cycle of a single-ended clock signal.
SUMMARY
[0009] Circuits for adjusting the duty cycle of a clock(s) signal
include a negative feedback loop for applying an offset signal to
the uncorrected clock signal(s). The offset signal, which
corresponds to a duty cycle error of the corrected clock signal(s),
adjusts the slicing level of the uncorrected clock signal(s) to
cause the duty cycle error to converge toward a predetermined
value, for example, zero. The techniques may be used to adjust the
duty cycle error of differential clock signals as well as
single-ended clock signals.
[0010] In various implementations, the feedback loop may include a
charge pump and an integrator to receive an output from the charge
pump. A net charge in the integrator may correspond to the duty
cycle error. A driver may be provided to amplify and clamp the
values of the clock signals after applying a DC offset signal to
the uncorrected clock signal(s).
[0011] Various implementations may include one or more of the
following advantages. For example, the circuits may be used to
correct a signal having an arbitrary duty cycle to a signal having
the same frequency with a 50% duty cycle. Use of an integrator in
the feedback loop may allow the gain to be sufficiently large to
minimize or reduce the duty cycle error.
[0012] Other features and advantages will be readily apparent from
the following detailed description, the accompanying drawings and
the claims.
DETAILED DESCRIPTION
[0013] As shown in FIG. 1, a circuit 20 may be used to adjust the
differential duty cycle for a pair of clock signals (CN, CP). In
particular, the circuit 20 may be used to correct the differential
duty cycle and cause it to converge toward 50%.
[0014] The circuit uses a negative feedback configuration that adds
a DC offset signal (V.sub.OS) to the uncorrected clock signals (CN,
CP). The DC offset voltage (V.sub.OS) may be added to the input
clock signals using summers 22, 24, to produce corrected clock
signals, CN' and CP', respectively.
[0015] The corrected clock signals (CN', CP') are applied as inputs
to a driver 26 which forms part of the feedback loop. The output
signals (OUTN, OUTP) from the driver 26 represent the clock signals
with the corrected differential duty cycle. The driver may provide
a high gain and may clamp the maximum amplitude of the output clock
signals at a fixed value to prevent amplitude variation.
[0016] The feedback loop also includes a differential charge pump
28 and integrator 30 which together produce an error voltage
proportional to the duty cycle error. The output clock signals from
the driver 26 are applied, respectively, to input terminals (UP,
DN) of the charge pump. When the signal at the terminal UP is a
high level signal and the signal at the terminal DN is a low level
signal, the charge pump sources a current I.sub.UP from one output
(I) and sinks substantially the same amount of current into the
second output {overscore (I)}. Conversely, when the signal at the
terminal input UP is a low level signal and the signal at the
terminal DN is a high level signal, the currents flow in the
opposite direction--in other words, the charge pump sources a
current I.sub.DN from the output {overscore (I)} and sinks
substantially the same amount of current into the output I. The
outputs of the charge pump are indicative of the instantaneous time
difference between the high and low states of the clock signals.
For example, if the duty cycle of the clock signals were exactly
50%, the average net output of the charge pump would be about
zero.
[0017] The current signals from the output terminals (I and
{overscore (I)}) of the charge pump are applied as input signals to
the integrator 30. The integrator may include capacitors (not shown
in FIG. 1) which are charged and discharged depending on the output
currents from the charge pump 28. The net charge on the capacitors
is proportional to the integrated value of the deviation of the
clock signals from a predetermined duty cycle, for example, a 50%
duty cycle. The DC offset voltage (V.sub.OS) corresponds to the net
charge and represents the duty cycle error of the differential
clock signal (CP'-CN'). For example, if the differential duty cycle
were exactly 50%, then the DC offset voltage (V.sub.OS) would be
about zero volts. On the other hand, as the duty cycle deviates
from 50%, the DC offset voltage will vary as well. Applying the DC
offset voltage signal to the input clock signals CN, CP adjusts the
zero crossing point, or slicing level, of the input clock signals
so that the differential duty cycle converges toward 50%.
[0018] FIG. 2(a) illustrate an example of a timing diagram in which
it is assumed that the input clock signals have a duty cycle that
deviates from 50%. In that case, the duty cycle of the differential
clock signal (CP-CN) also will deviate from 50%. The feedback loop
causes the offset voltage V.sub.OS to be applied to the input clock
signals, effectively shifting the zero crossing (i.e., slicing
level) of the clock signals, as illustrated in FIG. 2(b). Although
each of the modified clock signals (CP', CP') has approximately a
50% duty cycle, the duty cycle of the differential clock signal
(CP'-CP') may still deviate from 50% as a result of the amplitude
variations in the modified clock signals. The driver 26 amplifies
and clamps the modified clock signals to produce the output clock
signals (OUTP, OUTN), as illustrated in FIG. 2(c). The output clock
signals have approximately a 50% duty cycle. Furthermore, as shown
by FIG. 2(d), the differential clock signal, OUTP-OUTN, also has
approximately a 50% duty cycle.
[0019] A particular implementation of the duty cycle correction
circuit is shown in FIG. 3. In this implementation, the driver
includes a pair of single-ended drivers, such as complementary
metal oxide semiconductor (CMOS) inverters 32, 34. The input clock
signals (CP, CN) may be AC-coupled through the respective
capacitors C.sub.C to the CMOS inverters which drive external loads
shown as a pair of capacitors C.sub.L. The input to each inverter
is the sum of the offset voltage (V.sub.OS) and the corresponding
uncorrected clock signal.
[0020] In other embodiments, the driver 26 may be implemented as a
differential amplifier.
[0021] The charge pump 28 may operate at the input clock rate. One
specific implementation of the charge pump is illustrated in FIG. 4
and includes a p-type MOS current source, an n-type MOS current
sink, and CMOS switches to direct the currents. Other types of
charge pumps may be used as well.
[0022] The integrator 30 may be implemented as a passive integrator
including one or more capacitors. Alternatively, as shown in FIG.
3, the feedback loop may include an active integrator. In the
implementation of FIG. 3, the active integrator 30 includes a
differential operational amplifier 38 and feedback capacitors
C.sub.p, C.sub.n. The output clock signals (OUTP, OUTN) drive the
charge pump 28, which charges and discharges the capacitors
C.sub.p, C.sub.n. The active integrator keeps the potentials of the
output terminals of the charge pump substantially equal to one
another. The charge pump output currents may, therefore, be
independent of the duty cycle error, as well as the offset voltage
(V.sub.OS), thereby relaxing requirements on the charge pump. The
integrator outputs are fed back through a pair of resistors R.sub.F
to control the DC voltage across the AC-coupling capacitors
C.sub.C.
[0023] To ensure stability of the duty cycle correction loop, the
values of the feedback capacitors C.sub.p and C.sub.n in the
integrator should be large enough to provide sufficient phase
margin.
[0024] In some applications, the input offset voltage
(V.sub.offset) of the operational amplifier 38 may cause a small
duty cycle error in the output. The error in the output is
proportional to the input offset voltage and is inversely
proportional to the slew rate (r) and period (T) of the input
signal. For example, assuming that the rise and fall times are one
fourth the period--r.multidot.(T/4)=V.sub.DD=1.2 volts--then an
input offset voltage of 10 millivolts (mV) would result in an
output duty cycle error or about only 0.4%.
[0025] Although the particular circuits described above are
illustrated in the context of differential clock signals, the
techniques may be used for adjusting the duty cycle of a
single-ended clock signal as well. As shown in FIG. 5, a negative
feedback loop may be used to adjust the duty cycle of the
single-ended clock signal CP and to cause it to converge toward
50%. The amplified clock output signal (OUT) from the driver 26
serves as the input to the UP terminal of the charge pump 28. The
clock output signal (OUT) also may serve as the input to an
inverter 40 whose output is provided to the DN terminal of the
charge pump. The output current from the terminal (I) of the charge
pump serves as the input to the integrator 30. The DC offset
voltage at the output of the integrator represents the DC component
of the clock signal (CP') which, in turn, corresponds to the duty
cycle error. Feeding the DC offset voltage back to the summer 24
causes the duty cycle to converge toward 50%.
[0026] The foregoing techniques may be used for clock signals at
high or low frequencies, but may be particularly advantageous for
frequencies of 1.25 gigahertz (GHz) and higher. The techniques may
be useful, for example, in high-speed digital transmitters in which
the output data is clocked by a double-edge-triggered (DET)
flip-flop. The techniques may be used in other systems as well.
[0027] Other implementations are within the scope of the
claims.
* * * * *