U.S. patent application number 10/442934 was filed with the patent office on 2005-04-07 for focal plane processor for ir detection.
Invention is credited to Adin, Amnon, Elkind, Shimon.
Application Number | 20050072923 10/442934 |
Document ID | / |
Family ID | 11075949 |
Filed Date | 2005-04-07 |
United States Patent
Application |
20050072923 |
Kind Code |
A1 |
Elkind, Shimon ; et
al. |
April 7, 2005 |
Focal plane processor for IR detection
Abstract
A focal plane array detector in a sensor for IR imaging. Pixel
readout and analog to digital conversion is performed in an
integrated circuit which includes the imaging array. The charge of
each pixel is accumulated in a capacitor and a digital to analog
charge converter cancels this charge. A controller controls this
charge converter providing the appropriate amount of charge. An
analog to digital converter incorporating a comparator switches the
controller on/off. In some embodiment a programmable device
external to the sensor participates in the control of the analog to
digital converter. In a typical embodiment of the invention a cycle
generator controls the charge output of the digital to analog
converter. In a preferred embodiment the analog to digital
converters are grouped wherein all such converters group operate
simultaneously.
Inventors: |
Elkind, Shimon; (Carmiel,
IL) ; Adin, Amnon; (Haifa, IL) |
Correspondence
Address: |
WELSH & FLAXMAN LLC
2450 CRYSTAL DRIVE
SUITE 112
ARLINGTON
VA
22202
US
|
Family ID: |
11075949 |
Appl. No.: |
10/442934 |
Filed: |
May 22, 2003 |
Current U.S.
Class: |
250/332 ;
348/E5.09 |
Current CPC
Class: |
H03M 1/1225 20130101;
H04N 5/33 20130101 |
Class at
Publication: |
250/332 |
International
Class: |
H01L 025/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 6, 2002 |
IL |
150058 |
Claims
1. A focal plane array containing rows and columns of pixels for IR
imaging, wherein pixel readout and analog to digital conversion is
performed in an integrated circuit inclusive of said array,
comprising: at least one capacitor per pixel, for accumulating the
charge of a detector element. at least one analog to digital
converter (ADC) incorporating a comparator for on/off switching a
digital controller, wherein said controller controls a digital to
analog charge converter for providing an appropriate amount of
charge to cancel out the charge of one pixel at a time by one ADC,
and switching elements for connecting said pixels to said ADCs.
2. A focal plane array for IR imaging as in claim 1 comprising a
cycle generator, for controlling a charge output of a digital to
analog converter to cancel out said charge of said pixel.
3. A focal plane array for IR imaging as in claim 2 wherein said
cycle generator is a ramp generator connected through a capacitor
to the input port of said at least one ADC and to a column
line.
4. A focal plane array for IR imaging as in claim 3 wherein said
ramp generator produces at least one linear ramp.
5. A focal plane array for IR imaging as in claim 1 wherein said
comparator includes an integrator as an input stage.
6. A focal plane array for IR imaging as in claim 1 and wherein
said focal plane array is cooled.
7. A focal plane array for IR imaging as in claim 1 wherein said
ADCs are allocated in groups, wherein all ADCs of one group operate
simultaneously.
8. A focal plane array for IR imaging as in claim 7 each of said
groups contain at least two ADCs per each column.
9. A focal plane array for IR imaging as in claim 7 and wherein one
multi ramp generator serves at least one group of ADCs.
10. A focal plane array for IR imaging as in claim 7 and wherein
one counter serves at least one group of ADC's.
11. An IR imaging system as in claim 1 and wherein an external
programmable logic device connected via a communication channel
participates at least in the control of said ADC.
12. An IR imaging system as in claim 11 wherein said external
programmable device also contains a buffer, for providing a
interface between the pixels' readout stream and the timing
parameters and communications protocols of a user.
13. A method for digitally quantifying IR radiation impinging on a
focal plane array, wherein pixels readout and analog to digital
conversion is performed in an integrated circuit inclusive of said
array, employing at least one circuit for each column of said
array, and wherein a charge on each of said pixels is converted to
a digital number, comprising the steps of: on/off switching by a
comparator of a digital controller controlling a digital to analog
charge converter for supplying a charge by a digital to analog
converter in an appropriate quantity to cancel out said charge of
said pixel, and generating a dual ramp conversion cycle for a
substantially two step analog to digital conversion of said charge
and providing a most significant count in a first step and a least
significant count of said charge in a second step.
14. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 13 wherein an analog to digital
conversion of the charge in every pixel is done on the focal plane
in two quantification steps, a first step providing the most
significant bits and a second step the least significant bits of
said quantification.
15. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 14 and wherein the combination of the
most significant bits and the least significant bits into one
digital number is done partially externally, outside said focal
plane array.
16. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 13 and wherein a cycle is generated
for controlling the charge output of a digital to analog converter
to cancel out said charge of said pixel.
17. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 16 and wherein a cycle generated
contains at least one ramp .
18. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 13, and wherein a tradeoff between
the resolution of said quantification and the frame rate is enabled
by programming said dual ramp conversion cycle.
19. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 13 and wherein said charge of said
pixel is loaded first into a capacitor of an integrator wherein
said integrator is connected to a column of said array, and wherein
said charge is later digitally quantified.
20. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 13, and wherein the pixels of said
array are grouped, such that quantification is performed
simultaneously for all members of said group, each group at a time,
allocating at one conversion time one ADC to each member of each
group.
21. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 20, and wherein for said each group
of pixels, one common ramp generator produces at least one linear
voltage ramp whereby in each ADC a low level DC current is created
by said ramp driving a capacitor connected to a virtual ground of
an integrator.
22. A method for digitally quantifying IR radiation impinging on a
focal plane array as in claim 20, and wherein each of said groups
contain two rows of said array.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to IR focal plane
array detectors. More specifically, the present invention is in the
field of detector pixel signal readout and processing.
BACKGROUND OF THE INVENTION
[0002] Photonic detector devices respond to received photons by
creating an electric effect which can be quantified and hence
provide information as regards the flux of the received photons.
Focal plane arrays (FPAs) of detectors are used to obtain images of
objects, whereby each detector provides a pixel in the image array.
In the image, each pixel is provided with a unique address and a
numeric value, which can further be used for manipulating the image
for extracting information from the image.
[0003] Thermal Infra red (IR) FPAs are used for obtaining images in
the thermal IR range. The resolution of an imaging array in the IR
is limited by two factors, namely noise equivalent temperature
(NET) and spatial noise, of the analog chain: the focal plane
processor (FPP), the external analog circuitry and the analog to
digital conversion. An external interference, such as RF
interference or signals induced by the digital system may also
degrade the performance. The temporal noise of the FPP can be
reduced by careful design to be negligible relative to the signal
noise, providing low NET values. Yet, to overcome the spatial
noise, an external process of non uniformity correction (NUC) must
be carried out. A "two point correction" process is generally used,
assuming the analog chain to be linear and having stable offset and
gain. The final results depend upon the validity of these
assumptions, and the spatial resolution becomes a main restriction,
limiting the dynamic range and requiring frequent calibrations. The
FPP is kept at a steady temperature, e.g. at about 77.degree. K
while the external circuitry is exposed to wide temperature
variations, degrading the gain and offset stability. Also, the FPP
is relatively shielded against external interference, which is not
the case with the external elements. In order to reach such a low
temperature and keep it steady, the sensor is disposed within a
cooled dewar. The dewar has electric connections installed in the
walls, in order to facilitate electrical connection with external
circuits.
[0004] Heat production is a matter of high importance in the design
of FPPs. The efficiency of the cooling system being very low, the
amount of power consumed by the circuits of the FPP at any time
must also be limited. Sampling rates, sampling resolution, and
output rates are factors which affect heat production. The use of
components and combinations thereof having a low power consumption
is favoured in the design of cooled FPPs. A trade-off between
imaging parameters is a compromise often imposed for obtaining
desirable image parameters. Accordingly, image frame rate at the
expense of image resolution or image size are known in the art.
Continuous attempts are made by various system designers to
overcome the limitations described, striving to attain a high frame
rate and a high resolution, with a reasonable power
dissipation.
[0005] The value of the electric effect associated with each
detector of the FPA is converted into a digital format, before it
can be subjected to digital image processing. However, there are a
number of critical reasons favouring conversion to digital format
at an early stage as possible of the signal corresponding to each
pixel. U.S. Pat. No. 5,886,659 discloses an on-focal plane analog
to digital conversion application. Benefits of having the
analog-to-digital conversion in the focal plane are discussed in
that publication, the contents of which are incorporated herewith
by reference.
[0006] Integrated converters have used several types of conversion
schemes. Single-slope analog to digital conversion is a
well-established technique. For example, U.S. Pat. No. 5,742,058
discloses an analog to digital conversion in the focal plane
utilizing a single slope conversion cycle. The Dual-slope
conversion provides better accuracy and stability (R. Van De
Plassche, cited below). Yet, both techniques require quite long
conversion times, being based on counters: the full-scale time of
an n-bit single-slope converter is 2.sup.n*Tc, where Tc is the
clock cycle time. The dual slope requires up to twice that time.
The dual-ramp single-slope method, described by R. Van De Plassche
in: INTEGRATED ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS,
Kluwer Academic Press, pp. 274-289, 1994, the contents of which are
incorporated herein by reference, promises both high resolution and
reduced conversion time.
[0007] It is on the background hitherto described, that the present
invention was conceived. The invention described below provides a
basis for increasing the rate of sampling digitally at the FPP
level, without compromising the resolution of each pixel.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is schematic description of the main structural
features of an IR sensor system in which the invention is
implemented;
[0009] FIG. 2 is a flow chart describing schematically the process
of the invention;
[0010] FIG. 3A is a schematic description of the pixel charge
converting circuit of the invention;
[0011] FIG. 3B is a charge DAC implementation in accordance with an
embodiment of the invention;
[0012] FIG. 3C is another charge DAC implementation in accordance
with an embodiment of the invention;
[0013] FIG. 4 is an implementation of a pixel charge converting
circuit of the invention adapted for an array of pixels;
[0014] FIG. 5A is a detailed implementation of the circuit
described in FIG. 4;
[0015] FIG. 5B is a description of the main wave-shape forms in the
circuit of FIG. 5A, implemented in the course of one conversion
cycle;
[0016] FIG. 6. is a schematic description of the interconnections
existing between the main components of the imaging system, in
accordance with the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0017] A system of the invention is implemented in association with
an integrated circuit device, a focal plane processor (FPP). The
FPP is disposed within a cooled dewar, as described schematically
in FIG. 1 to which reference is now made. A longitudinal cross
section elevation in an IR sensor is shown, in which the FPP 14 of
the invention is functional. Metal plate 16 is adjacent cold finger
18. The FPP is thermally connected while electrically isolated,
with metal plate 16 through ceramic plate and spacers 20. To
ceramic plate and spacers 20, which is electrically insulating, are
connected wire bonds 22. FPP chip 14 supports detector array chip
24 through indium bumps 26, whereby for each detector in the
detector array chip 24 there exists one bump connecting to the
respective pixel in the FPP chip 14. Penetrating through the
envelope of the dewar 26 are connecting pins 28. Wire bonds 22
connect pads (not shown) of FPP 14 to the appropriate connecting
pins, having intermediate pads on the ceramic plate 20. The
connecting pins provide electrical contact to external circuits
30.
[0018] The process of the invention is summarized schematically in
FIG. 2 to which reference is now made. In step 40, photon flux is
captured on a detector pixel, causing a corresponding build-up of
charge in the respective FPP pixel in step 42. In step 44 the
charge in the FPP pixel is quantified digitally. In step 46 the
results of the quantification are processed and in step 48 the
processed data is transmitted to a programmable logic outside of
the dewar for further processing. In step 50, digital numbers are
calculated and pixels are remapped to restore the image.
FPP Pixel Charge Digital Conversion
[0019] The charge accumulated in the pixel in the FPP of the
invention is according to the present invention converted to a
digital form by a circuit modified from Van De Plassche, cited
above. The original circuit, known as a dual ramp single slope
converter, converts input voltage into a digital number. The
modification of the circuit to a charge converter circuit, and the
function thereof are described in reference to FIG. 3A. The charge
ADC 52 is composed of comparator 66, charge output
digital-to-analog converter (DAC) 62 and of controller 64. The
input port of ADC 52 is line 67, which connects between the output
port of the DAC 62 and comparator 66. Qpx, the charge to be
converted, is stored in pixel capacitor 60. DAC 62 produces a
charge of opposite polarity, the value of which is controlled
digitally by the controller 64. The digital control value (in bits)
which eliminates Qpx (as indicated by the comparator 66 output) is
the conversion output. Two exemplary implementations of a charge
DAC of the invention are described in FIGS. 3B and 3C to which
reference is now made. In FIG. 3B a DAC implementation is described
in which the charge for elimination of the Qpx is provided by a set
of several capacitors such as capacitor 68, used in a successive
approximation mode. It is also possible to use only the smallest
capacitor, switching it many times and counting the number of
switching necessary to eliminate the converted charge. In FIG. 3C,
the required charges are achieved by switching-on the relevant
current sources, e.g. source 69, for a given time, producing charge
packets accordingly.
[0020] However, in practice, the pixels are arranged in the
framework of a matrix of rows and columns which may be long such
that certain implications are inevitable trying to adapt a solitary
pixel ADC application to a pixel array application, such as a
column of the array . Accordingly, the following two concerns must
be dealt with. First, the long column line adds a parasitic
capacitance, Ccl, the value of which is about one order of
magnitude larger then the pixel capacitor Cpx. Second, during the
conversion, a cross-talk exists between adjacent column lines,
impairing the function of the matrix.
[0021] In accordance with the present invention, an integrator, the
input of which is a virtual ground, is added as a first stage of
the comparator of the charge ADC circuit. This architectural
feature helps to overcome the above mentioned problems as the
column line in this configuration becomes connected to a virtual
ground. Such a configuration is described in FIG. 4 to which
reference is now made. Integrator 70, is disposed between the
comparator 72 and the column line 74, The charge to be converted is
stored in the integrator's capacitor 76, whereas the charge
injected from DAC 78 into the virtual ground, eliminates this
charge as described above.
[0022] The use of an FPA of the invention is typically in IR
imaging applications, in which accurate reference to the absolute
temperature of a pixel is not required. Rather, in an IR imaging
application, the accuracy of the differences among the different
pixels is the matter of relevance. Accurate variability measurement
and conversion can be supported by the "dual ramp single slope ADC"
used in some embodiments of the present invention.
[0023] The "dual ramp single slope ADC" employs a quantification
cycle which implements two steps. In the first step MS (most
significant) part of the numeric value is determined, and in a
second step, LS (least significant) part of the numeric value of
the charge is determined. The two parts of the digital values of
the measured quantity must be combined to form a complete digital
word, as will be explained later on. In the framework of a pixel
array, the readout and quantification are performed in the context
of columns and rows as has been discussed above, and will be
further explained with reference to FIGS. 5A and 5B. In FIG. 5A is
shown an ADC circuit in accordance with a preferred embodiment of
the invention, the function of which is explained with reference to
the conversion cycle and switching sequences described in FIG.
5B.
[0024] At time t.sub.0, the quiescent output voltage of integrator
90, is forced by closing momentarily switch S1 91 to Vpch,
(pre-charge voltage), which is also the reference voltage for
comparator 92. Closing momentarily switch S3 94 at time t1, the
charge of a pixel, accumulated in capacitor Cpxl 96, is transferred
to integrator 90, lowering the output voltage accordingly. Closing
switch S4 98 at time t.sub.2, a constant current source is
established by the combination of a linear ramp voltage (ramp 148
of FIG. 5B), the capacitor C1 100 and the virtual ground of the
integrator. Switch S5 102 closes simultaneously with switch S4 98.
Counter 104, which has been reset earlier, starts counting the
clock pulses while the integrator output goes up linearly. Reaching
Vpch at time t.sub.3 the integrator activates the comparator. The
period t.sub.3-t.sub.2 is a true indication of the signal to be
measured. Yet, the output of the comparator is synchronized to the
next clock, and only then it opens switch 98 and samples the
counter reading (switch S5 102 remains closed until t.sub.4 in
order to serve other ADCs). As a result, the output of the
integrator continues to rise for a period .DELTA.t (in FIG. 5B), so
that the counter reading provides only the MS count, and a value,
proportional to .DELTA.t should be subtracted with higher
resolution. This is done by resetting counter 104 and closing again
switch S5 102 and switch S4 98 at time t.sub.5, which connects a
second ramp (ramp 150 in FIG. 5B), the slope of which is positive
and slower.
[0025] The output of the integrator goes down and reaches Vpch at
time t.sub.6, disabling the comparator. The counter reading is
sampled at time t.sub.6, providing the LS count to be subtracted
(with the proper weight ) from the digital number represented by
the former MS bits. The ratio between the absolute values of the
slopes of the two ramps determines the number and weight of LS
bits. The value of .DELTA.t is nominally less then one clock time.
Yet, in practice, due to delays in the comparator and the
switching, it might reach as high as some clock times, the actual
number of which depends also upon the clock frequency.
Consequently, the period and the number of counter stages assigned
to the second ramp is to be increased accordingly.
[0026] Being used in IR imagers, an offset thus created is
compensated for in the non-uniformity correction (NUC) procedure,
provided it has a constant value. An advantage associated with the
ADC implementation in accordance with the present invention,
results from the comparator being activated at a constant input
level by a signal of a constant slope, independent of the converted
signal amplitude. Also, the focal plane is cooled to a very stable
temperature. Therefore, the delays and the resulting offset are
very stable. Another advantage obtained by using the invented ADC
in focal plane arrays is the connection of the column line to a
virtual ground. The column lines are long and parallel, resulting
in a significant coupling capacitance between neighbors. During the
period of transfer of charge from the pixel to the ADC, the column
line potential is temporarily raised, only to revert to the
original value by the end of that period. Therefore, finally no
charge injection occurs between adjacent column lines.
[0027] The combination a common linear voltage ramp (148 or 150 in
FIG. 5B) driving the capacitor 100 (in FIG. 5A) into the virtual
ground of the integrator, enables applying low level DC current
sources of approximately the same amplitude to all the ADCs. Thus
the use of current mirrors, which are not accurate enough
(especially in the nano-ampere levels), is avoided. The ramp
generator 106 (in FIG. 5A) is basically an integrator, fed at each
step of the conversion cycle by a constant current source of
appropriate amplitude and polarity.
[0028] In order to further decrease the conversion time without
loosing resolution, the "dual ramp single slope ADC" concept can be
further extended into a multi ramp ADC, where additional conversion
steps, having successively decreased weights, are employed. This
may be desirable in the case of very high resolution
converters.
Programmable Logic Applications in the Present Invention
[0029] The FPP of the present invention is applicable to IR imagers
in general. Yet, it is especially advantageous in cooled imagers,
where the heat dissipated in the focal plane should be removed by
cooling to a low and stable temperature. Therefore, architectural
and functional considerations of the make-up of the integrated
circuit have been made in order to decrease the power dissipation
in the FPP integrated circuit. In accordance with one aspect of the
invention, a programmable logic device, external to the dewar in
which the integrated circuit of the sensor is disposed, performs
several tasks. The first one relates to the digital functions of
the ADCs which are partially performed outside of the dewar. These
functions being performed in the uncooled environment, serve to
decrease the amount of components and heat dissipation in the FPP,
therefore potentially improving the overall performance of the
imager. As explained above, the digital value of each pixel is
obtained in a MS part and an LS part. The two parts, after initial
processing in the FPP, are finally combined to form one digital
word in the external programmable logic device. The second task
relates to the remapping of the pixels. The data transmission from
the FPP to the programmable logic is optimized to minimize focal
plane power dissipation. Consequently, the bits of a digital word
transmitted from the dewar include a mixture of data from two
pixels. Such mixed data is remapped in the external logic device,
to restore the image.
[0030] The external programmable logic device also adds flexibility
and optimizes the conversion cycle. Whereas the order of succession
of the various conversion steps is fixed, the duration of each step
is controlled externally. Thus, the duration of each step is set as
required by the actual performance sequence, avoiding the need to
reserve lengthy intervals of time for confidence margins. The data
transfer associated with this aspect of the invention is described
with reference to FIG. 6. The detector assembly 170, includes a
focal plane module 172 and an external proximity board 174. The
proximity board is a printed circuit board, placed close to the
dewar pins, upon which the programmable logic such as FPGA (field
programmable gate array) 176, a clock generator 178 and power
supply regulation circuits 180 are mounted. In the focal plane
module 172, the detector component 182 and the s FPP 184 are
included. The interconnections between the proximity board 174 and
the focal plane module 172 are divided into four groups: regulated
FPP power supplies bus, slow communications link, FPP clock and
timing link and the raw data bus.
[0031] Through the conventional comparatively slow communication
bus, various operation parameters of the FPP, which are not
directly involved in the timing of the analog-to-digital conversion
steps, are controlled, These include, inter alia,
"integrate-then-read" (ITR) or "integrate-while-read" (IWR) modes
of operation, working points, readout window size and location,
etc. One parameter should be mentioned here, namely the resolution
of the analog-to-digital conversion. The duration of a conversion
cycle depends also on the resolution, increasing with the
resolution. Some bits of the slow communication stream control the
resolution, e.g. a 13 bit or a 15 bit resolution, enabling a
trade-off between the resolution and the frame-rate.
[0032] A faster link carries to the FPP the clock signal and the
timing information of the conversion steps, mentioned earlier. In
this fast channel, a stream of short pulses is sent on a wire from
the external programmable logic to the FPP, where each pulse is
recognized in the FPP as the start or end of a specific step.
Programming the intervals between the pulses, the optimal
conversion duration is determined. The raw data bus carries the
partially processed data produced by the ADCs, from the FPP to be
finally processed and remapped in the programmable logic
device.
[0033] A different aspect of the imaging array which relates to the
external programmable logic, is its exploitation as a user
interface. Thus, in some embodiments of the invention, the
programmable logic device can be used also as an interface to the
external system 190 in FIG. 6, simplifying the users' interaction
with the FPP. While the FPP of the invention operates with the
optimal clock and timing for the conversion, the user can approach
the buffered output on the programmable logic implementing specific
communications protocol and clock. The clock of the user system is
independent of the clock of the detector assembly, and does not
have to be synchronized with it. The dialog between the two systems
can then be established by an handshaking implemented on the
programmable logic device.
[0034] As described so far, the system of the invention is most
beneficial in cooled FPPs, typically implemented in thermal IR
imaging. It is nevertheless contended that the same system can be
used in any FPP systems, for other imaging purposes, such as
visible, near infra-red and X-ray. In such systems, heat
dissipation in the FPP may be less critical, but the benefits of
the system are still evident.
* * * * *