U.S. patent application number 10/952105 was filed with the patent office on 2005-03-31 for transistor having a protruded drain and method of manufacturing the transistor.
This patent application is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Chang, Dong-Ryul, Lee, Soo-Cheol, Lee, Tae-Jung.
Application Number | 20050067662 10/952105 |
Document ID | / |
Family ID | 34374213 |
Filed Date | 2005-03-31 |
United States Patent
Application |
20050067662 |
Kind Code |
A1 |
Lee, Tae-Jung ; et
al. |
March 31, 2005 |
Transistor having a protruded drain and method of manufacturing the
transistor
Abstract
A field effect transistor includes a gate that is formed in a
channel region of an active region defined on a substrate. A source
is formed at a first surface portion of the active region that is
adjacently disposed at a first side face of the gate. A drain is
formed at a second surface portion of the active region that is
opposite to the first surface portion with respect to the gate. The
drain has a protruded portion that is protruded from a surface
portion of the substrate.
Inventors: |
Lee, Tae-Jung; (Hwasung-gu,
KR) ; Lee, Soo-Cheol; (Seoul, KR) ; Chang,
Dong-Ryul; (Suwon-si, KR) |
Correspondence
Address: |
Steven M. Mills
MILLS & ONELLO LLP
Suite 605
Eleven Beacon Street
Boston
MA
02108
US
|
Assignee: |
Samsung Electronics Co.,
Ltd.
|
Family ID: |
34374213 |
Appl. No.: |
10/952105 |
Filed: |
September 28, 2004 |
Current U.S.
Class: |
257/408 ;
257/E21.417; 257/E21.427; 257/E21.43; 257/E29.04; 257/E29.256;
257/E29.268 |
Current CPC
Class: |
H01L 29/7816 20130101;
H01L 29/0882 20130101; H01L 29/0847 20130101; H01L 29/7834
20130101; H01L 29/66689 20130101; H01L 29/086 20130101; H01L
29/66628 20130101; H01L 29/66659 20130101; H01L 29/7835
20130101 |
Class at
Publication: |
257/408 |
International
Class: |
H01L 029/94 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 29, 2003 |
KR |
03-67244 |
Claims
What is claimed is:
1. A field effect transistor comprising: a gate formed in a channel
region of an active region that is defined on a substrate; a source
formed at a first surface portion of the active region that is
positioned adjacent to a first side face of the gate; and a drain
formed at a second surface portion of the active region that is
positioned adjacent to a second side face of the gate opposite to
the first side face, the drain having a protruded portion that is
protruded from a surface portion of the substrate.
2. The transistor of claim 1, wherein the gate comprises: a
dielectric layer pattern formed on the channel region; and a
conductive layer pattern formed on the dielectric layer
pattern.
3. The transistor of claim 2, wherein the source comprises a
lightly doped source region and a heavily doped source region, the
lightly doped source region has a first depth from the surface of
the substrate, and the heavily doped source region has a second
depth less than the first depth from the surface of the
substrate.
4. The transistor of claim 3, wherein the lightly doped source
region comprises a portion positioned under the dielectric layer,
and the heavily doped source region comprises an exposed surface
and is surrounded by the lightly doped source region.
5. The transistor of claim 1, wherein the drain comprises a lightly
doped drain region having a third depth from the surface of the
substrate, the protruded portion being positioned on the lightly
doped drain region.
6. The transistor of claim 5, wherein a heavily doped drain region
is formed at a surface portion of the protruded portion.
7. A lateral double diffused metal-oxide-semiconductor (LDMOS)
transistor, comprising: a gate formed in a channel region of an
active region that is defined on a substrate; a source formed at a
first surface portion of the active region that is positioned
adjacent to a first side face of the gate; a drain formed at a
second surface portion of the active region that is positioned
adjacent to a second side face of the gate opposite to the first
side face, the drain having a protruded portion that is protruded
from a surface portion of the substrate; and a base contacting the
drain and surrounding the channel region and the source.
8. The transistor of claim 7, wherein the gate comprises: a
dielectric layer pattern formed on the channel region; and a
conductive layer pattern formed on the dielectric layer
pattern.
9. The transistor of claim 8, wherein the source comprises and a
heavily doped source region and a base contact electrically
connected to the heavily doped source region, and the base contact
is formed at a surface portion of the active region that is
positioned farther than the heavily doped source region with
respect to the gate.
10. The transistor of claim 9, wherein the base contact comprises a
conductivity type that is different from that of the heavily doped
source region.
11. The transistor of claim 10, wherein the source further
comprises a lightly doped source region having a portion that is
positioned under the dielectric layer, and surrounding the heavily
doped source region.
12. The transistor of claim 8, wherein the drain comprises a
lightly doped drain region, the protruded portion being positioned
on the lightly doped drain region.
13. The transistor of claim 12, wherein a heavily doped drain
region is formed at a surface portion of the protruded portion.
14. A method of manufacturing a field effect transistor comprising:
forming a source at a first surface portion of an active region
that is defined on a substrate; forming a drain at a second surface
portion of the active region that is opposite to the first surface
portion of the active region, the drain having a protruded portion
that is protruded from a surface portion of the substrate; and
forming a gate on a channel region between the source and the
drain.
15. A method of manufacturing a field effect transistor comprising:
forming an insulation layer on a substrate to define an active
region on the substrate; forming lightly doped source/drain regions
at surface portions of the active region, the lightly doped
source/drain regions being spaced apart from each other; forming a
gate on the active region between the lightly doped source/drain
regions, the gate having a width greater than the distance at which
the lightly doped source/drain regions are spaced apart; forming a
protruded portion doped with impurities at a high-concentration on
the lightly doped drain region between the gate and the insulating
layer; and forming a heavily doped source region at a surface
portion of the lightly doped source region and a heavily doped
drain region at a surface portion of the protruded portion.
16. The method of claim 15, wherein the lightly doped source/drain
regions are formed before forming the insulation layer.
17. The method of claim 15, wherein the lightly doped source/drain
regions are formed by an ion implantation process or ion
implantation/diffusion processes.
18. The method of claim 15, wherein forming the gate comprises:
forming a dielectric layer on the substrate at which the lightly
doped source/drain regions are formed; forming a conductive layer
on the dielectric layer; and patterning the conductive layer and
the dielectric layer to form the gate including a conductive layer
pattern and a dielectric layer pattern.
19. The method of claim 15, wherein forming the protruded portion
comprises: depositing oxide on the gate and the substrate to form a
blocking layer; partially etching the blocking layer to expose a
surface of the lightly doped drain region; and applying a material
substantially identical to that of the lightly doped drain region
onto the exposed surface of the lightly doped drain region to
epitaxially grow the material from the exposed surface of the
lightly doped drain region.
20. A method of manufacturing a lateral double diffused
metal-oxide-semiconductor (LDMOS) transistor comprising: forming a
base at a first surface portion of an active region that is defined
on a substrate; forming a source on the base; forming a drain at a
second surface portion of the active region that is opposite to the
first surface portion of the active region, the drain having a
protruded portion that is protruded from a surface portion of the
substrate; and forming a gate in a channel region between the
source and the drain.
21. A method of manufacturing a lateral double diffused
metal-oxide-semiconductor (LDMOS) transistor, comprising: forming a
base at a first surface portion of an active region that is defined
on a substrate; forming insulation layers at surface portions of
the base and the substrate, respectively; forming a lightly doped
drain region at a second surface portion of the active region;
forming a gate on the substrate adjacent to the lightly doped drain
region; forming a protruded portion doped with impurities at a
high-concentration on the lightly doped drain region; forming a
heavily doped source region at a surface portion of the lightly
doped source region and a heavily doped drain region at a surface
portion of the protruded portion; and forming a base contact doped
with impurities at a high-concentration between the gate and the
heavily doped source region.
22. The method of claim 21, wherein the lightly doped drain region
is formed simultaneously with the lightly doped source region.
23. The method of claim 21, wherein the lightly doped drain region
is formed before forming the insulation layer.
24. The method of claim 21, wherein the lightly doped source/drain
regions are formed by an ion implantation process or ion
implantation/diffusion processes.
25. The method of claim 21, wherein forming the gate comprises:
forming a dielectric layer on the substrate at which the lightly
doped drain region is formed; forming a conductive layer on the
dielectric layer; and patterning the conductive layer and the
dielectric layer to form the gate including a conductive layer
pattern and a dielectric layer pattern.
26. The method of claim 21, wherein forming the protruded portion
comprises: depositing oxide on the gate and the substrate to form a
blocking layer; partially etching the blocking layer to expose a
surface of the lightly doped drain region; and applying a material
substantially identical to that of the lightly doped drain region
onto the exposed surface of the lightly doped drain region to
epitaxially grow the material from the exposed surface of the
lightly doped drain region.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims priority under 35 USC .sctn. 119 to
Korean Patent Application No. 2003-67244, filed on Sep. 29, 2003,
the contents of which are herein incorporated by reference in its
entirety for all purposes.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a field effect transistor
and a method of manufacturing the transistor. More particularly,
the present invention relates to a field effect transistor having a
drain that is protruded from a substrate, and a method for forming
the transistor.
[0004] 2. Description of the Related Art
[0005] In general, semiconductor transistors may be categorized as
bipolar junction transistors (BJT) or field effect transistors
(FET).
[0006] The BJT has electrons and holes as charge carriers. The
electron and the hole carry charges in a single transistor. Thus,
regardless of whether the transistor is an NPN transistor or a PNP
transistor, the charge carrier in the BJT is the electron and the
hole.
[0007] On the contrary, the FET has only a single charge carrier.
The charge carrier is an electron in an N type FET and is a hole in
a P type FET. The FET can be a metal-oxide-semiconductor FET
(MOSFET) that is widely employed in semiconductor devices.
[0008] The MOSFET can be a complementary MOS (CMOS). The CMOS is
used in most digital logic circuits. The CMOS has a low operation
voltage. Accordingly, although a low voltage is applied to the
CMOS, the CMOS may be normally operated. However, when a high
voltage is applied to the CMOS, the CMOS may be abnormally
operated. As a result, since the CMOS has a low breakdown voltage,
the CMOS to which the high voltage is applied may malfunction.
[0009] Generally, a high-voltage transistor has a rectifying
function and a switching function. To evaluate the functions of the
high-voltage transistor, a breakdown voltage and a resistance in
the high-voltage transistor are considered as important
factors.
[0010] The operation voltage of the transistor is determined in
accordance with the breakdown voltage. A high breakdown voltage is
required for performing the rectifying and the switching functions
of the high-voltage transistor when a high voltage is applied to
the high-voltage transistor.
[0011] A breakdown generated in a semiconductor device is mainly an
avalanche breakdown. The avalanche breakdown is caused by an
electron-hole pair (EHP). The EHP is generated due to a collision
of the charge carrier that receives energy generated by a strong
electric field with a molecule for forming a crystalline structure
of the semiconductor device. The strong electric field is applied
to a depletion region. When the electron or the hole as the charge
carrier moves in the depletion region, the electric field applied
to the depletion region provides kinetic energy to the charge
carrier so that the charge carrier collides with the molecule,
thereby losing the kinetic energy. The EHP is then generated from
the molecule. This mechanism continuously occurs to generate the
avalanche breakdown in the semiconductor device. Thus, when the
breakdown is generated, a great amount of current flows through a
channel region of the transistor. As a result, the amount of the
current varies remarkably in accordance with a tiny increase of
voltage so that the semiconductor device may be uncontrollable.
[0012] Another breakdown is a Zener breakdown caused by tunneling.
The Zener breakdown is generated in a PN junction doped with
impurities at a high-concentration. A conduction band of an N type
semiconductor device and a valence band of a P type semiconductor
device overlap with each other, thereby generating the Zener
breakdown. When a concentration profile of the PN junction quickly
increases, the Zener breakdown is also generated. Accordingly, when
the semiconductor device is doped with impurities at a
high-concentration, Zener breakdown is generated before generating
the avalanche breakdown. To prevent the occurrence of the Zener
breakdown that is generated under a voltage that is relatively low
compared to that causing the avalanche breakdown, a region doped
with impurities at a low-concentration is required in source/drain
regions of the transistor.
[0013] In order that the transistor may function as a switch, the
channel has a low resistance when the transistor is turned-on, and
the channel has a high resistance when the transistor is
turned-off. In an ideal transistor, the resistance of the channel
is about zero when the transistor is turned-on, and is infinite
when the transistor is turned-off. However, in a real transistor,
the channel has a resistance in the turned-on or the turned-off
state. In particular, the non-infinite resistance of the transistor
in the turned-off state causes a leakage current of the transistor.
Further, a high resistance of the channel decreases a transmission
efficiency of a signal through the channel.
[0014] Accordingly, the transistor has a high breakdown voltage and
a low resistance to be operated at a high voltage. However, the
resistance and the breakdown voltage have a trade-off relation that
characteristics of the resistance are degraded when characteristics
of the breakdown voltage are improved, and vice versa.
[0015] Many transistors are suggested for improving the
characteristics of the resistance and the breakdown voltage.
[0016] A conventional transistor is formed so as to have a lightly
doped drain (LDD) structure. Source/drain regions doped with
impurities at a low-concentration are formed to surround
source/drain regions doped with impurities at a high-concentration,
respectively, to provide a high breakdown voltage to the
transistor. The source region doped with impurities at a
low-concentration is extended under a gate oxide layer. The drain
region doped with impurities at a low-concentration is extended
under a portion of the gate oxide layer that is disposed adjacent
to the drain region doped impurities at a high-concentration
impurity. A length of a channel region is shortened in the
structure described above, thereby reducing the resistance of the
transistor. Further, the source/drain regions doped with impurities
at a low-concentration, which intersect each other at both sides of
the gate oxide layer, prevent a hot-carrier injection generated in
the channel region adjacent to the drain region doped with
impurities at a high-concentration. Particularly, the source/drain
regions doped with impurities at a low-concentration increase a
width between the source/drain regions doped with impurities at a
high-concentration so that the transistor has a high breakdown
voltage.
[0017] Another conventional transistor has a lateral
double-diffused MOS (LDMOS). The LDMOS has improved resistance and
breakdown voltage characteristics. The LDMOS is also normally
operated by an input signal having a high frequency. Further, since
the LDMOS may be fabricated by processes for manufacturing standard
CMOS and by additional processes, the LDMOS is employed in
conventional process lines for manufacturing the standard CMOS. The
LDMOS has a very short channel length so that the transistor has
improved high frequency and resistance characteristics. To improve
the breakdown voltage characteristic, an interval between the
source region and the drain region that are doped with impurities
at a high-concentration is widened. Thus, the drain region is
needed to have a wide lightly doped region. A structural feature of
the LDMOS is that the transistor has a channel region separated
from a drift region, whereas other transistors have the channel and
drift regions into one combined region. The drift region for
maintaining the high voltage that is applied to the drain region is
doped with impurities at a low-concentration to a great extent. The
channel region through which the charge carrier passes has a very
short length for suppressing the occurrence of the EHP.
Additionally, the LDMOS has a base and a base contact for capturing
an electron or a hole that is generated by moving the charge
carrier.
[0018] The above-mentioned conventional transistors are required to
have the wide low-concentration impurity region so that the area
occupied by transistors in a semiconductor device is enlarged.
Numbers of semiconductor devices on a wafer, that is, a net die,
are reduced. Further, a photoresist pattern may be mis-aligned in
an ion implantation process for forming the source/drain regions so
that characteristics of a semiconductor device may be greatly
changed. As a result, guaranteeing a process margin may be
difficult.
SUMMARY OF THE INVENTION
[0019] The present invention provides a field effect transistor
having a high breakdown voltage.
[0020] The present invention also provides an LDMOS transistor
having a high breakdown voltage.
[0021] The present invention also provides a method of
manufacturing a field effect transistor that has a high breakdown
voltage.
[0022] The present invention also provides a method of
manufacturing an LDMOS transistor that has a high breakdown
voltage.
[0023] A field effect transistor in accordance with one aspect of
the present invention includes a gate that is formed in a channel
region of an active region defined on a substrate. A source is
formed at a first surface portion of the active region that is
adjacently disposed at a first side face of the gate. A drain is
formed at a second surface portion of the active region that is
positioned adjacent to a second side face of the gate opposite to
the first side face. That is, the second surface portion is
opposite to the first surface portion with respect to the gate. The
drain has a protruded portion that is protruded from a surface
portion of the substrate.
[0024] An LDMOS transistor in accordance with another aspect of the
present invention includes a gate that is formed on a channel
region of an active region defined on a substrate. A source is
formed at a first surface portion of the active region that is
positioned adjacent to a first side face of the gate. A drain is
formed at a second surface portion of the active region that is
positioned adjacent to a second side face of the gate opposite to
the first side face. That is, the second surface portion is
opposite to the first surface portion with respect to the gate. The
drain has a protruded portion that is protruded from a surface
portion of the substrate. A base makes contact with the drain and
surrounds the channel region and the source.
[0025] In a method of manufacturing a field effect transistor in
accordance with still another aspect of the present invention, a
source is formed at a first surface portion of an active region
that is defined on a substrate. A drain, having a protruded portion
that is protruded from a surface portion of the substrate, is
formed at a second surface portion of the active region that is
opposite to the first surface portion of the active region, i.e.,
opposite to the source. A gate is formed on a channel region
between the source and the drain.
[0026] In a method of manufacturing an LDMOS transistor in
accordance with still another aspect of the present invention, an
insulation layer is formed on a substrate to define an active
region on the substrate. Lightly doped source/drain regions are
formed at surface portions of the active region, the lightly doped
source/drain regions being spaced apart from each other. A gate is
formed on the active region between the lightly doped source/drain
regions, the gate having a width greater than the distance at which
the lightly doped source/drain regions are spaced apart. A
protruded portion doped with impurities at a high-concentration is
formed on the lightly doped drain region between the gate and the
insulating layer. A heavily doped source region is formed at a
surface portion of the lightly doped source region, and a heavily
doped drain region is formed at a surface portion of the protruded
portion.
[0027] In a method of manufacturing an LDMOS transistor in
accordance with still another aspect of the present invention, a
base is formed at a first surface portion of an active region that
is defined on a substrate. A source is formed on the base. A drain
having a protruded portion that is protruded from a surface portion
of the substrate is formed at a second surface portion of the
active region that is opposite to the first surface portion, i.e.,
opposite to the source. A gate is formed on a channel region
between the source and the drain.
[0028] In a method of manufacturing an LDMOS transistor in
accordance with still another aspect of the present invention, a
base is formed at a first surface portion of an active region that
is defined on a substrate. Insulation layers are formed at surface
portions of the base and the substrate, respectively. A lightly
doped drain region is formed at a surface portion of the active
region. A gate is formed on the substrate adjacent to the lightly
doped drain region. A protruded portion doped with impurities at a
high-concentration is formed on the lightly doped drain region. A
heavily doped source region is formed at a surface portion of the
lightly doped source region, and a heavily doped drain region is
formed at a surface portion of the protruded portion. A base
contact doped with impurities at a high-concentration is formed
between the gate and the heavily doped source region.
[0029] According to the present invention, the transistor has a
reduced area. Also, a breakdown voltage is controllable without
degrading a resistance characteristic. Further, an ion implantation
process for forming a drain doped with impurities at a
high-concentration is readily carried out.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The foregoing and other features and advantages of the
invention will be apparent from the more particular description of
an embodiment of the invention, as illustrated in the accompanying
drawing. The drawing is not necessarily to scale, emphasis instead
being placed upon illustrating the principles of the invention.
[0031] FIG. 1 is cross sectional view illustrating a field effect
transistor in accordance with a first embodiment of the present
invention.
[0032] FIGS. 2 to 7 are cross sectional views illustrating a method
of manufacturing the field effect transistor in FIG. 1.
[0033] FIG. 8 is a cross sectional view illustrating an LDMOS
transistor in accordance with a second embodiment of the present
invention.
[0034] FIGS. 9 to 14 are cross sectional views illustrating a
method of manufacturing the LDMOS transistor in FIG. 8.
DESCRIPTION OF THE INVENTION
[0035] Hereinafter, transistors and method for forming the
transistors in accordance with embodiments of the present invention
are illustrated in detail with reference to the accompanying
drawings.
[0036] Embodiment 1
[0037] FIG. 1 is cross sectional view illustrating a field effect
transistor in accordance with a first embodiment of the present
invention. In FIG. 1, wirings of a transistor are omitted.
[0038] Referring to FIG. 1, an insulation layer 102 for defining an
active region is positioned at a surface portion of a substrate
100. The insulation layer 102 may be formed by a local oxidation of
silicon (LOCOS) process or a trench isolation process. When the
insulation layer 102 is formed by the trench isolation process, an
electric field may be concentrated on a bottom corner of the
insulation layer 102 so that an insulation characteristic between
devices is degraded. Thus, the insulation layer 102 is preferably
formed by the LOCOS process.
[0039] A field effect transistor (FET) is positioned on the active
region that is defined by the insulating layer 102. A gate is
located at a central portion of the transistor. The gate includes a
dielectric layer pattern 108 and a conductive layer pattern 110.
The gate may include a spacer 112 to protect the dielectric layer
pattern 108 and the conductive layer pattern 110 in a subsequent
etching process or an ion implantation process.
[0040] A source is positioned between a first side face of the gate
and the insulation layer 102. The source includes a highly or
heavily doped source region 120 and a lightly doped source region
104. The lightly doped source region 104 extends from the
insulation layer 102 towards a lower portion of the dielectric
layer pattern 108. That is, the lightly doped source region 104 and
the dielectric layer pattern 108 are partially overlapped with each
other. The heavily doped source region 120 is formed in the lightly
doped source region 104 without being overlapped with the
dielectric layer pattern 108. The lightly doped source region 104
preferably surrounds the heavily doped source region 120.
Accordingly, the lightly doped source region 104 has a first depth
from the surface of the substrate 100. The heavily doped source
region 120 has a second depth less than the first depth from the
surface of the substrate 100.
[0041] A drain is positioned between a second side face of the gate
opposite to the first side face and the insulation layer 102.
Accordingly, the drain is disposed opposite to the source with
respect to the gate. The drain includes a lightly doped drain
region 106, a protruded portion 116 doped with impurities at a
high-concentration, and a heavily doped drain region 118 formed at
a surface portion of the protruded portion 116. The lightly doped
drain region 106 is formed at the surface portion of the substrate
100 that is disposed adjacent to the second side face of the gate.
The lightly doped drain region 106 is partially overlapped with the
dielectric layer pattern 108. The lightly doped drain region 106
has a third depth from the surface of the substrate 100. The
protruded portion 116 is positioned between a gate spacer formed on
the second face of the gate and the insulation layer 102. A height
of the protruded portion 116 may vary in accordance with an
operation voltage of the transistor. The height of the protruded
portion 116 may be higher than that of the gate. Alternatively, the
height of the protruded portion 116 may be substantially equal to
or no more than that of the gate. The heavily doped drain region
118 is positioned on the protruded portion 116. An area of the
transistor is remarkably reduced due to the lightly doped drain
region 106 and the protruded portion 116.
[0042] FIGS. 2 to 7 are cross sectional views illustrating a method
for forming the field effect transistor in FIG. 1.
[0043] Referring to FIG. 2, the insulation layer 102 is formed on
the substrate 100 by a LOCOS process or a trench process.
Preferably, the insulation layer 102 is formed by the LOCOS
process.
[0044] The insulation layer 102 may be formed by the following
method. A pad oxide layer (not shown) and a nitride layer (not
shown) are subsequently formed on the substrate 100. A photoresist
film (not shown) is formed on the nitride layer. The photoresist
film is patterned to form a photoresist pattern (not shown). The
nitride layer is etched using the photoresist pattern as an etching
mask to partially expose the pad oxide layer. The exposed pad oxide
layer is oxidized to transform into a partial oxide layer. The
nitride layer and the pad oxide layer are removed to obtain the
insulation layer 102 corresponding to the partial oxide layer. The
insulation layer 102 defines an active region on the substrate on
which the transistor is formed.
[0045] Referring to FIG. 3, a photoresist film (not shown) is
formed on the substrate 100 and the insulation layer 102. The
photoresist film is patterned to form a photoresist pattern (not
shown). Impurities are implanted into the surface portions of the
active region at a low concentration to form the lightly doped
source region 104 and the lightly doped drain region 106 that is
spaced apart from the lightly doped source region 104 by a
predetermined distance. A diffusion process may be further
performed after implanting the impurities. Alternatively, the
source/drain regions may be formed prior to formation of the
insulation layer 102.
[0046] Referring to FIG. 4, a gate is formed on the surface portion
of the substrate 100 between the lightly doped source region 104
and the lightly doped drain region 106. To form the gate, the
dielectric layer (not shown) including oxide is formed on the
substrate 100. The conductive layer (not shown) including
polysilicon is formed on the dielectric layer. A photoresist film
(not shown) is formed on the conductive layer. The photoresist film
is patterned to form a photoresist pattern (not shown). The
conductive layer and the dielectric layer are etched using the
photoresist pattern as an etching mask to form the gate including
the dielectric layer pattern 108 and the conductive layer pattern
110. The dielectric layer pattern 108 and the conductive layer
pattern 110 have a width greater than the distance between the
lightly doped source/drain regions 104 and 106. Thus, the
dielectric layer pattern 108 is overlapped with the lightly doped
source/drain regions 104 and 106. Additionally, the gate may
include a spacer 112 that is formed on a sidewall of the dielectric
layer pattern 108 and the conductive layer pattern 110. A nitride
layer (not shown) is formed on the gate and the substrate 100. The
nitride layer is etched-back to form the spacer 112.
[0047] Referring to FIG. 5, a blocking layer (not shown) including
oxide is formed on the gate and the substrate 100. A photoresist
film (not shown) is formed on the blocking layer. The photoresist
film is patterned to form a photoresist pattern (not shown)
exposing the lightly doped drain region 106. The blocking layer is
partially etched using the photoresist pattern as an etching mask
to form a blocking layer pattern 114 exposing the lightly doped
drain region 106 and the spacer 112. Here, in FIG. 5, the blocking
layer pattern 114 exposes the spacer 112 and the lightly doped
drain region 106. Alternatively, the blocking layer pattern 114 may
expose only the lightly doped drain region 106 or the lightly doped
drain region 106 and a portion of the insulation layer 102. Also,
the blocking layer pattern 114 may expose the spacer 112, the
lightly doped drain region 106 and a portion of the insulation
layer 102. Accordingly, a margin in a photolithography process for
forming the photoresist pattern is guaranteed.
[0048] Referring to FIG. 6, a gas including a material that is
substantially identical to that of the lightly doped drain region
106 is applied to the lightly doped drain region 106 to epitaxially
grow the protruded portion 116 from the lightly doped drain region
106. Here, the blocking layer pattern 114 prevents the epitaxial
growth of layers that are disposed under the blocking layer pattern
114. Accordingly, the protruded portion 116 is formed only on the
exposed lightly doped drain region 106. In FIG. 6, the protruded
portion 116 has a height less than that of the gate. Alternatively,
the protruded portion 116 may have a height substantially equal to
or no more than that of the gate in accordance with the operation
voltage of the transistor. The protruded portion 116 is doped with
impurities at a low-concentration. The protruded portion 116 also
has a conductivity type substantially identical to that of the
lightly doped source/drain regions 104 and 106.
[0049] Referring to FIG. 7, impurities are implanted into the
protruded portion 116 at a high concentration to form a heavily
doped drain region 118. The heavily doped drain region 118 is
formed at a surface portion of the protruded portion 116.
Simultaneously, the heavily doped source region 120 is formed
together with the heavily doped drain region 118 by implanting the
impurities at a high concentration. Since the protruded portion 116
is positioned on the lightly doped drain region 106 and the heavily
doped drain region 118 is positioned on the protruded portion 116,
an effective length between the heavily doped source region 120 and
the heavily doped drain region 118 is a sum of a horizontal length
from the heavily doped source region 120 to the lightly doped drain
region 106 and a vertical length from the lightly doped drain
region 106 to the heavily doped drain region 118. Accordingly, the
distance between the source and the drain is elongated so that the
transistor having a high breakdown voltage has a narrow area.
[0050] In accordance with the invention, the transistor may be an N
type transistor or a P type transistor. When the transistor is an N
type transistor, the source/drain regions are an N type. When the
transistor is a P type transistor, the source/drain regions are a P
type. Additionally, the transistor may include a well (not shown)
that includes the source, the drain and the gate and also is
distinguished from a bulk portion of the substrate.
[0051] Embodiment 2
[0052] FIG. 8 is cross sectional view illustrating an LDMOS
transistor in accordance with a second embodiment of the present
invention.
[0053] Referring to FIG. 8, an insulation layer 102 for defining an
active region is positioned at a surface portion of a substrate
100. The insulation layer 102 may be formed by a local oxidation of
silicon (LOCOS) process or a trench isolation process. When the
insulation layer 102 is formed by the trench isolation process, an
electric field may be concentrated on a bottom corner of the
insulation layer 102 so that an insulation characteristic between
devices is degraded. Thus, the insulation layer 102 is preferably
formed by the LOCOS process.
[0054] A field effect transistor (FET) is positioned on the active
region that is defined by the insulating layer 102. A gate is
located at a central portion of the transistor. The gate includes a
dielectric layer pattern 108 and a conductive layer pattern 110.
The gate may include a spacer 112 to protect the dielectric layer
pattern 108 and the conductive layer pattern 110 in a subsequent
etching process or an ion implantation process.
[0055] A source is positioned between a first side face of the gate
and the insulation layer 102. The source includes a heavily doped
source region 120; a lightly doped source region 104 and a base
contact 122. The lightly doped source region 104 extends from the
insulation layer 102 towards a lower portion of the dielectric
layer pattern 108. Thus, the lightly doped source region 104 and
the dielectric layer pattern 108 are partially overlapped with each
other. The heavily doped source region 120 is formed in the lightly
doped source region 104 without being overlapped with the
dielectric layer pattern 108. The lightly doped source region 104
preferably surrounds the heavily doped source region 120.
Accordingly, the lightly doped source region 104 has a first depth
from the surface of the substrate 100. The heavily doped source
region 120 has a second depth less than the first depth from the
surface of the substrate 100. The base contact 122 makes contact
with the lightly doped source region 104. The base contact 122 is
also electrically isolated from the low-concentration and heavily
doped source regions 120. The base contact 122 has a conductivity
type opposite to that of the low-concentration and heavily doped
source regions 104 and 120. When the low-concentration and heavily
doped source regions 104 and 120 are N type, the base contact 122
is P type, and vice versa.
[0056] A base 101 is positioned under a channel region beneath the
gate and the source. The base 101 has a conductivity type
substantially identical to that of the base contact 122.
[0057] A drain is positioned between a second side face of the gate
opposite to the first side face and the insulation layer 102.
Accordingly, the drain is disposed opposite to the source with
respect to the gate. The drain includes a lightly doped drain
region 106, a protruded portion 116 doped with impurities at a
high-concentration, and a heavily doped drain region 118 formed at
a surface portion of the protruded portion 116. The lightly doped
drain region 106 is formed at the surface portion of the substrate
100 that is disposed adjacent to the second side face of the gate.
The lightly doped drain region 106 is partially overlapped with the
dielectric layer pattern 108. The lightly doped drain region 106
has a third depth from the surface of the substrate 100. The
protruded portion 116 is positioned between a gate spacer formed on
the second face of the gate and the insulation layer 102. A height
of the protruded portion 116 may vary in accordance with an
operation voltage of the transistor. The height of the protruded
portion 116 may be higher than that of the gate. Alternatively, the
height of the protruded portion 116 may be substantially equal to
or no more than that of the gate. The heavily doped drain region
118 is positioned on the protruded portion 116. An area of the
transistor is remarkably reduced due to the lightly doped drain
region 106 and the protruded portion 116.
[0058] Additionally, the transistor may include a well (not shown)
that includes the base 101 and the lightly doped drain region 106.
The well has a conductivity type opposite to that of the base 101
and substantially identical to that of the lightly doped drain
region 106.
[0059] FIGS. 9 to 14 are cross sectional views illustrating a
method for forming the LDMOS transistor in FIG. 8.
[0060] Referring to FIG. 9, the base 101 is formed at a surface
portion of the substrate 100 by an ion implantation process or ion
implantation/diffusion processes. In particular, a photoresist film
(not shown) is formed on the substrate 100. The photoresist film is
patterned to form a photoresist pattern (not shown). Impurities are
implanted into the substrate using the photoresist pattern as an
ion implanting mask to form the base 101. Additionally, the
impurities in the base 101 may be diffused for controlling a depth
and a width of the base 101.
[0061] Referring to FIG. 10, the insulation layer 102 is formed at
surface portions of the base 101 and the substrate 100 by a LOCOS
process or a trench isolation process. Preferably, the insulation
layer 102 is formed by the LOCOS process.
[0062] The insulation layer 102 may be formed by a following
method. A pad oxide layer (not shown) and a nitride layer (not
shown) are subsequently formed on the substrate 100. A photoresist
film (not shown) is formed on the nitride layer. The photoresist
film is patterned to form a photoresist pattern (not shown). The
nitride layer is etched using the photoresist pattern as an etching
mask to partially expose the pad oxide layer. The exposed pad oxide
layer is oxidized to become a partial oxide layer. The nitride
layer and the pad oxide layer are removed to obtain the insulation
layer 102 corresponding to the partial oxide layer. The insulation
layer 102 defines an active region on the substrate on which the
transistor is formed.
[0063] Referring to FIG. 11, a photoresist film (not shown) is
formed on the substrate 100 and the insulation layer 102. The
photoresist film is patterned to form a photoresist pattern (not
shown). Impurities are implanted into the surface portions of the
active region at a low concentration to form the lightly doped
source region 104 and the lightly doped drain region 106 that is
spaced apart from the lightly doped source region 104 by a
predetermined distance. A diffusion process may be further
performed after implanting the impurities. Alternatively, the
source/drain regions may be formed before forming the insulation
layer 102.
[0064] Referring to FIG. 12, a gate is formed on the surface
portion of the substrate 100 between the lightly doped source
region 104 and the lightly doped drain region 106. To form the
gate, the dielectric layer (not shown) including oxide is formed on
the substrate 100. The conductive layer (not shown) including
polysilicon is formed on the dielectric layer. A photoresist film
(not shown) is formed on the conductive layer. The photoresist film
is patterned to form a photoresist pattern (not shown). The
conductive layer and the dielectric layer are etched using the
photoresist pattern as an etching mask to form the gate including
the dielectric layer pattern 108 and the conductive layer pattern
110. The dielectric layer pattern 108 and the conductive layer
pattern 110 have a width greater than the distance between the
lightly doped source/drain regions 104 and 106. Thus, the
dielectric layer pattern 108 is overlapped with the lightly doped
source/drain regions 104 and 106. Additionally, the gate may
include a spacer 112 that is formed on a sidewall of the dielectric
layer pattern 108 and the conductive layer pattern 110. A nitride
layer (not shown) is formed on the gate and the substrate 100. The
nitride layer is etched-back to form the spacer 112.
[0065] Referring to FIG. 13, a blocking layer (not shown) including
oxide is formed on the gate and the substrate 100. A photoresist
film (not shown) is formed on the blocking layer. The photoresist
film is patterned to form a photoresist pattern (not shown)
exposing the lightly doped drain region 106. The blocking layer is
partially etched using the photoresist pattern as an etching mask
to form a blocking layer pattern 114 exposing the lightly doped
drain region 106 and the spacer 112. Here, in FIG. 13, the blocking
layer pattern 114 exposes the spacer 112 and the lightly doped
drain region 106. Alternatively, the blocking layer pattern 114 may
expose only the lightly doped drain region 106 or the lightly doped
drain region 106 and a portion of the insulation layer 102. Also,
the blocking layer pattern 114 may expose the spacer 112, the
lightly doped drain region 106 and the portion of the insulation
layer 102. Accordingly, a margin in a photolithography process for
forming the photoresist pattern is guaranteed.
[0066] Referring to FIG. 14, a gas including a material that is
substantially identical to that of the lightly doped drain region
106 is applied to the lightly doped drain region 106 to epitaxially
grow the protruded portion 116 from the lightly doped drain region
106. Here, the blocking layer pattern 114 prevents the epitaxial
growth of layers that are disposed under the blocking layer pattern
114. Accordingly, the protruded portion 116 is formed only on the
exposed lightly doped drain region 106. In FIG. 14, the protruded
portion 116 has a height less than that of the gate. Alternatively,
the protruded portion 116 may have a height substantially equal to
or no more than that of the gate in accordance with the operation
voltage of the transistor. The protruded portion 116 is doped with
impurities at a low-concentration. Also, the protruded portion 116
has a conductivity type substantially identical to that of the
lightly doped source/drain regions 104 and 106.
[0067] High-concentration impurities are implanted into the
protruded portion 116 to form a heavily doped drain region 118. The
heavily doped drain region 118 is formed at a surface portion of
the protruded portion 116. Simultaneously, the heavily doped source
region 120 is formed together with the heavily doped drain region
118 by implanting the high-concentration impurities. Since the
protruded portion 116 is positioned on the lightly doped drain
region 106 and the heavily doped drain region 118 is positioned on
the protruded portion 116, an effective length between the heavily
doped source region 120 and the heavily doped drain region 118 is a
sum of a horizontal length from the heavily doped source region 120
to the lightly doped drain region 106 and a vertical length from
the lightly doped drain region 106 to the heavily doped drain
region 118. Accordingly, the distance between the source and the
drain is elongated so that the transistor having a high breakdown
voltage has a narrow area.
[0068] A base contact 122 doped with impurities at a
high-concentration is formed between the lightly doped source
region 104 and the insulation layer 102. The base contact 122 has a
conductivity type opposite to that of the lightly doped source
region 104 and the heavily doped source region 120. Accordingly,
when the lightly doped source region 104 and the heavily doped
source region 120 are an N type, the base contact 122 is a P type
substantially identical to that of the base 101. The base contact
122 is formed by an ion implantation process. The base contact 122
also makes contact with the lightly doped source region 104. Thus,
the base contact 122 is electrically isolated from the heavily
doped source region 120, respectively. Alternatively, the base
contact 122 may be formed before forming the heavily doped source
region 120 and the heavily doped drain region 118. The base contact
122 captures minority carriers among the EHPs that are generated
from the base 101 defining the channel region.
[0069] An effective length of the LDMOS transistor is the distance
between the lightly doped source region 104 and the lightly doped
drain region 106 so that the resistance of the LDMOS transistor is
reduced. Further, the effective length extends by the protruded
portion 116 so that the breakdown voltage increases.
[0070] In particular, the protruded portion 116 is positioned on
the lightly doped drain region 106, and the heavily doped drain
region 118 is positioned on the protruded portion 116. Accordingly,
the effective length between the heavily doped source region 120
and the heavily doped drain region 118 is the sum of a horizontal
length from the heavily doped source region 120 to the lightly
doped drain region 106 and a vertical length from the lightly doped
drain region 106 to the heavily doped drain region 118.
Accordingly, the distance between the source and the drain is
elongated so that the transistor having a high breakdown voltage
has a narrow area
[0071] The transistor may be an N type transistor or a P type
transistor in the present embodiment. When the transistor is the N
type transistor, the source/drain regions are N type, and the base
and the base contact are P type. When the transistor is the P type
transistor, the source/drain regions are P type, and the base and
the base contact are N type. Additionally, the transistor may
include a well (not shown) that includes the source, the drain, the
gate, and the base, and is also distinguished from a bulk portion
of the substrate. The well has a conductivity type substantially
identical to that of the drain regions though concentrations of the
well and the drain regions are different from each other.
[0072] According to the present invention, the FET and the LDMOS
transistors having a small area are manufactured without degrading
characteristics of the resistance and the breakdown voltage.
Further, a sufficient process margin in forming the heavily doped
drain region is guaranteed. The drift region in the heavily doped
drain region that is maintained in a high voltage is readily
controlled. As a result, the transistors are readily manufactured
in accordance with the operation voltage of the transistors.
[0073] While this invention has been particularly shown and
described with reference to preferred embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made therein without departing from the
spirit and scope of the invention as defined by the appended
claims.
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