U.S. patent application number 10/925986 was filed with the patent office on 2005-03-03 for thin-film field effect transistor and making method.
Invention is credited to Fukui, Ikuo.
Application Number | 20050045876 10/925986 |
Document ID | / |
Family ID | 34101211 |
Filed Date | 2005-03-03 |
United States Patent
Application |
20050045876 |
Kind Code |
A1 |
Fukui, Ikuo |
March 3, 2005 |
Thin-film field effect transistor and making method
Abstract
In a thin-film field effect transistor with a MIS structure, the
materials of which the semiconductor and insulating layers are made
are polymers which are dissolvable in organic solvents and have a
weight average molecular weight of more than 2,000 to 1,000,000.
Use of polymers for both the semiconductor layer and insulating
layer of TFT eliminates such treatments as patterning and etching
using photoresists in the prior art circuit-forming technology,
reduces the probability of TFT defects and achieves a reduction of
TFT manufacture cost.
Inventors: |
Fukui, Ikuo; (Niigata-ken,
JP) |
Correspondence
Address: |
BIRCH STEWART KOLASCH & BIRCH
PO BOX 747
FALLS CHURCH
VA
22040-0747
US
|
Family ID: |
34101211 |
Appl. No.: |
10/925986 |
Filed: |
August 26, 2004 |
Current U.S.
Class: |
257/40 |
Current CPC
Class: |
H01L 51/0007 20130101;
H01L 51/0036 20130101; H01L 51/0558 20130101; H01L 51/052
20130101 |
Class at
Publication: |
257/040 |
International
Class: |
H01L 035/24 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 28, 2003 |
JP |
2003-304019 |
Claims
1. A thin-film field effect transistor with a
metal-insulator-semiconducto- r structure, wherein the materials of
which the semiconductor and insulating layers are made are polymers
which are dissolvable in organic solvents and have a weight average
molecular weight of more than 2,000 to 1,000,000.
2. The thin-film field effect transistor of claim 1, wherein the
polymer of which the insulating layer is made is an insulating
polymer having cyano groups.
3. The thin-film field effect transistor of claim 1, wherein the
material of which the semiconductor layer is made is a
polythiophene.
4. A method for fabricating a thin-film field effect transistor,
comprising the steps of: applying a solution of a polymer having a
weight average molecular weight of more than 2,000 to 1,000,000 in
a first organic solvent to a gate electrode in the form of a metal
layer, drying the applied polymer solution to form an insulating
layer on the metal layer, and forming on the insulating layer a
semiconductor layer which is dissolvable in a second organic
solvent in which the insulating layer is not dissolvable.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This Nonprovisional application claims priority under 35
U.S.C. .sctn.119(a) on Patent Application No. 2003-304019 filed in
Japan on Aug. 28, 2003, the entire contents of which are hereby
incorporated by reference.
TECHNICAL FIELD
[0002] This invention relates to thin-film field effect transistors
(TFTs) utilizing silicon semiconductors or compound semiconductors,
especially for use in liquid crystal displays, and a method of
fabricating the same.
BACKGROUND ART
[0003] TFTs utilizing silicon semiconductors or compound
semiconductors are used in common integrated circuits and in
wide-spreading other applications. In particular, the use of TFTs
in liquid crystal displays is well known. Nowadays LC displays are
making continuous progress toward larger size and more precise
definition. The requirement to incorporate a greater number of TFTs
corresponding to the number of pixels becomes stronger than
ever.
[0004] However, ordinary metal based semiconductors used in the art
cannot avoid the problem that slight defective pixels are caused by
the defects of TFTs formed on the substrate as a result of
treatments including patterning and etching using photoresists
during circuitry formation on the substrate. Such treatments impose
a certain limit in reducing the cost of TFT manufacture. This is
also true for other flat displays such as plasma displays and
organic EL displays when TFTs are used therein.
[0005] The recent trend toward larger size and more precise
definition tends to increase the probability of defection in the
TFT manufacture. It is thus strongly desired to minimize such TFT
defects.
[0006] For TFTs with a metal-insulator-semiconductor (MIS)
structure, attempts have been made to use organic materials as the
insulator and semiconductor. For example, JP-A 5-508745 (WO 9201313
or U.S. Pat. No. 5,347,144) describes that a device using an
insulating organic polymer having a dielectric constant of at least
5 as the insulating layer and a polyconjugated organic compound
having a weight average molecular weight of up to 2,000 as the
semiconductor layer exerts a field effect and has a mobility of
carriers of about 10.sup.-2 cm.sup.2V.sup.-1s.sup.-1. Since the
semiconductor layer is formed by evaporating .alpha.-sexithienyl as
an organic semiconductor material, treatments including patterning
and etching using photoresists are necessary, failing to achieve a
cost reduction.
SUMMARY OF THE INVENTION
[0007] An object of the present invention is to provide thin-film
field effect transistors (TFTs) having a higher carrier mobility
than prior art TFTs and minimized defects, and a method of
fabricating the same.
[0008] The inventor has discovered that in a TFT with a
metal-insulator-semiconductor (MIS) structure, a simple approach of
using organic solvent-soluble polymers as the materials of which
the semiconductor and insulating layers are made is successful in
achieving a greater carrier mobility than in the prior art.
[0009] Accordingly, the present invention provides a thin-film
field effect transistor with an MIS structure, wherein the
materials of which the semiconductor and insulating layers are made
are polymers which are dissolvable in organic solvents and have a
weight average molecular weight of more than 2,000 to
1,000,000.
[0010] In another embodiment of the invention, a thin-film field
effect transistor is fabricated by a process involving the steps of
dissolving polymers having a weight average molecular weight (Mw)
of more than 2,000 to 1,000,000 in organic solvents, applying the
resulting polymer solutions, and drying the applied polymer
solutions, thereby forming a semiconductor layer and an insulating
layer.
[0011] According to the invention, use of polymers for both the
semiconductor layer and insulating layer of TFT eliminates such
treatments as patterning and etching using photoresists or the like
in the circuit forming technology using prior art metal based
semiconductors and insulators, reduces the probability of TFT
defects and achieves a reduction of TFT manufacture cost.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a perspective view of TFT in one embodiment of the
invention.
[0013] FIG. 2 is a graph of drain current versus drain voltage of
TFT in an example of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0014] Referring to FIG. 1, a TFT in one embodiment of the
invention is illustrated as comprising a substrate 1 of SiO.sub.2
or the like, a metal layer 2 formed on the substrate 1 and serving
as a gate electrode, an insulating layer 3 formed on the metal
layer 2, a semiconductor layer 4 formed on the insulating layer 3,
and source and drain electrodes 5 and 6 formed on the semiconductor
layer 4.
[0015] The metal layer 2 used herein may be a commonly used ITO
(indium tin oxide) film, or a film of a single metal such as Au, Cu
or Al or a laminate metal film of Au/Ti, Cu/Ti or Al/Ti, deposited
by the physical vapor deposition (PVD) or metal organic chemical
vapor deposition (MOCVD) method. Since the objects of the invention
favor that the metal layer 2 be formed by printing, it is
recommended to use electroconductive metal pastes if no practical
problems are encountered.
[0016] In the inventive TFT, the material of which the insulating
layer is made is a polymer or high-molecular weight compound which
is dissolvable in an organic solvent and has a weight average
molecular weight (Mw) of more than 2,000 to 1,000,000, and
preferably an insulating polymer having cyano groups. Examples
include cyanoethyl pullulan, cyanoethyl cellulose, cyanoethyl
polyvinyl alcohol, and polyacrylonitrile. These insulating polymers
having cyano groups are readily obtainable. For example, cyanoethyl
pullulan is obtained by reacting a pullulan resin with
acrylonitrile in the presence of an alkali catalyst (see JP-B
59-31521). The degree of substitution of cyano groups (e.g., degree
of substitution of cyanoethyl groups in the case of cyanoethyl
pullulan) is desirably at least 80 mol %, more desirably at least
85 mol %. This is because the concentration of polar groups or
cyano groups must be above a certain level in order to produce a
TFT having a fully improved mobility, and a more content of
residual hydroxyl groups leads to an increase in dielectric loss as
a loss factor and is sometimes undesirable for the objects of the
invention.
[0017] In the inventive TFT, the material of which the
semiconductor layer is made is a polymer or high-molecular weight
compound which is dissolvable in an organic solvent and has a
weight average molecular weight (Mw) of more than 2,000 to
1,000,000. Although no other limits are imposed on the polymer for
the semiconductor layer, the polymer should be dissolvable in an
organic solvent in which the insulating layer is not dissolvable.
This is because it is generally believed that in forming the
semiconductor layer and the insulating layer in a lay-up manner,
the interfacial state does not become uniform.
[0018] Past studies on organic TFT employed a method of forming an
organic semiconductor layer on an organic insulating film by
evaporation as described in JP-A 5-508745, and a method of forming
only an organic semiconductor layer on an inorganic insulating
layer. One exemplary method involves dissolving both an organic
semiconductor material and an organic insulating material in an
identical organic solvent to form solutions, coating and drying the
organic insulating material solution to form an organic insulating
layer, then applying the organic semiconductor material solution to
the organic insulating layer. At this point, the organic insulating
material is slightly dissolved at the coating interface. Eventually
the interface between layers of the obtained laminated film after
drying is disordered. By contrast, the present invention solves the
problem by using different organic solvents for dissolution of a
semiconductor material and an insulating material, that is, by
combining two organic solvents with two materials such that one of
the materials is not dissolvable in one of the organic
solvents.
[0019] Specifically, suitable polymers for forming the
semiconductor layer include polythiophenes, polypyrroles,
polyanilines, polyacetylenes, polythienylene vinylenes, and
polyphenylene vinylenes. Of these, polythiophenes such as
poly(3-hexylthiophene) are preferred because of solubility in
organic solvents, good processability, stability and a high carrier
mobility.
[0020] Suitable organic solvents for dissolving the polymers of
which the insulating layer is made include N-methyl-2-pyrrolidone,
dimethylformamide, acetone, acetonitrile, .gamma.-butyrolactone,
etc. Suitable organic solvents for dissolving the polymers of which
the semiconductor layer is made include chloroform, toluene,
hexane, alcohols, etc. In either case, the solvent may be used
alone or in admixture of two or more.
[0021] According to the invention, a thin-film field effect
transistor is fabricated by applying a solution of a polymer having
a Mw of more than 2,000 to 1,000,000 in a first organic solvent to
a gate electrode in the form of a metal layer, drying the applied
polymer solution to form an insulating layer on the metal layer,
and forming on the insulating layer a semiconductor layer which is
dissolvable in a second organic solvent in which the insulating
layer is not dissolvable. This method may be implemented using
well-known techniques. For example, a metal layer serving as a gate
electrode is formed by a sputtering technique on the substrate
which is selected from glass and ordinary polymer sheets.
Alternatively, a metal layer is formed by applying a metal paste or
electroconductive polymer to the substrate by a spin coating,
screen printing or ink jet printing technique, followed by drying.
Commercially available ITO glass may also be used.
[0022] An insulating layer is then formed on the thus formed gate
electrode, by applying a solution of the insulating layer-forming
material in a first organic solvent by a spin coating, screen
printing or ink jet printing technique, followed by drying. In this
case, the insulating layer may preferably have a thickness of 0.2
to 10 .mu.m, more preferably 0.5 to 3 .mu.m. Too thin insulating
layer may cause a large leakage current. Too thick insulating layer
may require a large driving voltage.
[0023] Next, a semiconductor layer is formed on the insulating
layer by applying a solution of the semiconductor layer-forming
material in a second organic solvent in which the insulating
polymer is not dissolvable, by a spin coating, screen printing or
ink jet printing technique, followed by drying. The surface of the
insulating layer may be previously subjected to physical treatment,
typically known rubbing treatment in order that semiconductor
molecules be aligned at the interface between insulating and
semiconductor layers.
[0024] Finally, source and drain electrodes are formed on the
semiconductor layer by a sputtering technique. Alternatively, a
metal paste or electroconductive polymer is applied by a screen
printing or ink jet printing technique, followed by drying.
[0025] The inventive TFT has a structure including an insulating
layer formed on a gate electrode in the form of a metal layer and a
semiconductor layer formed on the insulating layer. When an
electric potential is applied to the gate to produce an electric
field, electric charges are created within the semiconductor in
proximity to the insulating layer due to a field effect, thereby
forming a conductive region, called the channel, within the
semiconductor layer between source and drain electrodes formed on
the semiconductor layer. This means that the interfacial state
between insulating and semiconductor layers is crucial. The flatter
interface, the better performs the device.
EXAMPLE
[0026] Examples of the invention are given below by way of
illustration and not by way of limitation.
Example 1
[0027] There were furnished cyanoethyl pullulan having a
substitution of cyanoethyl of 85.2 mol % (CyEPL, Shin-Etsu Chemical
Co., Ltd., CR-S, Mw=49,000) as an insulating layer material and
poly(3-hexylthiophene) (P3HT, Aldrich, Mw=87,000) as an organic
semiconductor layer material. The organic solvent in which P3HT was
dissolved was chloroform, in which CyEPL was insoluble. A TFT was
fabricated using these materials and evaluated as follows.
[0028] On a glass (SiO.sub.2) substrate, a gate electrode was
formed by depositing Ti to a thickness of 5 nm and then Au to a
thickness of 20 nm, using an RF sputtering technique at room
temperature and a back pressure of 10.sup.-4 Pa.
[0029] An insulating layer was then formed on the gate electrode by
dissolving 15 wt % CyEPL as the insulating layer material in
N-methyl-2-pyrrolidone, passing the solution through a 0.2-micron
membrane filter, spin coating the solution, and drying at
100.degree. C. for one hour.
[0030] A semiconductor layer of 50 nm thick was then formed on the
insulating layer by dissolving 0.8 wt % P3HT in chloroform, passing
the solution through a 0.2-micron membrane filter, spin coating the
solution, and drying at 100.degree. C. for one hour.
[0031] The substrate was cooled at -20.degree. C. Au was deposited
to a thickness of 300 nm on the organic semiconductor layer through
a metal mask, using an RF sputtering technique at a back pressure
below 10.sup.-5 Pa. There were formed two gold electrodes of 4 mm
wide spaced a distance of 50 .mu.m (see FIG. 1, L=50 .mu.m and W=4
mm) serving as source and drain electrodes.
Comparative Example 1
[0032] There were furnished cyanoethyl pullulan having a
substitution of cyanoethyl of 85.2 mol % (CyEPL, Shin-Etsu Chemical
Co., Ltd., CR-S) as an insulating layer material and copper
phthalocyanine (CuPc) as an organic semiconductor layer material. A
TFT was fabricated using these materials and evaluated as
follows.
[0033] On a glass (SiO.sub.2) substrate, a gate electrode was
formed by depositing Ti to a thickness of 5 nm and then Au to a
thickness of 20 nm, using an RF sputtering technique at room
temperature and a back pressure of 10.sup.-4 Pa.
[0034] An insulating layer was then formed on the gate electrode by
dissolving 15 wt % CyEPL as the insulating layer material in
N-methyl-2-pyrrolidone, passing the solution through a 0.2-micron
membrane filter, spin coating the solution, and drying at
100.degree. C. for one hour.
[0035] A semiconductor layer of 50 nm thick was then formed on the
insulating layer by depositing CuPc, using an RF sputtering
technique at room temperature and a back pressure of 10.sup.-5
Pa.
[0036] The substrate was cooled at -20.degree. C. Au was deposited
to a thickness of 300 nm on the organic semiconductor layer through
a metal mask, using an RF sputtering technique at a back pressure
below 10.sup.-5 Pa. There were formed two gold electrodes of 4 mm
wide spaced a distance of 50 .mu.m serving as source and drain
electrodes.
Comparative Example 2
[0037] There were furnished SiO.sub.2 as an insulating layer
material and copper phthalocyanine (CuPc) as an organic
semiconductor layer material. A TFT was fabricated using these
materials and evaluated as follows.
[0038] A p-type doped silicon substrate was annealed in a furnace
to form an oxide film (SiO.sub.2) of 300 nm thick as an insulating
film. Then only the back surface of the substrate which had not
been mirror finished was treated with hydrofluoric acid to remove
the oxide film. On only the back surface thus treated, a gate
electrode was formed by depositing Ti to a thickness of 5 nm and
then Au to a thickness of 20 nm, using an RF sputtering technique
at room temperature and a back pressure of 10.sup.-4 Pa.
[0039] A semiconductor layer of 50 nm thick was then formed on the
surface of the oxide film serving as the insulating layer, by
depositing CuPc, using an RF sputtering technique at room
temperature and a back pressure below 10.sup.-5 Pa.
[0040] The substrate was cooled at -20.degree. C. Au was deposited
to a thickness of 300 nm on the organic semiconductor layer through
a metal mask, using an RF sputtering technique at a back pressure
below 10.sup.-5 Pa. There were formed two gold electrodes of 4 mm
wide spaced a distance of 50 .mu.m serving as source and drain
electrodes.
[0041] [TFT Evaluation]
[0042] Each of the devices thus fabricated was placed in a vacuum
prober where the substrate was heated at 50.degree. C. and allowed
to stand in a vacuum (below 10.sup.-4 Torr) for one hour. In the
prober under vacuum, light-shielded conditions, the TFT
characteristics were determined by a semiconductor parameter
analyzer SCS4200 by Keithley.
[0043] The results are shown in Table 1.
[0044] Drain current versus voltage (I.sub.SD-V.sub.SD) curves
representing the field effect of TFT of Example 1 are shown in the
graph of FIG. 2.
1 TABLE 1 Insulating Semiconduct layer or layer Mobility Threshold
material material (cm.sup.2V.sup.-1s.sup.-1) (V0) Example 1 CyEPL
P3HT 4.0 .times. 10.sup.-1 -9.0 Comparative CyEPL CuPc 2.0 .times.
10.sup.-3 -7.0 Example 1 Comparative SiO.sub.2 CuPc 2.0 .times.
10.sup.-4 -0.13 Example 2
[0045] The results of Comparative Examples 1 and 2 suggest that use
of CyEPL as the organic insulating layer material provides a
greater mobility than conventional SiO.sub.2. Although the TFT of
Example 1 was fabricated by the method which is generally believed
to achieve no improvement in mobility due to disordered interface,
that is, in which both the organic insulating layer and the organic
semiconductor layer are formed by coating and drying, the TFT of
Example 1 exhibits a significantly high mobility. The inventive TFT
has an improved mobility because the channel formation would be
enhanced by polar groups aligned at the interface between
insulating and semiconductor layers, when a potential is applied to
the gate.
[0046] Japanese Patent Application No. 2003-304019 is incorporated
herein by reference.
[0047] Although some preferred embodiments have been described,
many modifications and variations may be made thereto in light of
the above teachings. It is therefore to be understood that the
invention may be practiced otherwise than as specifically described
without departing from the scope of the appended claims.
* * * * *