U.S. patent application number 10/949142 was filed with the patent office on 2005-02-24 for method for eliminating reaction between photoresist and osg.
Invention is credited to Daniels, Brian J., Dunne, Jude A., Kennedy, Joseph T..
Application Number | 20050042860 10/949142 |
Document ID | / |
Family ID | 25010517 |
Filed Date | 2005-02-24 |
United States Patent
Application |
20050042860 |
Kind Code |
A1 |
Daniels, Brian J. ; et
al. |
February 24, 2005 |
Method for eliminating reaction between photoresist and OSG
Abstract
A method of forming a microelectronic device while preventing
photoresist poisoning. Various layers of conductive metals and
dielectric materials are deposited onto a substrate in selective
sequence to form an integrated circuit. Vias and trenches are
formed throughout the structure by exposing and patterning a
photoresist material. The dielectric materials of the insulating
layers are protected from the photoresist to prevent chemical
reactions which lead to photoresist poisoning. This is done by
forming a modified surface layer on the dielectric material by
either depositing an additional layer that covers the dielectric
material, or by modifying the exposed surface of the dielectric
material to a plasma or chemical treatment.
Inventors: |
Daniels, Brian J.; (La
Honda, CA) ; Dunne, Jude A.; (Menlo Park, CA)
; Kennedy, Joseph T.; (San Jose, CA) |
Correspondence
Address: |
Roberts & Roberts, LLP
Attorneys at Law
P.O. Box 484
Princeton
NJ
08542-0484
US
|
Family ID: |
25010517 |
Appl. No.: |
10/949142 |
Filed: |
September 24, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10949142 |
Sep 24, 2004 |
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10243528 |
Sep 13, 2002 |
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6818552 |
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10243528 |
Sep 13, 2002 |
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09748692 |
Dec 26, 2000 |
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6583047 |
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Current U.S.
Class: |
438/637 ;
257/E21.579; 257/E23.167 |
Current CPC
Class: |
H01L 23/53238 20130101;
H01L 23/53295 20130101; H01L 21/76843 20130101; H01L 21/76813
20130101; H01L 21/76825 20130101; H01L 21/76835 20130101; H01L
21/76831 20130101; H01L 21/76807 20130101; H01L 2221/1063 20130101;
H01L 23/5329 20130101; H01L 2924/0002 20130101; H01L 21/76811
20130101; H01L 21/76808 20130101; H01L 21/76828 20130101; H01L
21/76826 20130101; H01L 21/76829 20130101; H01L 2924/0002 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
438/637 |
International
Class: |
H01L 021/4763 |
Claims
1. (Canceled)
2. The process of claim 18 wherein the first dielectric layer
comprises an organic dielectric material and the second dielectric
layer comprises an inorganic dielectric material.
3. The process of claim 18 wherein the first dielectric layer
comprises an inorganic dielectric material and the second
dielectric layer comprises an organic dielectric material.
4. The process of claim 18 wherein the first dielectric layer
comprises an inorganic dielectric material and the second
dielectric layer comprises an inorganic dielectric material.
5. The process of claim 18 wherein the first dielectric layer
comprises an organic dielectric material and the second dielectric
layer comprises an organic dielectric material.
6. The process of claim 18 wherein the etch stop layer is
present.
7. The process of claim 6 wherein the etch stop layer comprises
silicon nitride, silicon oxynitride, silicon dioxide, silicon
carbide, silicon oxycarbide, spin on glass, organic polymers,
hydrogen silsesquioxane, methyl silsesquioxane or combinations
thereof.
8. The process of claim 18 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
9. The process of claim 18 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have substantially the same etch resistance
properties.
10. (Canceled)
11. The process of claim 18 wherein the barrier metal comprises Ti,
Ta, or a nitride.
12. The process of claim 18 wherein the fill metal comprises
aluminum, aluminum alloys, copper, copper alloys, tantalum,
tungsten, titanium, nitrides thereof or combinations thereof.
13-17. (Canceled).
18. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer
or the optional etch stop layer; ) (d) depositing a layer of a
photoresist on a top surface of the second dielectric layer and
imagewise removing a portion of the photoresist corresponding to at
least one via for the first dielectric layer; (e) removing the
portions of each layer which are under the removed portions of the
photoresist thus forming at least one via through the second
dielectric layer, optional etch stop and first dielectric layer,
and removing the balance of the photoresist layer; (f) depositing a
barrier material on a top surface of the second dielectric layer,
and a surface of inside walls and a floor of the via through the
second dielectric layer, optional etch stop and first dielectric
layer thus forming a barrier material layer thereon; (g) depositing
an additional layer of a photoresist on the barrier material layer
on the top surface of the second dielectric layer and on the walls
and a floor of the via through the second dielectric layer,
optional etch stop layer, and first dielectric layer, and imagewise
removing a portion of the photoresist corresponding to at least one
trench for the second dielectric layer; (h) removing the portions
of the barrier material layer on the top surface of the second
dielectric layer, the second dielectric layer, and the barrier
material layers on the walls of the via within the second
dielectric layer which are under the removed portion of the
additional photoresist layer thus forming at least one trench down
through the second dielectric layer, and removing the balance of
the additional photoresist layer; (i) lining a barrier metal on
inside walls and a floor of the trench, and on the inside walls and
floor of the via; and (j) filling the trench and via with a fill
metal in contact with the barrier metal lining.
19. The process of claim 18 wherein the barrier layer material
comprises CVD oxide, CVD nitride, CVD oxynitride, CVD SiC, spin on
glass, organic polymers, chromophore laden spin on glass, hydrogen
silsesquioxane, methyl silsesquioxane, metals and combinations
thereof.
20. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer
or the optional etch stop layer; (d) depositing a layer of a
photoresist on a top surface of the second dielectric layer and
imagewise removing a portion of the photoresist corresponding to at
least one via for the second dielectric layer and the optional etch
stop layer; (e) removing the portions of the second dielectric
layer and the optional etch stop layer which are under the removed
portions of the photoresist thus forming at least one via down
through the second dielectric layer and the optional etch stop
layer, and removing the balance of the photoresist layer; (f)
depositing a barrier material on a top surface of the second
dielectric layer, and a surface of inside walls and a floor of the
via through the second dielectric layer and optional etch stop
layer thus forming a barrier material layer thereon; (g) depositing
an additional layer of a photoresist on the barrier material layer
on the top surface of the second dielectric layer and on the walls
and a floor of the via through the second dielectric layer and the
optional etch stop layer, and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer; (h) removing the portions of the barrier material
layer on the top surface of the second dielectric layer, the second
dielectric layer, and the barrier material layers on the walls of
the via within the second dielectric layer which are under the
removed portion of the additional photoresist layer thus forming at
least one trench down through the second dielectric layer, and
removing the portions of the barrier material layer from the floor
of the via which was in the second dielectric layer, and portions
of the first dielectric layer under the via which was in the second
dielectric layer thus forming at least one via down through the
first dielectric layer; (i) removing the balance of the additional
photoresist layer; (j) lining a barrier metal on inside walls and a
floor of the trench, and on the inside walls and floor of the via;
and (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
21. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer
or the optional etch stop layer; (d) depositing a layer of a
photoresist on a top surface of the second dielectric layer and
imagewise removing a portion of the photoresist corresponding to at
least one trench for the second dielectric layer; (e) removing the
portions of the second dielectric layer which are under the removed
portions of the photoresist thus forming at least one trench
through the second dielectric layer, and removing the balance of
the photoresist layer; (f) modifying a top surface of the second
dielectric layer, and a surface of inside walls and a floor of the
trench thus forming a protective material thereon; (g) depositing
an additional layer of a photoresist on the protective material on
the top surface of the second dielectric layer, and the protective
material on the walls and floor of the trench, and imagewise
removing a portion of the photoresist corresponding to at least one
via for the first dielectric layer; (h) removing the portions of
each layer which are under the removed portion of the additional
photoresist layer thus forming at least one via down through the
first dielectric layer, and removing the balance of the additional
photoresist layer; (i) lining a barrier metal on inside walls and a
floor of the trench, and on inside walls and a floor of the via;
and (j) filling the trench and via with a fill metal in contact
with the barrier metal lining.
22. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer
or the optional etch stop layer; (d) depositing a layer of a
photoresist on a top surface of the second dielectric layer and
imagewise removing a portion of the photoresist corresponding to at
least one trench for the second dielectric layer; (e) removing the
portions of the second dielectric layer and optionally removing the
etch stop layer, if present, which are under the removed portions
of the photoresist thus forming at least one trench through the
second dielectric layer and optionally through the etch stop layer,
and removing the balance of the photoresist layer; (f) depositing a
barrier material on a top surface of the second dielectric layer,
and a surface of inside walls and a floor of the trench thus
forming a barrier material layer thereon; (g) depositing an
additional layer of a photoresist on the barrier material layer on
the top surface of the second dielectric layer and the inside walls
and floor of the trench, and imagewise removing a portion of the
photoresist corresponding to at least one via for the first
dielectric layer; (h) removing the portions of each of the barrier
material layer on the floor of the trench, any remaining portions
of the etch stop layer, and portions of the first dielectric layer
which are under the removed portion of the additional photoresist
layer, thus forming at least one via down through the barrier
material layer on the floor of the trench, the optional etch stop
layer, and the first dielectric layer, and removing the balance of
the additional photoresist layer; (i) lining a barrier metal on the
barrier material layer on the inside walls and floor of the trench,
and on inside walls and a floor of the via; and (j) filling the
trench and via with a fill metal in contact with the barrier metal
lining.
23. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer
or the optional etch stop layer; (d) forming a first hardmask layer
on the second dielectric layer; (e) forming a second hardmask layer
on the first hardmask layer; (f) depositing a layer of a
photoresist on a top surface of the second hardmask layer and
imagewise removing a portion of the photoresist corresponding to at
least one via for the second hardmask layer; (g) removing the
portions of the second hardmask layer which are under the removed
portions of the photoresist thus forming at least one via through
the second hardmask layer, and removing the balance of the
photoresist layer; (h) depositing an additional layer of a
photoresist on the top surface of the second hardmask layer and on
inside walls and floor of the via in the second hardmask, and
imagewise removing a portion of the photoresist corresponding to at
least one trench for the second hardmask layer; (i) removing the
portions of the first hardmask layer and the second dielectric
layer which are under the via in the second hardmask layer thus
forming at least one via down through the first hardmask layer and
the second dielectric layer; (j) removing the portions of the
second hardmask layer which are under the removed portions of the
additional photoresist thus forming at least one trench down
through the second hardmask layer, and removing the portions of the
optional etch stop layer which are under the via in the second
dielectric layer thus extending the via down through the optional
etch stop layer; (k) removing the portions of the first hardmask
layer and the second dielectric layer which are under the trench in
the second hardmask layer thus forming at least one trench down
through the first hardmask layer and the second dielectric layer;
removing the portions of the first dielectric layer under the via
which was in the second dielectric layer thus forming a via through
the first dielectric layer, and removing the balance of the
additional photoresist layer; (l) lining a barrier metal on inside
walls and a floor of the trench, and on inside walls and a floor of
the via; and (m) filling the trench and via with a fill metal in
contact with the barrier metal lining.
24. The process of claim 23 wherein the first hardmask layer and
the second hardmask layer comprise dissimilar materials selected
from the group consisting of SiO.sub.2, Si.sub.3N.sub.4, SiOC, SiC,
SiN, SiON, spin on glass, chromophore laden spin on glass, organic
spin on polymers, hydrogen silsesquioxane, methyl silsesquioxane,
metals and combinations thereof.
25. A process for producing a microelectronic device which
comprises: (a) forming a first dielectric layer on a substrate; (b)
forming an optional etch stop layer on the first dielectric layer;
(c) forming an second dielectric layer on the first dielectric
layer or the optional etch stop layer; (d) forming a first hardmask
layer on the second dielectric layer; (e) forming a second hardmask
layer on the first hardmask layer; (f) depositing a layer of a
photoresist on a top surface of the second hardmask layer and
imagewise removing a portion of the photoresist corresponding to at
least one trench for the second hardmask layer; (g) removing the
portions of the second hardmask layer which are under the removed
portions of the photoresist thus forming at least one trench
through the second hardmask layer, and removing the balance of the
photoresist layer; (h) depositing an additional layer of a
photoresist on the top surface of the second hardmask layer and on
inside walls and floor of the trench, and imagewise removing a
portion of the photoresist corresponding to at least one via for
the second dielectric layer and the optional etch stop layer; (i)
removing the portions of the first hardmask layer, the second
dielectric layer, and the optional etchstop layer which are under
the removed portion of the additional photoresist layer thus
forming at least one via down through the second dielectric layer
and optional etch stop layer, and removing the balance of the
additional photoresist layer; (j) removing the portions of the
first hardmask layer and the second dielectric layer which are
under the trench in the second hardmask layer thus forming at least
one trench down through the second dielectric layer and removing
the portions of the first dielectric layer corresponding to the via
in the second dielectric layer or optional etch stop layer, thus
forming at least one via down through the first dielectric layer;
(k) lining a barrier metal on inside walls and a floor of the
trench, and on inside walls and a floor of the via; and (l) filling
the trench and via with a fill metal in contact with the barrier
metal lining.
26. The process of claim 25 wherein the first hardmask layer and
the second hardmask layer comprise dissimilar materials selected
from the group consisting of SiO.sub.2, Si.sub.3N.sub.4, SiOC, SiC,
SiN, SiON, spin on glass, chromophore laden spin on glass, organic
spin on polymers, hydrogen silsesquioxane, methyl silsesquioxane,
metals and combinations thereof.
27. The process of claim 20 wherein the etch stop layer is
present.
28. The process of claim 20 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
29. The process of claim 21 wherein the etch stop layer is
present.
30. The process of claim 21 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
31. The process of claim 22 wherein the etch stop layer is
present.
32. The process of claim 22 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
33. The process of claim 23 wherein the etch stop layer is
present.
34. The process of claim 23 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
35. The process of claim 25 wherein the etch stop layer is
present.
36. The process of claim 25 wherein the optional etch stop layer is
not present and wherein the first dielectric layer and the second
dielectric layer have significantly different etch resistance
properties.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to the formation of structures
in microelectronic devices such as integrated circuit devices. More
particularly, the invention relates to the prevention of
photoresist poisoning during the formation of microelectronic
devices.
[0003] 2. Description of the Related Art
[0004] In the fabrication of microelectronic devices, it is known
in the art to deposit various metal layers and insulation layers
onto a substrate in selective sequence to form an integrated
circuit (IC). As used herein, the term "microelectronic device"
includes integrated circuits, intermetal dielectrics, and the like.
Typically, a first level metal layer is deposited on a substrate,
and is separated from a second level metal layer by one or more
insulation layers. Subsequent metal layers may, in turn, be
separated by one or more further insulation layers.
[0005] Insulation layers, which typically include dielectric
materials such as silicon dioxide, silicon oxynitride, fluorinated
silicate glass (FSG), spin-on glass (SOG) and the like, serve as
electrical insulation between intermetal dielectric layers. These
insulation layers are typically deposited by conventional
techniques such as chemical vapor deposition (CVD) and the like,
and serve as protective layers or gap fillers to achieve
planarization of the substrate. The metal layers typically comprise
conductive metals such as aluminum, copper, titanium, tantalum,
tungsten and the like.
[0006] During the formation of these microelectronic devices, it is
necessary to remove portions of the dielectric using standard
photolithography and etching techniques. Trenches, vias, and the
like are formed within the dielectric and are filled with
conductive metals to form electrical connections with metal
contacts in the integrated circuit. Upon such processing, the
dielectric can come in contact with other materials, including but
not limited to photoresist and antireflective coatings (ARC's).
[0007] One problem that arises from this contact between materials
is that a reaction between the photoresist and certain dielectrics
may occur. This is particularly important for a class of dielectric
materials referred to as organosilicate glasses (OSGs), which
includes trade name materials such as HOSP.TM., Black Diamond.TM.
and Coral.TM.. These materials can be either porous or non-porous.
These materials are extremely attractive in the industry as their
dielectric constant is much lower than that of silicon dioxide. The
reaction that occurs between the OSG and the photoresist/ARC
creates a reaction product in vias which is difficult to remove by
etching, ashing, and/or chemical stripping. As a result, the
subsequent patterning of the interconnect structure is no longer
defined by the photoresist and photoresist rework may become
difficult or impossible. This phenomenon is known as "photoresist
poisoning", "resist poisoning", "nailheading", and/or
"mushrooming". Upon development, photoresist poisoning causes the
exposed pattern areas of the photoresist layer to have a
photoresist profile or structure with non-uniform side walls. Where
a positive photoresist is used, photoresist poisoning often leads
to the formation of a photoresist footing, or a widening of the
photoresist line just above the substrate. Where a negative
photoresist is used, photoresist pinching may result, which is a
formation of non-uniform side walls of the photoresist profile on
the underlying substrate after photolithographic exposure and
development. After etching, such photoresist footing or photoresist
pinching problem will lead to an imperfect transfer of the
photoresist pattern to the underlying layer or layers. For some
preferred methods of interconnect fabrication, in particular the
dual Damascene process, this OSG/photoresist reaction can make
interconnection formation difficult or impossible.
[0008] It would be desirable to devise a method of forming
integrated circuits which avoids poisoning of the photoresist layer
during resist formation. The subject of this invention is that the
deposition or creation of an intermediate layer between the
dielectric material and the photoresist inhibits the reaction which
causes photoresist poisoning.
[0009] According to the present invention, the dielectric materials
of the insulating layers are protected from the photoresist
material to prevent chemical reactions which lead to photoresist
poisoning. This is done by forming a modified surface layer on the
dielectric material by either depositing an additional layer that
covers the dielectric material, or by modifying the exposed surface
of the dielectric material to a plasma or chemical treatment.
SUMMARY OF THE INVENTION
[0010] The present invention provides a process for producing a
microelectronic device which comprises:
[0011] (a) forming a first dielectric layer on a substrate;
[0012] (b) forming an optional etch stop layer on the first
dielectric layer;
[0013] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0014] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the first
dielectric layer;
[0015] (e) removing the portions of each layer which are under the
removed portions of the photoresist thus forming at least one via
down through the first dielectric layer, and removing the balance
of the photoresist layer;
[0016] (f) depositing a protective material on the top surface of
the second dielectric layer and on inside walls and a floor of the
via;
[0017] (g) depositing an additional layer of a photoresist on the
protective material and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer;
[0018] (h) removing the portions of each layer which are under the
removed portion of the additional photoresist layer thus forming at
least one trench down through the second dielectric layer;
[0019] (i) removing the balance of the additional photoresist layer
and the balance of the protective material;
[0020] (j) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0021] (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0022] The present invention also provides a process for producing
a microelectronic device which comprises:
[0023] (a) forming a first dielectric layer on a substrate;
[0024] (b) forming an optional etch stop layer on the first
dielectric layer;
[0025] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0026] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the second
dielectric layer;
[0027] (e) removing the portions of the second dielectric layer and
the optional etch stop layer which are under the removed portions
of the photoresist thus forming at least one via down through the
second dielectric layer and the optional etch stop layer, and
removing the balance of the photoresist layer;
[0028] (f) depositing a protective material on a top surface of the
second dielectric layer and on inside walls and a floor of the
via;
[0029] (g) depositing an additional layer of a photoresist on the
protective material and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer;
[0030] (h) removing the portions of the protective material and the
second dielectric layer which are under the removed portion of the
additional photoresist layer thus forming at least one trench down
through the second dielectric layer, and removing the portions of
the first dielectric layer which are under the via which was in the
second dielectric layer thus forming a via down through the first
dielectric layer;
[0031] (i) removing the balance of the additional photoresist layer
and the balance of the protective material;
[0032] (j) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0033] (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0034] The present invention further provides a process for
producing a microelectronic device which comprises:
[0035] (a) forming a first dielectric layer on a substrate;
[0036] (b) forming an optional etch stop layer on the first
dielectric layer;
[0037] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0038] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer;
[0039] (e) removing the portions of the second dielectric layer
which are under the removed portions of the photoresist thus
forming at least one trench down through the second dielectric
layer, and removing the balance of the photoresist layer;
[0040] (f) depositing a protective material on a top surface of the
second dielectric layer and on inside walls and a floor of the
trench;
[0041] (g) depositing an additional layer of a photoresist on the
protective material and imagewise removing a portion of the
photoresist corresponding to at least one via for the first
dielectric layer;
[0042] (h) removing the portions of each layer which are under the
removed portion of the additional photoresist layer thus forming at
least one via down through the protective material, the optional
etch stop layer, and the first dielectric layer;
[0043] (i) removing the balance of the additional photoresist layer
and the balance of the protective material;
[0044] (j) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0045] (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0046] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0047] (a) forming a first dielectric layer on a substrate;
[0048] (b) forming an optional etch stop layer on the first
dielectric layer;
[0049] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0050] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the first
dielectric layer;
[0051] (e) removing the portions of each layer which are under the
removed portions of the photoresist thus forming at least one via
through the second dielectric layer, the optional etch stop layer,
and first dielectric layer, and removing the balance of the
photoresist layer;
[0052] (f) modifying the top surface of the second dielectric
layer, and a surface of inside walls of the via through the second
dielectric layer, optional etch stop layer, and first dielectric
layer thus forming a protective material thereon;
[0053] (g) depositing an additional layer of a photoresist on the
protective material on the top surface of the second dielectric
layer and on the protective material on the walls and a floor of
the via through the second dielectric layer, optional etch stop
layer, and first dielectric layer, and imagewise removing a portion
of the photoresist corresponding to at least one trench for the
second dielectric layer;
[0054] (h) removing the portions of the protective material on the
top surface of the second dielectric layer, the second dielectric
layer, and the walls of the via within the second dielectric layer,
which are under the removed portion of the additional photoresist
layer thus forming at least one trench down through the second
dielectric layer, and removing the balance of the additional
photoresist layer;
[0055] (i) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0056] (j) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0057] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0058] (a) forming a first dielectric layer on a substrate;
[0059] (b) forming an optional etch stop layer on the first
dielectric layer;
[0060] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0061] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the second
dielectric layer and the optional etch stop layer;
[0062] (e) removing the portions of the second dielectric layer and
the optional etch stop layer which are under the removed portions
of the photoresist thus forming at least one via down through the
second dielectric layer and the optional etch stop layer, and
removing the balance of the photoresist layer;
[0063] (f) modifying a top surface of the second dielectric layer,
and a surface of inside walls of and a floor of the via through the
second dielectric layer and optional etch stop layer thus forming a
protective material thereon;
[0064] (g) depositing an additional layer of a photoresist on the
protective material on the top surface of the second dielectric
layer and on the protective material on the walls and floor of the
via through the second dielectric layer and the optional etch stop
layer, and imagewise removing a portion of the photoresist
corresponding to at least one trench for the second dielectric
layer;
[0065] (h) removing the portions of the protective material on the
top surface of the second dielectric layer, the second dielectric
layer, and the protective material on the walls of the via within
the second dielectric layer which are under the removed portion of
the additional photoresist layer thus forming at least one trench
down through the second dielectric layer, and removing the portions
of the protective material on the floor of the via which was in the
second dielectric layer, and portions of the first dielectric layer
under the via which was in the second dielectric layer thus forming
at least one via down through the first dielectric layer;
[0066] (i) removing the balance of the additional photoresist
layer;
[0067] (j) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0068] (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0069] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0070] (a) forming a first dielectric layer on a substrate;
[0071] (b) forming an optional etch stop layer on the first
dielectric layer;
[0072] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0073] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the first
dielectric layer;
[0074] (e) removing the portions of each layer which are under the
removed portions of the photoresist thus forming at least one via
through the second dielectric layer, optional etch stop and first
dielectric layer, and removing the balance of the photoresist
layer;
[0075] (f) depositing a barrier material on a top surface of the
second dielectric layer, and a surface of inside walls and a floor
of the via through the second dielectric layer, optional etch stop
and first dielectric layer thus forming a barrier material layer
thereon;
[0076] (g) depositing an additional layer of a photoresist on the
barrier material layer on the top surface of the second dielectric
layer and on the walls and a floor of the via through the second
dielectric layer, optional etch stop layer, and first dielectric
layer, and imagewise removing a portion of the photoresist
corresponding to at least one trench for the second dielectric
layer;
[0077] (h) removing the portions of the barrier material layer on
the top surface of the second dielectric layer, the second
dielectric layer, and the barrier material layers on the walls of
the via within the second dielectric layer which are under the
removed portion of the additional photoresist layer thus forming at
least one trench down through the second dielectric layer, and
removing the balance of the additional photoresist layer;
[0078] (i) lining a barrier metal on inside walls and a floor of
the trench, and on the inside walls and floor of the via; and
[0079] (j) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0080] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0081] (a) forming a first dielectric layer on a substrate;
[0082] (b) forming an optional etch stop layer on the first
dielectric layer;
[0083] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0084] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the second
dielectric layer and the optional etch stop layer;
[0085] (e) removing the portions of the second dielectric layer and
the optional etch stop layer which are under the removed portions
of the photoresist thus forming at least one via down through the
second dielectric layer and the optional etch stop layer, and
removing the balance of the photoresist layer;
[0086] (f) depositing a barrier material on a top surface of the
second dielectric layer, and a surface of inside walls and a floor
of the via through the second dielectric layer and optional etch
stop layer thus forming a barrier material layer thereon;
[0087] (g) depositing an additional layer of a photoresist on the
barrier material layer on the top surface of the second dielectric
layer and on the walls and a floor of the via through the second
dielectric layer and the optional etch stop layer, and imagewise
removing a portion of the photoresist corresponding to at least one
trench for the second dielectric layer;
[0088] (h) removing the portions of the barrier material layer on
the top surface of the second dielectric layer, the second
dielectric layer, and the barrier material layers on the walls of
the via within the second dielectric layer which are under the
removed portion of the additional photoresist layer thus forming at
least one trench down through the second dielectric layer, and
removing the portions of the barrier material layer from the floor
of the via which was in the second dielectric layer, and portions
of the first dielectric layer under the via which was in the second
dielectric layer thus forming at least one via down through the
first dielectric layer;
[0089] (i) removing the balance of the additional photoresist
layer;
[0090] (j) lining a barrier metal on inside walls and a floor of
the trench, and on the inside walls and floor of the via; and
[0091] (k) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0092] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0093] (a) forming a first dielectric layer on a substrate;
[0094] (b) forming an optional etch stop layer on the first
dielectric layer;
[0095] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0096] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer;
[0097] (e) removing the portions of the second dielectric layer
which are under the removed portions of the photoresist thus
forming at least one trench through the second dielectric layer,
and removing the balance of the photoresist layer;
[0098] (f) modifying a top surface of the second dielectric layer,
and a surface of inside walls and a floor of the trench thus
forming a protective material thereon;
[0099] (g) depositing an additional layer of a photoresist on the
protective material on the top surface of the second dielectric
layer, and the protective material on the walls and floor of the
trench, and imagewise removing a portion of the photoresist
corresponding to at least one via for the first dielectric
layer;
[0100] (h) removing the portions of each layer which are under the
removed portion of the additional photoresist layer thus forming at
least one via down through the first dielectric layer, and removing
the balance of the additional photoresist layer;
[0101] (i) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0102] (j) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0103] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0104] (a) forming a first dielectric layer on a substrate;
[0105] (b) forming an optional etch stop layer on the first
dielectric layer;
[0106] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0107] (d) depositing a layer of a photoresist on a top surface of
the second dielectric layer and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
dielectric layer;
[0108] (e) removing the portions of the second dielectric layer and
optionally removing the etch stop layer, if present, which are
under the removed portions of the photoresist thus forming at least
one trench through the second dielectric layer and optionally
through the etch stop layer, and removing the balance of the
photoresist layer;
[0109] (f) depositing a barrier material on a top surface of the
second dielectric layer, and a surface of inside walls and a floor
of the trench thus forming a barrier material layer thereon;
[0110] (g) depositing an additional layer of a photoresist on the
barrier material layer on the top surface of the second dielectric
layer and the inside walls and floor of the trench, and imagewise
removing a portion of the photoresist corresponding to at least one
via for the first dielectric layer;
[0111] (h) removing the portions of each of the barrier material
layer on the floor of the trench, any remaining portions of the
etch stop layer, and portions of the first dielectric layer which
are under the removed portion of the additional photoresist layer,
thus forming at least one via down through the barrier material
layer on the floor of the trench, the optional etch stop layer, and
the first dielectric layer, and removing the balance of the
additional photoresist layer;
[0112] (i) lining a barrier metal on the barrier material layer on
the inside walls and floor of the trench, and on inside walls and a
floor of the via; and
[0113] (j) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0114] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0115] (a) forming a first dielectric layer on a substrate;
[0116] (b) forming an optional etch stop layer on the first
dielectric layer;
[0117] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0118] (d) forming a first hardmask layer on the second dielectric
layer;
[0119] (e) forming a second hardmask layer on the first hardmask
layer;
[0120] (f) depositing a layer of a photoresist on a top surface of
the second hardmask layer and imagewise removing a portion of the
photoresist corresponding to at least one via for the second
hardmask layer;
[0121] (g) removing the portions of the second hardmask layer which
are under the removed portions of the photoresist thus forming at
least one via through the second hardmask layer, and removing the
balance of the photoresist layer;
[0122] (h) depositing an additional layer of a photoresist on the
top surface of the second hardmask layer and on inside walls and
floor of the via in the second hardmask, and imagewise removing a
portion of the photoresist corresponding to at least one trench for
the second hardmask layer;
[0123] (i) removing the portions of the first hardmask layer and
the second dielectric layer which are under the via in the second
hardmask layer thus forming at least one via down through the first
hardmask layer and the second dielectric layer;
[0124] (j) removing the portions of the second hardmask layer which
are under the removed portions of the additional photoresist thus
forming at least one trench down through the second hardmask layer,
and removing the portions of the optional etch stop layer which are
under the via in the second dielectric layer thus extending the via
down through the optional etch stop layer;
[0125] (k) removing the portions of the first hardmask layer and
the second dielectric layer which are under the trench in the
second hardmask layer thus forming at least one trench down through
the first hardmask layer and the second dielectric layer; removing
the portions of the first dielectric layer under the via which was
in the second dielectric layer thus forming a via through the first
dielectric layer, and removing the balance of the additional
photoresist layer;
[0126] (l) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0127] (m) filling the trench and via with a fill metal in contact
with the barrier metal lining.
[0128] The present invention still further provides a process for
producing a microelectronic device which comprises:
[0129] (a) forming a first dielectric layer on a substrate;
[0130] (b) forming an optional etch stop layer on the first
dielectric layer;
[0131] (c) forming a second dielectric layer on the first
dielectric layer or the optional etch stop layer;
[0132] (d) forming a first hardmask layer on the second dielectric
layer;
[0133] (e) forming a second hardmask layer on the first hardmask
layer;
[0134] (f) depositing a layer of a photoresist on a top surface of
the second hardmask layer and imagewise removing a portion of the
photoresist corresponding to at least one trench for the second
hardmask layer;
[0135] (g) removing the portions of the second hardmask layer which
are under the removed portions of the photoresist thus forming at
least one trench through the second hardmask layer, and removing
the balance of the photoresist layer;
[0136] (h) depositing an additional layer of a photoresist on the
top surface of the second hardmask layer and on inside walls and
floor of the trench, and imagewise removing a portion of the
photoresist corresponding to at least one via for the second
dielectric layer and the optional etch stop layer;
[0137] (i) removing the portions of the first hardmask layer, the
second dielectric layer, and the optional etch stop layer which are
under the removed portion of the additional photoresist layer thus
forming at least one via down through the second dielectric layer
and optional etch stop layer, and removing the balance of the
additional photoresist layer;
[0138] (j) removing the portions of the first hardmask layer and
the second dielectric layer which are under the trench in the
second hardmask layer thus forming at least one trench down through
the second dielectric layer and removing the portions of the first
dielectric layer corresponding to the via in the second dielectric
layer or optional etch stop layer, thus forming at least one via
down through the first dielectric layer;
[0139] (k) lining a barrier metal on inside walls and a floor of
the trench, and on inside walls and a floor of the via; and
[0140] (l) filling the trench and via with a fill metal in contact
with the barrier metal lining.
BRIEF DESCRIPTION OF THE DRAWINGS
[0141] FIGS. 1(a)-(h) show a first embodiment of the present
invention, showing a deep, via first technique together with a
deposited protective material.
[0142] FIGS. 2(a)-(h) show a second embodiment of the present
invention, showing a shallow, via first technique together with a
deposited protective material.
[0143] FIGS. 3(a)-(h) show a third embodiment of the present
invention, showing a trench first technique together with a
deposited protective material.
[0144] FIGS. 4(a)-(h) show a fourth embodiment of the present
invention, showing a deep, via first technique together with the
formation of a surface-modified protective material.
[0145] FIGS. 5(a)-(h) show a fifth embodiment of the present
invention, showing a shallow, via first technique together with the
formation of a surface-modified protective material.
[0146] FIGS. 6(a)-(h) show a sixth embodiment of the present
invention, showing a deep, via first technique together with a
barrier material layer.
[0147] FIGS. 7(a)-(h) show a seventh embodiment of the present
invention, showing a shallow, via first technique together with a
barrier material layer.
[0148] FIGS. 8(a)-(h) show an eighth embodiment of the present
invention, showing a trench first technique together with the
formation of a surface-modified protective material.
[0149] FIGS. 9(a)-(h) show a ninth embodiment of the present
invention, showing a trench first technique together with a barrier
material layer.
[0150] FIGS. 10(a)-(h) show a tenth embodiment of the present
invention, showing a via first technique together with first and
second hardmask layers.
[0151] FIGS. 11(a)-(h) show an eleventh embodiment of the present
invention, showing a trench first technique together with first and
second hardmask layers.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0152] In a first embodiment of the present invention, as shown in
FIG. 1(a), a first dielectric material is deposited onto a surface
of a substrate to form a first dielectric layer on the substrate.
An optional etch stop material may then be deposited onto the first
dielectric layer to form an optional etch stop layer. A second
dielectric material is then deposited onto the first dielectric
layer or the optional etch stop layer to thereby form a second
dielectric layer. A layer of a photoresist material is then
deposited onto a top surface of the second dielectric layer, and a
portion of the photoresist is imagewise removed by standard
photolithographic techniques to outline a via for the first
dielectric layer. Portions of each layer under the removed portions
of the photoresist are then removed to form at least one via down
through the first dielectric layer, as shown in FIG. 1(b). The
balance of the photoresist layer is then removed, as in FIG. 1(c).
A protective material, in this case a sacrificial film (SAC) is
deposited onto a top surface of the second dielectric layer and on
inside walls and a floor of the via, as shown in FIG. 1(d). An
additional layer of a photoresist is then deposited on the
protective material, and then a portion of the additional
photoresist is imagewise removed to outline at least one trench for
the second dielectric layer, as shown in FIG. 1(e). Portions are
removed from the protective material and the second dielectric
material under the removed portions of the additional photoresist,
to form at least one trench down through the second dielectric
layer, as shown in FIG. 1(f). The balance of the additional
photoresist layer is then removed, and the balance of the
protective material is removed, as shown in FIG. 1(g). Inside walls
and a floor of the via and the trench are then lined with a barrier
metal, and then the trench and via are filled with a fill metal in
contact with the barrier metal lining, as shown in FIG. 1(h).
[0153] Suitable substrates useful for the techniques described
above include those suitable to be processed into an integrated
circuit or other microelectronic device. Substrates non-exclusively
include semiconductor materials such as gallium arsenide (GaAs),
germanium, silicon, silicon germanium, lithium niobate and
compositions containing silicon such as crystalline silicon,
polysilicon, amorphous silicon, epitaxial silicon, and silicon
dioxide (SiO.sub.2) and mixtures thereof and may include metal
contact lines which are typically formed by well known lithographic
techniques. Suitable materials for the metal contacts include
aluminum, aluminum alloys, copper, copper alloys, titanium,
tantalum, and tungsten. These lines form the conductors of an
integrated circuit. Such are typically closely separated from one
another at distances preferably of from about 20 micrometers or
less, more preferably from about 1 micrometer or less, and most
preferably of from about 0.05 to about 1 micrometer.
[0154] The first dielectric layer and the second dielectric layer,
may comprise any organic or inorganic dielectric material commonly
used in the production of microelectronic devices. It is most
preferred to use dielectrics of low dielectric constant, k, values
in the practice of the present invention. The dielectrics may
nonexclusively include OSG's, silicon containing spin-on glasses,
i.e. silicon containing polymer such as an alkoxysilane polymer, a
silsesquioxane polymer, a siloxane polymer; a poly(arylene ether),
a fluorinated poly(arylene ether), other polymeric dielectric
materials, nanoporous silica, or mixtures thereof. One useful
polymeric dielectric material useful for the invention includes an
nanoporous silica alkoxysilane polymer formed from an alkoxysilane
monomer which has the formula: 1
[0155] wherein at least 2 of the R groups are independently C.sub.1
to C.sub.4 alkoxy groups and the balance, if any, are independently
selected from the group consisting of hydrogen, alkyl, phenyl,
halogen, substituted phenyl. Preferably each R is methoxy, ethoxy
or propoxy. Such are commercially available from Honeywell
International Inc. as Nanoglass.TM.. The most preferred
alkoxysilane monomer is tetraethoxysilane (TEOS). Also useful are
hydrogensiloxanes which have the formula
[(HSiO.sub.1.5).sub.xO.sub.y].sub.n, hydrogensilsesquioxanes which
have the formula (HSiO.sub.1.5).sub.n, and hydroorganosiloxanes
which have the formulae
[(HSiO.sub.1.5).sub.xO.sub.y(RSiO.sub.1.5).sub.z]- .sub.n,
[(HSiO.sub.1.5).sub.x(RSiO.sub.1.5).sub.y].sub.n and
[(HSiO.sub.1.5).sub.xO.sub.y(RSiO.sub.1.5).sub.z].sub.n. In each of
these polymer formulae, x=about 6 to about 20, y=1 to about 3,
z=about 6 to about 20, n=1 to about 4,000, and each R is
independently H, C.sub.1 to C.sub.8 alkyl or C.sub.6 to C.sub.12
aryl. The weight average molecular weight may range from about
1,000 to about 220,000. In the preferred embodiment n ranges from
about 100 to about 800 yielding a molecular weight of from about
5,000 to about 45,000. More preferably, n ranges from about 250 to
about 650 yielding a molecular weight of from about 14,000 to about
36,000. Useful polymers within the context of this invention
nonexclusively include hydrogensiloxane, hydrogensilsesquioxane,
hydrogenmethylsiloxane, hydrogenethylsiloxane,
hydrogenpropylsiloxane, hydrogenbutylsiloxane,
hydrogentert-butylsiloxane- , hydrogenphenylsiloxane,
hydrogenmethylsilsesquioxane, hydrogenethylsilsesquioxane,
hydrogenpropylsilsesquioxane, hydrogenbutylsilsesquioxane,
hydrogentert-butylsilsesquioxane and hydrogenphenylsilsesquioxane
and mixtures thereof. The hydroorganosiloxanes, poly(arylene
ethers), fluorinated poly(arylene ethers) and mixtures thereof are
preferred. Suitable poly(arylene ethers) or fluorinated
poly(arylene ethers) are known in the art from U.S. Pat. Nos.
5,155,175; 5,114,780 and 5,115,082. Preferred poly(arylene ethers)
and fluorinated poly(arylene ethers) are disclosed in U.S. patent
application Ser. No. 08/990,157 filed Dec. 12, 1997 which is
incorporated herein by reference. Preferred siloxane materials
suitable for use in this invention are commercially available from
Honeywell International Inc. under the tradename Accuglass.RTM.
T-11, T-12 and T-14. Also useful are methylated siloxane polymers
available from Honeywell International Inc. under the tradenames
Purespin.TM. and Accuspin.RTM. T18, T23 and T24. Preferred silicon
containing dielectric polymers have a formula selected from the
group consisting of [(HSiO.sub.1.5).sub.xO.sub.y].sub.n-
,(HSiO.sub.1.5).sub.n,
[(HSiO.sub.1.5).sub.xO.sub.y(RSiO.sub.1.5).sub.z].s- ub.n,
[(HSiO.sub.1.5).sub.x(RSiO.sub.1.5).sub.y].sub.n and
[(HSiO.sub.1.5).sub.xO.sub.y(RSiO.sub.1.5).sub.z].sub.n wherein
x=about 6 to about 20, y=1 to about 3, z=about 6 to about 20, n=1
to about 4,000, and each R is independently H, C.sub.1 to C.sub.8
alkyl or C.sub.6 to C.sub.12 aryl which are disclosed in U.S.
patent application Ser. No. 08/955,802 filed Oct. 22, 1997 and
which is incorporated herein by reference. Also preferred are
certain low organic content silicon containing polymers such as
those having the formula I:
[H--SiO.sub.1.5].sub.n[R--SiO.sub.1.5].sub.m,
[H.sub.0.4-1.0SiO.sub.1.5-1.8].sub.n[R.sub.0.4-1.0-SiO.sub.1.5-1.8].sub.m,
[H.sub.0-1.0SiO.sub.1.5-2.0].sub.n[R--SiO.sub.1.5].sub.m,
[H--SiO.sub.1.5].sub.x[R--SiO.sub.1.5].sub.y[SiO.sub.2].sub.z,
[0156] wherein the sum of n and m, or the sum or x, y and z is from
about 8 to about 5000, and m and y are selected such that carbon
containing substituents are present in an amount of less than about
40 Mole percent. Polymers having the structure I are of low organic
content where the carbon containing substituents are present in an
amount of less than about 40 mole percent. These polymers are
described more fully in U.S. patent application Ser. No.
09/044,831, filed Mar. 20, 1998, which is incorporated herein by
reference. Also preferred are certain high organic content silicon
containing polymers such as those having the formula II:
[HSiO.sub.1.5].sub.n[RSiO.sub.1.5].sub.m,
[H.sub.0.4-1.0SiO.sub.1.5-1.8].sub.n[R.sub.0.4-1.0SiO.sub.1.5-1.8].sub.m,
[H.sub.0-1.0SiO.sub.1.5-2.0].sub.n[RSiO.sub.1.5].sub.m,
[0157] wherein the sum of n and m is from about 8 to about 5000 and
m is selected such that the carbon containing substituent is
present in an amount of from about 40 percent or greater; and
[HSiO.sub.1.5].sub.x[RSiO.sub.1.5].sub.y[SiO.sub.2].sub.z;
[0158] wherein the sum of x, y and z is from about 8 to about 5000
and y is selected such that the carbon containing substituent is
present in an amount of about 40 Mole % or greater; and wherein R
is selected from substituted and unsubstituted straight chain and
branched alkyl groups, cycloalkyl groups, substituted and
unsubstituted aryl groups, and mixtures thereof. The specific mole
percent of carbon containing substituents is a function of the
ratio of the amounts of starting materials. Polymers having the
structure II which are of high organic content where the carbon
containing substituents are present in an amount of about 40 mole
percent or more. These polymers are described more fully in U.S.
patent application Ser. No. 09/044,798, filed Mar. 20, 1998, which
is incorporated herein by reference. The polymer may be present in
the dielectric composition in a pure or neat state (not mixed with
any solvents) or it may be present in a solution where it is mixed
with solvents. When solvents are present, the polymer is preferably
present in an amount of from about 1% to about 50% by weight of the
polymer, more preferably from about 3% to about 20%. The solvent
component is preferably present in an amount of from about 50% to
about 99% by weight of the dielectric composition, more preferably
from about 80% to about 97%. Suitable solvents nonexclusively
include aprotic solvents such as cyclic ketones including
cyclopentanone, cyclohexanone, cyclohexanone and cyclooctanone;
cyclic amides such as N-alkylpyrrolidinone wherein the alkyl group
has from 1 to about 4 carbon atoms, and N-cyclohexyl-pyrrolidinone,
and mixtures thereof.
[0159] Deposition of dielectric materials onto the substrate may be
conducted via conventional methods such as spin-coating, dip
coating, roller coating, spraying, chemical vapor deposition,
meniscus coating, and the like which are well-known in the art.
Spin coating is most preferred. The thickness of the dielectric
layers may vary depending on the deposition procedure and parameter
setup, but typically the thickness may range from about 500 .ANG.
to about 50,000 .ANG., and preferably from about 2000 .ANG. to
about 12000 .ANG.. In the most preferred embodiment, a liquid
dielectric composition is spun onto the appropriate surface
according to known spin techniques such as by applying a liquid
dielectric composition to the surface and then spinning on a
rotating wheel at speeds ranging from about 500 to about 6000 rpm
for about 5 to about 60 seconds.
[0160] The dielectric materials may optionally be heated to expel
residual solvent or to increase its molecular weight. The heating
may be conducted by conventional means such as heating on a hot
plate in air or in an inert atmosphere, or it may occur in a
furnace or oven in air, or in an inert atmosphere, or it may occur
in a vacuum furnace or vacuum oven. Heating is preferably conducted
at a temperature of from about 80.degree. C. to about 500.degree.
C., and more preferably from about 150.degree. C. to about
425.degree. C. This heating is preferably performed from about 1
minute to about 360 minutes, and more preferably from about 2 to
about 60 minutes. The dielectric materials may also optionally be
exposed to actinic light, such as UV light, to increase their
molecular weight. The amount of exposure may range from about 100
mJ/cm.sup.2 to about 300 mJ/cm.sup.2. The dielectric materials may
optionally be cured by overall exposed to electron beam radiation.
Electron beam exposure may be controlled by setting the beam
acceleration. Electron beam radiation may take place in any chamber
having a means for providing electron beam radiation to substrates
placed therein. It is preferred that the electron beam exposing
step is conducted with a wide, large beam of electron radiation
from a large-area electron beam source. Preferably, an electron
beam chamber is used which provides a large area electron source.
Suitable electron beam chambers are commercially available from
Electron Vision Corporation of San Diego, Calif. under the trade
name "ElectronCure.TM.". The principles of operation and
performance characteristics of such device are described in U.S.
Pat. No. 5,003,178, the disclosure of which is incorporated herein
by reference. The temperature of the electron beam exposure
preferably ranges from about 20.degree. C. to about 450.degree. C.,
more preferably from about 50.degree. C. to about 400.degree. C.
and most preferably from about 200.degree. C. to about 400.degree.
C. The electron beam energy is preferably from about 0.5 KeV to
about 30 KeV, and more preferably from about 3 to about 10 KeV. The
dose of electrons is preferably from about 1 to about 50,000
.mu.C/cm.sup.2 and more preferably from about 50 to about 20,000
.mu.C/cm.sup.2. The gas ambient in the electron beam tool can be
any of the following gases: nitrogen, oxygen, hydrogen, argon, a
blend of hydrogen and nitrogen, ammonia, xenon or any combination
of these gases. The electron beam current is preferably from about
1 to about 40 mA, and more preferably from about 5 to about 20 mA.
Preferably, the electron beam exposing step is conducted with a
wide, large beam of electron beam radiation from a uniform
large-are electron beam source which covers an area of from about 4
inches to about 256 square inches.
[0161] In the practice of the present invention, it is preferred
that the first dielectric layer has significantly different etch
resistance properties from the optional etch stop layer, and the
optional etch stop layer has significantly different etch
resistance properties from the second dielectric layer. The first
dielectric layer may be the same or different from the second
dielectric layer. If the optional etch stop layer is not present,
the first dielectric layer should have substantially the same or
significantly different etch resistance properties from the second
dielectric layer. When the first and second dielectric layers have
substantially the same etch resistance properties and no etch stop
layer is present, etching may be done by controlling the duration
of time for the etching of each layer. Useful etch stop layers
non-exclusively include silicon nitride, silicon oxynitride,
silicon dioxide, silicon carbide, silicon oxycarbide, spin on
solutions such as spin on glass, organic polymers, hydrogen
silsesquioxane and methyl silsesquioxane and combinations
thereof.
[0162] The photoresist component may be positive working or
negative working and is generally commercially available. Positive
working photoresists are more preferred in the practice of the
present invention. Suitable positive working photoresist materials
are well known in the art and may comprise an o-quinone diazide
radiation sensitizer. The o-quinone diazide sensitizers include the
o-quinone-4-or-5-sulfonyl-diazides disclosed in U.S. Pat. Nos.
2,797,213; 3,106,465; 3,148,983; 3,130,047; 3,201,329; 3,785,825;
and 3,802,885. When o-quinone diazides are used, preferred binding
resins include a water insoluble, aqueous alkaline soluble or
swellable binding resin, which is preferably a novolak. Suitable
positive photodielectric resins may be obtained commercially, for
example, under the trade name of AZ-P4620 from Clariant Corporation
of Somerville, N.J. The photoresist material may be deposited by
conventional means such as spin coating. The thickness of
photoresist layers may vary depending on the deposition procedure
and parameter setup. The thickness preferably ranges from about
1,000 .ANG. to about 30,000 .ANG., more preferably from about 2,000
.ANG. to about 10,000 .ANG., and most preferably from about 3,000
.ANG. to about 7,500 .ANG..
[0163] Imagewise removal of the photoresist is conducted in a
manner well known in the art such as by imagewise exposing the
photoresist to actinic radiation such as through a suitable mask
and developing the photoresist. The photoresist may be imagewise
exposed to actinic radiation such as light in the visible,
ultraviolet or infrared regions of the spectrum through a mask, or
scanned by an electron beam, ion or neutron beam or x-ray
radiation. Actinic radiation may be in the form of incoherent light
or coherent light, for example, light from a laser. The photoresist
is then imagewise developed using a suitable solvent, such as an
aqueous alkaline solution. Optionally the photoresist is heated to
cure the image portions thereof and thereafter developed to remove
the non-image portions and define a via mask.
[0164] Via is a term known in the art which includes holes and
apertures. Vias may be filled with metals or other conductive
materials to form electrical connections with other metals or
conductive contacts. Although this invention refers to at least one
via, it is preferred that a plurality of vias be formed in the
practice of the present invention. These vias preferably extend
downward to underlying metal contacts.
[0165] Trench is a term known in the art which includes tunnel-like
connections between vias. Like vias, trenches also may be filled
with metals or other conductive materials to form electrical
connections with other metals or conductive contacts. Although this
invention refers to at least one trench, it is preferred that a
plurality of trenches be formed in the practice of the present
invention. These trenches preferably connect two or more vias.
[0166] The protective material serves to prevent contact between
the photoresist and the dielectrics, thus preventing resist
poisoning. The protective material may be deposited onto a surface
of a dielectric material, as described above, or it may be formed
on the surface of a dielectric material through surface
modification, as described below.
[0167] A deposited protective material may be deposited by
conventional means such as CVD, PVD, spin coating or the like.
Suitable deposited protective materials nonexclusively include CVD
oxide, CVD nitride, CVD oxynitride, CVD SiC, spin on solutions such
as organic polymers, SOG, chromophore laden SOGs such as those
described in U.S. patent application Ser. No. 09/330,248 filed Jun.
10, 1999 which is incorporated herein by reference, anti reflective
coating (ARC) materials such as those described in U.S. Pat. No.
6,033,830 and bottom anti reflective coating materials (BARC) such
as silicon oxynitrides and the materials described in U.S. Pat. No.
6,121,123, hydrogen silsesquioxane and methyl silsesquioxane and
metals such as Ta and TaN. Preferably, the deposited protective
material may comprise SOG and chromophore laden SOG. The most
preferred deposited protective material in the practice of this
invention is chromophore laden SOG.
[0168] The barrier metal on the sidewalls and floor of the vias and
trenches serves to prevent diffusion of the subsequently deposited
conductive metal into the dielectric layers. Suitable barrier
metals nonexclusively include Ti, Ta, or a nitride such as TaN or
TiN. Barrier metals may be applied by conventional techniques such
as vapor deposition, sputtering, evaporation and the like. The
thickness of the barrier metal may vary depending on the deposition
procedure and parameter setup desired. The thickness preferably
ranges from about 25 .ANG. to about 1000 .ANG., more preferably
from about 50 .ANG. to about 500 .ANG., and most preferably from
about 100 .ANG. to about 300 .ANG..
[0169] Suitable fill metals include aluminum, aluminum alloys,
copper, copper alloys, tantalum, tungsten, titanium or other metals
or combinations thereof as typically employed in the formation of
microelectronic devices. Copper is most preferred. The fill metals
may also be applied by such techniques as vapor deposition,
sputtering, evaporation, electroplating, electroless plating and
the like. As used herein, the term "metal" includes amalgams of
metals.
[0170] In a second embodiment of the present invention, as shown in
FIG. 2(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As shown in FIG. 2(b), a layer of a photoresist material is then
deposited on the second dielectric layer, and a portion of the
photoresist is imagewise removed to outline a via for the second
dielectric layer. FIG. 2(b) also shows that portions are removed
from the second dielectric layer and the optional etch stop layer
which are under the removed portions of the photoresist to form at
least one via down through the second dielectric layer and the
optional etch stop layer. The balance of the photoresist layer is
then removed, as shown in FIG. 2(c), and a protective material is
deposited on a top surface of the second dielectric layer and on
inside walls and a floor of the via, as shown in FIG. 2(d). An
additional layer of a photoresist is deposited on the protective
material, and then a portion of the additional photoresist is
imagewise removed to outline a trench for the second dielectric
layer, as shown in FIG. 2(e). Portions are removed from each of the
protective material and the second dielectric layer which are under
the removed portion of the additional photoresist layer, to form at
least one trench down through the second dielectric layer, as shown
in FIG. 2(f). Also shown in FIG. 2(f), portions of the first
dielectric layer which are under the via which was in the second
dielectric layer are removed to form a via down through the first
dielectric layer. As shown in FIG. 2(g), the balance of the
additional photoresist layer is then removed, and the balance of
the protective material is removed. Inside walls and a floor of the
via and the trench are lined with a barrier metal, and then the
trench and via are filled with a fill metal in contact with the
barrier metal lining, as shown in FIG. 2(h).
[0171] In a third embodiment of the present invention, as shown in
FIG. 3(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention. A
layer of a photoresist material is then deposited on a top surface
of the second dielectric layer, and a portion of the photoresist is
imagewise removed to outline a trench for the second dielectric
layer, as shown in FIG. 3(b). As also shown in FIG. 3(b), portions
of the second dielectric layer which are under the removed portions
of the photoresist are removed to form at least one trench down
through the second dielectric layer. The balance of the photoresist
layer is then removed, as shown in FIG. 3(c), and a protective
material is deposited on a top surface of the second dielectric
layer and on inside walls and a floor of the trench, as shown in
FIG. 3(d). An additional layer of a photoresist is deposited on the
protective material, and then a portion of the additional
photoresist is imagewise removed to outline a via for the first
dielectric layer, as shown in FIG. 3(e). Portions are removed from
each layer under the removed portions of the additional
photoresist, to form at least one via down through the protective
material, the optional etch stop layer, and the first dielectric
layer, as shown in FIG. 3(f). The balance of the additional
photoresist layer is then removed, and the balance of the
protective material is removed, as shown in FIG. 3(g). Inside walls
and a floor of the via and the trench are lined with a barrier
metal, and then the trench and via are filled with a fill metal in
contact with the barrier metal lining, as shown in FIG. 3(h).
[0172] In a fourth embodiment of the present invention, as shown in
FIG. 4(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention. A
layer of a photoresist material is then deposited on a top surface
of the second dielectric layer, and a portion of the photoresist is
imagewise removed to outline a via for the first dielectric layer,
as shown in FIG. 4(b). As also shown in FIG. 4(b), portions are
removed from each layer under the removed portions of the
photoresist, to form at least one via down through the second
dielectric layer, the optional etch stop layer, and first
dielectric layer. The balance of the photoresist layer is then
removed, as shown in FIG. 4(c). As shown in FIG. 4(d), a top
surface of the second dielectric layer and a surface of inside
walls and a floor of the via are modified, thus forming a
protective material thereon. The depth of the modified region may
vary from about 5 .ANG. to about 1000 .ANG.. An additional layer of
a photoresist is deposited on the protective material of these
modified surfaces, and a portion of the additional photoresist is
imagewise removed to outline a trench for the second dielectric
layer, as shown in FIG. 4(e). Portions are removed from the
protective material on the top surface of the second dielectric
layer, the second dielectric layer, and the walls of the via within
the second dielectric layer, which are under the removed portion of
the additional photoresist layer, to form at least one trench down
through the second dielectric layer, as shown in FIG. 4(f). The
balance of the additional photoresist layer is then removed, as
shown in FIG. 4(g). Inside walls and a floor of the via and the
trench are lined with a barrier metal, and then the trench and via
are filled with a fill metal in contact with the barrier metal
lining, as shown in FIG. 4(h). The protective material may be
formed by surface modification of the walls and floor of the vias,
trenches and dielectric layers such as by exposure to CVD plasmas,
wet chemical exposure, annealing in controlled ambients, UV
exposure and E-beam exposure. Suitable surface-modified CVD plasmas
include N.sub.2/H.sub.2, H.sub.2, NH.sub.3 ,N.sub.2O, N.sub.2,
O.sub.2, Ar, Xe.
[0173] In a fifth embodiment of the present invention, as shown in
FIG. 5(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention. A
layer of a photoresist material is then deposited on a top surface
of the second dielectric layer, and a portion of the photoresist is
imagewise removed to outline a via for the second dielectric layer
and the optional etch stop layer, as shown in FIG. 5(b). As also
shown in FIG. 5(b), portions are removed from the second dielectric
layer and the optional etch stop layer which are under the removed
portions of the photoresist, to form at least one via down through
the second dielectric layer and the optional etch stop layer. The
balance of the photoresist layer is then removed, as shown in FIG.
5(c). A top surface of the second dielectric layer and a surface of
inside walls and a floor of the trench are modified, thus forming a
protective material thereon, as shown in FIG. 5(d). An additional
layer of a photoresist is deposited on the protective material of
the modified surfaces, and a portion of the additional photoresist
is imagewise removed to outline a trench for the second dielectric
layer, as shown in FIG. 5(e). Portions are removed of the
protective material on the top surface of the second dielectric
layer, the second dielectric layer, and the protective material on
the walls of the via within the second dielectric layer which are
under the removed portions of the additional photoresist, to form
at least one trench down through the second dielectric layer, as
shown in FIG. 5(f). As also shown in FIG. 5(f), portions of the
protective material on the floor of the via which was in the second
dielectric layer, and portions of the first dielectric layer under
the via which was in the second dielectric layer are removed to
form a via down through the first dielectric layer. The balance of
the additional photoresist layer is then removed, as shown in FIG.
5(g). Inside walls and a floor of the via and the trench are lined
with a barrier metal, and then the trench and via are filled with a
fill metal in contact with the barrier metal lining, as shown in
FIG. 5(h).
[0174] In a sixth embodiment of the present invention, as shown in
FIG. 6(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention. A
layer of a photoresist material is then deposited on a top surface
of the second dielectric layer, and a portion of the photoresist is
imagewise removed to outline a via for the first dielectric layer,
as shown in FIG. 6(b). As also shown in FIG. 6(b), portions are
removed from each of the layers which are under the removed
portions of the photoresist, to form a via down through the second
dielectric layer, the optional etch stop layer, and the first
dielectric layer. The balance of the photoresist layer is then
removed, as shown in FIG. 6(c), and a barrier material is deposited
on a top surface of the second dielectric layer and on a surface of
inside walls and a floor of the via to form a barrier material
layer on these surfaces, as shown in FIG. 6(d). An additional layer
of a photoresist is deposited on the barrier material layer on the
top surface of the second dielectric layer and on the walls and a
floor of the via through the second dielectric layer, optional etch
stop layer, and first dielectric layer, and a portion of the
additional photoresist is imagewise removed to outline a trench for
the second dielectric layer, as shown in FIG. 6(e). Portions are
removed of the barrier material layer on the top surface of the
second dielectric layer, the second dielectric layer, and the walls
of the via within the second dielectric layer which are under the
removed portion of the additional photoresist layer to form at
least one trench down through the second dielectric layer, as shown
in FIG. 6(f). The balance of the additional photoresist layer is
then removed, as shown in FIG. 6(g). Inside walls and a floor of
the via and the trench are lined with a barrier metal, and then the
trench and via are filled with a fill metal in contact with the
barrier metal lining, as shown in FIG. 6(h).
[0175] The barrier layer material serves to form a barrier between
the photoresist and the dielectrics, thus preventing resist
poisoning. Suitable barrier layer materials nonexclusively include
CVD oxide, CVD nitride, CVD oxynitride, CVD SiC, spin on solutions
such as organic polymers, SOG, chromophore laden SOGs as described
in U.S. patent application Ser. No. 09/330,248 filed Jun. 10, 1999,
hydrogen silsesquioxane, methyl silsesquioxane and metals such as
Ta and TaN. Preferably, the barrier layer material is CVD
SiO.sub.2, SiN, or SiC. The most preferred barrier layer material
in the practice of this invention is SiO.sub.2.
[0176] The barrier layer material may be deposited by conventional
means such as CVD, evaporation, spin coating, sputtering, and
atomic layer epitaxy. The thickness of protective material may vary
depending on the deposition procedure.
[0177] In a seventh embodiment of the present invention, as shown
in FIG. 7(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As shown in FIG. 7(b), a layer of a photoresist material is then
deposited on a top surface of the second dielectric layer, and a
portion of the photoresist is imagewise removed to outline a via
for the second dielectric layer and the optional etch stop layer.
As also shown in FIG. 7(b), portions are removed of the second
dielectric layer and the optional etch stop layer which are under
the removed portions of the photoresist, to form a via down through
the second dielectric layer and the optional etch stop layer. The
balance of the photoresist layer is then removed, as shown in FIG.
7(c), and a barrier material is deposited on a top surface of the
second dielectric layer and on a surface of inside walls and a
floor of the via through the second dielectric layer and optional
etch stop layer to form a barrier material layer on these surfaces,
as shown in FIG. 7(d). An additional layer of a photoresist is
deposited on the barrier material layer on the top surface of the
second dielectric layer and on the walls and a floor of the via
through the second dielectric layer and the optional etch stop
layer, and a portion of the additional photoresist is imagewise
removed to outline a trench for the second dielectric layer, as
shown in FIG. 7(e). Portions are removed of the barrier material
layer on the top surface of the second dielectric layer, the second
dielectric layer, and the walls of the via within the second
dielectric layer which are under the removed portion of the
additional photoresist layer to form at least one trench down
through the second dielectric layer, as shown in FIG. 7(f). As also
shown in FIG. 7(f), portions are removed of the barrier material
layer on the floor of the via which was in the second dielectric
layer, and portions are removed of the first dielectric layer under
the via which was in the second dielectric layer, to form a via
down through the first dielectric layer. The balance of the
additional photoresist layer is then removed, as shown in FIG.
7(g). Inside walls and a floor of the via and the trench are lined
with a barrier metal, and then the trench and via are filled with a
fill metal in contact with the barrier metal lining, as shown in
FIG. 7(h).
[0178] In an eighth embodiment of the present invention, as shown
in FIG. 8(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As shown in FIG. 8(b), a layer of a photoresist material is then
deposited on a top surface of the second dielectric layer, and a
portion of the photoresist is imagewise removed to outline a trench
for the second dielectric layer. As also shown in FIG. 8(b),
portions of the second dielectric layer which are under the removed
portions of the photoresist are removed to form at least one trench
down through the second dielectric layer. The balance of the
photoresist layer is then removed, as shown in FIG. 8(c), and the
top surface of the second dielectric layer and a surface of inside
walls and a floor of the trench are modified to form a protective
material thereon, as shown in FIG. 8(d). An additional layer of a
photoresist is deposited on the protective material on the top
surface of the second dielectric layer and on the walls and a floor
of the trench, and a portion of the additional photoresist is
imagewise removed to outline a via for the first dielectric layer,
as shown in FIG. 8(e). Portions are removed each layer which are
under the removed portion of the additional photoresist layer to
form at least one via down through the first dielectric layer, as
shown in FIG. 8(f). The balance of the additional photoresist layer
is then removed, as shown in FIG. 8(g). Inside walls and a floor of
the via and the trench are lined with a barrier metal, and then the
trench and via are filled with a fill metal in contact with the
barrier metal lining, as shown in FIG. 8(h).
[0179] In a ninth embodiment of the present invention, as shown in
FIG. 9(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As shown in FIG. 9(b), a layer of a photoresist material is then
deposited on a top surface of the second dielectric layer, and a
portion of the photoresist is imagewise removed to outline a trench
for the second dielectric layer. As also shown in FIG. 9(b),
portions of the second dielectric layer, and optionally portions of
the etch stop layer if present which are under the removed portions
of the photoresist are removed to form at least one trench down
through the second dielectric layer and optionally through the etch
stop layer. The balance of the photoresist layer is then removed,
as shown in FIG. 9(c), and a barrier material is deposited on a top
surface of the second dielectric layer and on a surface of inside
walls and a floor of the trench to form a barrier material layer
thereon, as shown in FIG. 9(d). An additional layer of a
photoresist is deposited on the barrier material layer on the top
surface of the second dielectric layer and on the walls and a floor
of the trench, and a portion of the additional photoresist is
imagewise removed to outline a via for the first dielectric layer,
as shown in FIG. 9(e). Portions are removed of the barrier material
layer on the floor of the trench, any remaining portions of the
etch stop layer, and portions of the first dielectric layer which
are under the removed portion of the additional photoresist layer
to form at least one via down through the barrier material layer on
the floor of the trench, the optional etch stop layer, and the
first dielectric layer, as shown in FIG. 9(f). The balance of the
additional photoresist layer is then removed, as shown in FIG.
9(g). Inside walls and a floor of the via and the trench are lined
with a barrier metal, and then the trench and via are filled with a
fill metal in contact with the barrier metal lining, as shown in
FIG. 9(h).
[0180] In a tenth embodiment of the present invention, as shown in
FIG. 10(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As also shown in FIG. 10(a), a layer of a first hardmask material
is then deposited on the second dielectric layer, and a layer of a
second hardmask layer is deposited on the first hardmask layer. A
layer of a photoresist material is then deposited on the top
surface of the second hardmask layer, and a portion of the
photoresist is imagewise removed to outline a via for the second
hardmask layer, as shown in FIG. 10(b). Portions are removed from
the second hardmask layer under the removed portions of the
photoresist, to form at least one via down through the second
hardmask layer, as also shown in FIG. 10(b). The balance of the
photoresist layer is then removed, as shown in FIG. 10(c).
[0181] An additional layer of a photoresist is deposited on the
second hardmask layer, and on inside walls and a floor of the via
in the second hardmask layer, as shown in FIG. 10(d). As also shown
in FIG. 10(d), a portion of the additional photoresist is imagewise
removed to outline at least one trench for the second hardmask
layer. Portions are removed from the first hardmask layer and the
second dielectric layer which are under the via in the second
hardmask layer, to form a via down through the first hardmask layer
and the second dielectric layer, as shown in FIG. 10(e). Portions
are then removed from second hardmask layer which are under the
removed portions of the additional photoresist, to form a trench
down through the second hardmask layer, as shown in FIG. 10(f). As
also shown in FIG. 10(f), portions are removed of the optional etch
stop layer which are under the via in the second dielectric layer,
to extend the via down through the optional etch stop layer.
Portions are then removed of the first hardmask layer and the
second dielectric layer which are under the trench in the second
hardmask layer, to form trench down through the first hardmask
layer and the second dielectric layer, as shown in FIG. 10(g). This
figure also shows that, portions are then removed of the first
dielectric layer under the via which was in the second dielectric
layer, to form a via through the first dielectric layer. As also
shown in FIG. 10(g), the balance of the additional photoresist
layer is then removed. This figure also shows that a via is then
formed through the first dielectric layer under the via which was
previously formed through the second dielectric layer. Portions of
the first hardmask layer and second dielectric layer which are
under the trench in the second hardmask layer are then removed to
form a trench through the second dielectric layer, as also shown in
FIG. 10(g). Inside walls and a floor of the via and the trench are
lined with a barrier metal, and then the trench and via are filled
with a fill metal in contact with the barrier metal lining, as
shown in FIG. 10(h).
[0182] In an eleventh embodiment of the present invention, as shown
in FIG. 11(a), a first dielectric material, optional etch stop
material, and second dielectric material are deposited onto a
substrate as they were in the first embodiment of this invention.
As also shown in FIG. 11(a), a layer of a first hardmask material
is then deposited on the second dielectric layer, and a layer of a
second hardmask layer is deposited on the first hardmask layer. A
layer of a photoresist material is then deposited on the top
surface of the second hardmask layer, and a portion of the
photoresist is imagewise removed to outline a trench for the second
hardmask layer, as shown in FIG. 11(b). As also shown in FIG.
11(b), portions are removed from the second hardmask layer under
the removed portions of the photoresist, to form at least one
trench down through the second hardmask layer. The balance of the
photoresist layer is then removed, as shown in FIG. 11(c). An
additional layer of a photoresist is deposited on the second
hardmask layer, and on inside walls and a floor of the trench in
the second hardmask layer, as shown in FIG. 11(d). As also shown in
FIG. 11(d), a portion of the additional photoresist is imagewise
removed to outline at least one via for the second dielectric layer
and the optional etch stop layer. As shown in FIG. 11(e), portions
are removed from the first hardmask layer, the second dielectric
layer, and the optional etch stop layer which are under the removed
portion of the additional photoresist layer, to form a via down
through the second dielectric layer and optional etch stop layer.
The balance of the additional photoresist layer is then removed, as
shown in FIG. 11(f). Portions are removed of the first hardmask
layer and the second dielectric layer which are under the trench in
the second hardmask layer, to form a trench down through the second
dielectric layer, as shown in FIG. 11(g). As also shown in FIG.
11(g), portions are then removed of the first dielectric layer
corresponding to the via which was in the second dielectric layer
or optional etch stop layer, thus forming at least one via down
through the first dielectric layer. Inside walls and a floor of the
via and the trench are lined with a barrier metal, and then the
trench and via are filled with a fill metal in contact with the
barrier metal lining, as shown in FIG. 11(h).
[0183] The first and second hardmask layers serve to form a mask
which prevents the photoresist from reacting with the dielectrics,
thus preventing resist poisoning.
[0184] Suitable hardmask layer materials nonexclusively include CVD
films such as SiO2, SiN, SiON, SiOC, SiC, spin on polymers such as
spin on glass, chromophore laden SOG, organic spin on polymers ,
hydrogen silsesquioxane, methyl silsesquioxane and metals such as
Ta, TaN . Preferably, the hardmask layer material is SiO.sub.2,
SiON, SiN, or SiC. Most preferably, the first hardmask layer
comprises SiO.sub.2, and the second hardmask layer comprises
Si.sub.3N.sub.4. Although this application refers only to first and
second hardmask layers, a plurality of hardmask layers be used in
the practice of the present invention. The hardmask layers may be
deposited by conventional means such as CVD, spin-on, evaporation,
sputtering, atomic layer epitaxy. The thickness of the hardmask
layers may be the same or different, and may vary depending on the
deposition procedure and parameter setup. The thicknesses
preferably range from about 100 .ANG. to about 5000 .ANG., more
preferably from about 200 .ANG. to about 3000 .ANG., and most
preferably from about 400 .ANG. to about 1500 .ANG..
[0185] The figures of the present invention show a process for the
formation of one interconnect level, however, the same processing
steps can be repeated again for upper levels of interconnects.
[0186] While the present invention has been particularly shown and
described with reference to preferred embodiments, it will be
readily appreciated by those of ordinary skill in the art that
various changes and modifications may be made without departing
from the spirit and scope of the invention. It is intended that the
claims be interpreted to cover the disclosed embodiment, those
alternatives which have been discussed above and all equivalents
thereto.
* * * * *