U.S. patent application number 10/932032 was filed with the patent office on 2005-02-03 for method for manufacturing a semiconductor device and semiconductor device with overlay mark.
This patent application is currently assigned to SAMSUNG ELECTRONICS., LTD.. Invention is credited to Kim, Dae-Joung, Oh, Seok-Hwan.
Application Number | 20050026385 10/932032 |
Document ID | / |
Family ID | 32105560 |
Filed Date | 2005-02-03 |
United States Patent
Application |
20050026385 |
Kind Code |
A1 |
Kim, Dae-Joung ; et
al. |
February 3, 2005 |
Method for manufacturing a semiconductor device and semiconductor
device with overlay mark
Abstract
In a method for forming a semiconductor device and a
semiconductor device having an overlay mark, a first pattern for
the semiconductor device is formed in a semiconductor device
formation region of a semiconductor substrate and simultaneously in
a first mark formation region of the semiconductor substrate. A
second pattern for the semiconductor device is formed on a
resultant structure in the semiconductor device formation region of
the semiconductor substrate and simultaneously in a second mark
formation region of the semiconductor substrate. The first and
second patterns in the first and second mark formation regions,
respectively, are inspected for misalignments using overlay marks
formed to have shapes and sizes identical to those of real patterns
in the semiconductor device formation region of the semiconductor
substrate. By measuring misalignments of real patterns using the
overlay marks, overlay mismatch between the semiconductor device
formation region and the overlay mark may be prevented.
Inventors: |
Kim, Dae-Joung; (Suwon-si,
KR) ; Oh, Seok-Hwan; (Yongin-si, KR) |
Correspondence
Address: |
LEE & STERBA, P.C.
SUITE 2000
1101 WILSON BOULEVARD
ARLINGTON
VA
22209
US
|
Assignee: |
SAMSUNG ELECTRONICS., LTD.
Suwon-city
KR
|
Family ID: |
32105560 |
Appl. No.: |
10/932032 |
Filed: |
September 2, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10932032 |
Sep 2, 2004 |
|
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10602149 |
Jun 25, 2003 |
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6803292 |
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Current U.S.
Class: |
438/401 ;
257/797; 438/16 |
Current CPC
Class: |
G03F 7/70633
20130101 |
Class at
Publication: |
438/401 ;
257/797; 438/016 |
International
Class: |
H01L 021/425; H01L
021/66 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 9, 2002 |
KR |
2002-47249 |
Claims
1-5. (Cancelled)
6. A semiconductor device having an overlay mark, the overlay mark,
comprising: a first mark formed in a first mark formation region of
a semiconductor substrate and a first pattern formed in a
semiconductor device formation region of the semiconductor
substrate, wherein the first mark and the first pattern are formed
simultaneously by a same process such that the first mark has a
shape identical to a shape of the first pattern; and a second mark
formed in a second mark formation region of the semiconductor
substrate and a second pattern formed in the semiconductor device
formation region of the semiconductor substrate, wherein the second
mark and the second pattern are formed simultaneously by a same
process such that the second mark has a shape identical to a shape
of the second pattern.
7. The semiconductor device as claimed in claim 6, wherein the
first mark formation region is a box shaped main scale formation
region, and the second mark formation region is a box shaped
vernier formation region.
8. The semiconductor device as claimed in claim 7, wherein the
first pattern is an active pattern in a DRAM cell region, and the
second pattern is a word line pattern in the DRAM cell region.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for manufacturing
a semiconductor device and a semiconductor device having an overlay
mark. More particularly, the present invention relates to a method
for manufacturing a semiconductor device wherein mismatching
between a region in which the semiconductor device is formed and an
overlay mark may be minimized by forming the overlay mark to have a
pattern identical to that of the region, and a semiconductor device
having the overlay mark.
[0003] 2. Description of the Related Art
[0004] In general, an electric circuit of a semiconductor device is
manufactured through repeating a series of unit processes such as
deposition, photolithography, etc., in order to form circuit
patterns on a substrate. In a photolithography process, a
photoresist film is exposed using a mask in which a circuit pattern
is formed. The photoresist film is developed after being coated on
a wafer, thereby transferring the circuit pattern of the mask onto
a photoresist pattern on the wafer. Then, a film under the
photoresist pattern is etched using the transferred photoresist
pattern as an etching mask so that the circuit pattern is formed in
the film.
[0005] When film patterns are formed by repeatedly performing the
photolithography process, alignment between an upper pattern and a
lower pattern becomes critical.
[0006] Alignment is generally performed by reticle alignment and
wafer alignment in an exposure apparatus during the
photolithography process. Adjustment of the alignment is performed
using correction data obtained by an overlay inspection for a
photoresist pattern after exposure and development steps.
[0007] In the overlay inspection, vertical and horizontal
misalignment, rotation, and orthogonality are measured between an
overlay mark formed on the lower pattern (a main scale) and an
overlay mark formed on the upper pattern (a vernier), thereby
generating correction data to apply in a subsequent exposure
step.
[0008] The overlay mark, generally having a box shape, is formed on
a die cutting line of a wafer (a scribe line).
[0009] However, the conventional overlay mark may not be useful for
an overlay inspection of a real pattern because the conventional
overlay mark has dimensions and shape different from those of the
real pattern in a region where a semiconductor device is
formed.
[0010] The prior art discloses a method for measuring energy
applied in an exposure step and for determining a focusing value by
comparing standard values with measured values in a
photolithography process. The measured values include length
variations in a line and space of a cell matching adopter when the
length variations are measured with an overlay apparatus after the
exposure step is performed. The cell matching adopter has a line
and space identical to those of a real pattern, and is included in
a monitoring mark formed on a scribe line of a wafer during
formation of a mask.
[0011] However, the cell matching adopter may not be useful for an
inspection of the real pattern because the cell matching adopter is
formed around a vernier only, and is identical to the real pattern
in size, but not shape.
SUMMARY OF THE INVENTION
[0012] Therefore, in an effort to solve the problems mentioned
above, it is a feature of an embodiment of the present invention to
provide a method for manufacturing a semiconductor device capable
of measuring an overlay condition of a real pattern by forming a
first mark of an overlay mark identical to a first pattern of the
real pattern and by forming a second mark of the overlay mark
identical to a second pattern of the real pattern.
[0013] It is another feature of an embodiment of the present
invention to provide a semiconductor device for measuring an
overlay condition of a real pattern with an overlay mark including
a first mark identical to a first pattern of the real pattern and a
second mark identical to a second pattern of the real pattern.
[0014] To provide a feature of an embodiment of the present
invention, there is provided a method for forming a semiconductor
device including forming a first pattern for a semiconductor device
in a semiconductor device formation region of a semiconductor
substrate and simultaneously forming the first pattern in a first
mark formation region of the semiconductor substrate; forming a
second pattern for the semiconductor device on a resultant
structure in the semiconductor device formation region of the
semiconductor substrate and simultaneously forming the second
pattern in a second mark formation region of the semiconductor
substrate; and inspecting the first pattern in the first mark
formation region and the second pattern in the second mark
formation region for misalignments.
[0015] In this case, the first mark formation region may be a box
shaped main scale formation region, and the second mark formation
region may be a box shaped vernier formation region. Also, the
first pattern may be an active pattern in a DRAM cell region, and
the second pattern may be a word line pattern in the DRAM cell
region.
[0016] In accordance with a feature of an embodiment of the present
invention, for optical proximity correction (OPC), a scattering bar
may be formed at an edge of a pattern in a mask corresponding to
the first pattern in the first mark formation region, and another
scattering bar may be formed at an edge of a pattern in a mask
corresponding to the second pattern in the second mark formation
region.
[0017] To provide another feature of an embodiment of the present
invention, there is provided a semiconductor device having an
overlay mark, the overlay mark including a first mark formed in a
first mark formation region of a semiconductor substrate and a
first pattern formed in a semiconductor device formation region of
the semiconductor substrate, wherein the first mark and the first
pattern are formed simultaneously by a same process such that the
first mark has a shape identical to a shape of the first pattern,
and a second mark formed in a second mark formation region of the
semiconductor substrate and a second pattern formed in the
semiconductor device formation region of the semiconductor
substrate, wherein the second mark and the second pattern are
formed simultaneously by a same process such that the second mark
has a shape identical to a shape of the second pattern.
[0018] The first pattern may be an active pattern in a DRAM cell
region, and the second pattern may be a word line pattern in the
DRAM cell region
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] These and other features and advantages of the present
invention will become readily apparent from the following detailed
description of the preferred embodiments when considered in
conjunction with the accompanying drawings, in which:
[0020] FIG. 1 illustrates a plan view of a wafer;
[0021] FIG. 2 illustrates a cross-sectional view showing an overlay
mark;
[0022] FIG. 3 illustrates a plan view of the overlay mark of FIG.
2;
[0023] FIGS. 4A and 4B illustrate enlarged views of a first portion
A and a second portion B, respectively, in the overlay mark of FIG.
3, according to an embodiment of the present invention.
[0024] FIG. 5 illustrates a cross-sectional view of a mask of the
overlay mark of FIG. 3 having a scattering bar, according to an
embodiment of the present invention;
[0025] FIG. 6 illustrates a block diagram for showing a control
system of an exposure apparatus according to an embodiment of the
present invention;
[0026] FIG. 7 illustrates a flow chart depicting a method for
manufacturing a semiconductor device according to an embodiment of
the present invention;
[0027] FIG. 8 illustrates a view for explaining a misalignment
measuring site; and
[0028] FIGS. 9A to 9C illustrate examples of misalignment
parameters concerning a wafer and a reticle.
DETAILED DESCRIPTION OF THE INVENTION
[0029] Korean Patent Application No. 2002-47249, filed Aug. 9,
2002, and entitled: "Method For Manufacturing Semiconductor Device
And Semiconductor Device With Overlay Mark," is incorporated by
reference herein in its entirety.
[0030] Hereinafter, preferred embodiments of the present invention
will be described in detail with reference to the accompanying
drawings, in which like reference numerals denote like elements
throughout.
[0031] FIG. 1 illustrates a plan view of a wafer.
[0032] Referring to FIG. 1, a semiconductor wafer 10 is divided
into a plurality of dies 12 by scribe lines 14. Each of the dies 12
is equivalent to a semiconductor device formation region where a
circuit pattern is formed. An alignment mark is formed on each of
the scribe lines 14 for alignment of the wafer 10.
[0033] FIG. 2 illustrates a cross-sectional view of an overlay mark
and FIG. 3 illustrates a plan view of the overlay mark of FIG.
2.
[0034] Referring to FIGS. 2 and 3, an overlay mark 20 includes a
main scale pattern 22 formed on a wafer 10, and a vernier pattern
24 formed over a layer 23 in which the main scale pattern 22 is
positioned. The main scale pattern 22 has a box shape and is
equivalent to an outer alignment mark. Misalignment between the
main scale pattern 22 and the vernier pattern 24 is measured with
an overlay measurement apparatus when the wafer 10 having the
overlay mark 20 is positioned in the overlay measurement apparatus.
The misalignment is measured with the overlay measurement apparatus
by measuring a vertical interval (dy) and a horizontal interval
(dx) between the main scale pattern 22 and the vernier pattern
24.
[0035] FIGS. 4A and 4B illustrate enlarged views of a first portion
A and a second portion B, respectively, in the overlay mark of FIG.
3, according to an embodiment of the present invention.
[0036] Referring to FIGS. 3, 4A and 4B, as examples of an
embodiment of the present invention, the main scale pattern 22 is
an active region pattern 32 in a DRAM cell region, and the vernier
pattern 24 is a word line pattern 34 disposed across the active
region pattern 32.
[0037] FIG. 5 illustrates a cross-sectional view of a mask of the
overlay mark 20 having a scattering bar according to an embodiment
of the present invention.
[0038] Referring to FIG. 5, an exposure mark of the present
invention is formed by transferring a main pattern 42 for an
overlay inspection onto a mask substrate 40 after the main pattern
42, preferably made of chrome, and a subsidiary pitcher (an
assisted bar, a scattering bar, or an intensity leveling bar) 44
are formed on the mask substrate 40.
[0039] In a photolithography process, a pattern of a photomask is
transferred onto a wafer through an optical lens. In this case, an
image transferred onto the wafer may be distorted because an
optical system transmitting the image functions as a low pass
filter. That is, the image has a rounded pattern shape because a
portion of the image where high frequency is applied, i.e., a
corner, is not transmitted, so that when a mask having a
rectangular shape is used, an edge or corner portion of the image
(where high frequency is applied) is also not transmitted. When a
pattern of the mask is large, the image generally has an initial
pattern shape by transmitting relatively many orders of the
frequency, since a basic spatial frequency is low. However, as a
size of a pattern becomes smaller, the spatial frequency becomes
higher, and an image becomes more greatly distorted by reducing the
number of orders of the frequency transmitted.
[0040] By taking distortion of the image into consideration and
changing the shape of a mask accordingly, optical proximity
correction (OPC) is able to produce a final pattern having a
desired shape on a wafer. An optical proximity is generated when
adjacent pitchers are interacted with each other to form a pattern
dependent modification. For example, patterns disposed to have
different proximities of pitches in a layout have different
dimensions after a developing step even though the patterns are
designed to have identical dimensions. Hence, a group of lines in
the pattern that are close to each other may be transmitted
differently than another group of lines in the pattern that are
separated from each other. A measured overlay value may be
distorted when widths of lines in the pattern are not constantly
reproduced.
[0041] According to an embodiment of the present invention, to
precisely transfer an overlay mark formed to have a shape and size
identical to those of a cell pattern onto a wafer, the OPC may be
minimized by adopting a scattering bar on a mark concerning an
overlay mark pattern.
[0042] Referring to FIG. 5, the main pattern 42 of the overlay mark
20 includes a plurality of closed edges 42a and isolated edges 42b.
Thus, to provide a peripheral portion of isolated edges 42b on the
mask with an OPC identical to that of the closed edges 42a,
scattering bars 44 are formed at positions spaced apart from the
isolated edges 42b by an interval identical to an interval between
the closed edges 42a. A width of the scattering bar 44 is no wider
than a minimum width of the main pattern 42, so that the scattering
bar 44 is not transferred onto the wafer 10.
[0043] FIG. 6 illustrates a block diagram of a control system of an
exposure apparatus according to an embodiment of the present
invention.
[0044] Referring to FIG. 6, a photo apparatus 100 includes a
coating processing part 102, an alignment and exposure processing
part 104, and a developing processing part 106.
[0045] The photo apparatus 100 deposits a film to be etched on a
wafer (W), and forms a photoresist pattern on the film to be
etched. Then, the photo apparatus 100 forms a single pattern layer
by a photolithography process in which the film is etched using the
photoresist pattern as an etching mask.
[0046] The steps described above are repeatedly performed with
respect to several films so that desired circuit patterns having
several overlying films are formed on the wafer, thereby allowing
formation of a plurality of integrated circuit chips on a single
wafer. Because the photolithography process has the potential to
greatly effect yield of a semiconductor device manufacturing
process, the photolithography process is crucial to the
semiconductor device manufacturing process.
[0047] The photolithography process usually includes a coating
step, an alignment and exposure step, and a developing step.
[0048] In the coating processing part 102, there are performed: a
pre-baking step for removing moisture from a surface of the wafer
(W) and for improving an adherence between the wafer (W) and a
photoresist coated thereon, a scrubbing step for removing
impurities on the wafer (W) using highly compressed deionized water
and a brush, a spinning step to provide uniform coating, and a soft
baking step for volatilizing a solvent in the photoresist and for
hardening the photoresist.
[0049] In the alignment and exposure part 104, there are performed:
a pre-aligning step for aligning a reticle in accordance with a
reference mark, and for aligning the wafer (W) and the reticle, an
aligning step for fixing a flat zone of the wafer, and an exposure
step for exposing the photoresist after determining an exposure
amount.
[0050] In the developing processing part 106, there are performed:
a post exposure step for removing a standing wave effect, a
developing step for selectively removing a portion of the
photoresist that has been reacted with an UV light, and a hard
baking step for hardening a photoresist pattern on the wafer (W) to
sufficiently maintain the shape of the wafer (W) at a high
temperature.
[0051] FIG. 7 illustrates a flow chart for showing a method for
manufacturing a semiconductor device according to an embodiment of
the present invention.
[0052] Referring to FIGS. 6 and 7, a first pattern (that is, an
active region pattern) is formed in a semiconductor formation
region of a semiconductor substrate and in a main scale formation
region of a scribe line using the above-described photolithography
process (step S202).
[0053] An insulation film and a gate electrode film are deposited
on the resultant thus obtained, and then a photolithography process
is performed with respect to the insulation and the gate electrode
films. That is, a photoresist film is formed on the insulation film
by coating a photoresist in the coating processing part 102, and
exposing the photoresist film with a mask having a vernier pattern
in the exposure processing part 104. Subsequently, a photoresist
pattern is formed by developing the exposed photoresist film in the
developing processing part 106. A word line electrode film is
selectively etched using the photoresist pattern as an etching
mask. As a result, a second pattern having a shape identical to
that of the word line is formed in a vernier formation region and
in the semiconductor device formation region of the semiconductor
substrate (step S204).
[0054] The wafer (W) is inserted into an overlay measuring part
110, which measures an overlay mark that includes the main scale
and the vernier having shapes and sizes identical to those of cell
patterns (step S206).
[0055] As described above, after the photoresist pattern is formed
on the wafer (W), misalignment is measured with the overlay
measuring part 110 to determine whether the measured misalignment
is within a predetermined tolerance.
[0056] FIG. 8 illustrates a view for explaining a misalignment
measuring site.
[0057] Referring to FIGS. 3 and 8, it is impossible for the overlay
measuring part 110 (FIG. 6) to measure the misalignment by
comparing all of the overlying pattern layers. Hence, the
misalignment is measured with respect to a plurality of
misalignment measuring sites (MS) formed on the wafer (W). Each of
the plurality of misalignment measuring sites (MS) is an overlay
mark 20.
[0058] After a site to be measured is selected from within the
misalignment measuring site (MS) formed on the wafer (W), dx/dy is
measured between an outer alignment mark 22 formed on a lower
pattern layer of the selected site and an inner alignment mark 24
formed on an upper pattern layer of the selected site. Regression
analysis is performed concerning data of the measured dx/dy to
extract misalignment parameters as follows:
[0059] The misalignment parameters are divided into parameters
concerning the wafer and parameters concerning a reticle.
[0060] FIGS. 9A, 9B and 9C illustrate examples of misalignment
parameters concerning the wafer and a reticle.
[0061] 1) parameters concerning the wafer:
[0062] offset (OF)--a degree of misalignment of the alignment
pattern in a vertical (Y) direction and in a horizontal (X)
direction (FIG. 9A);
[0063] scaling (SC)--an enlarged degree of the pattern on the
wafers due to warpage of a wafer or wafer stage moving accuracy,
etc., in a vertical (Y) direction and in a horizontal (X) direction
(FIG. 9B);
[0064] rotation (ROT)--a distorted degree of an axis of the
alignment pattern concerning an alignment reference axis (FIG. 9C);
and
[0065] orthogonality (ORT)--a distorted degree between wafer
alignment axes of the wafer.
[0066] 2) parameters concerning a reticle:
[0067] reticle rotation (ROT)--a distorted degree of the axis of
the alignment pattern concerning the alignment reference axis due
to an incorrect set of the reticle (FIG. 9C); and
[0068] reticle reduction (RED)--an enlarged degree of the pattern
on the wafer in a vertical direction (Y) and in a horizontal (X)
direction due to the incorrect set of the reticle (FIG. 9B);
[0069] The alignment and exposure part 104, which may be a stepper,
includes a wafer stage, a lens system, the reticle, and a light
source system.
[0070] When a light generated from the light source system is
applied onto the wafer through a mask pattern of the reticle and
the lens system, the mask pattern of the reticle is reductively
projected onto the wafer. Therefore, the wafer alignment requires
correction of distortions of an X-axis and a Y-axis, distortions of
rotation and orthogonality of the wafer disposed on the wafer
stage, and horizontal distortion of an image projected onto the
wafer. In addition, reticle alignment requires correction for
rotation and reduction of the reticle.
[0071] Thus, the overlay measuring part 110 provides an overlay
correction controller 120 with data including a measurement time,
lot identification data and ten measurement parameters such as
OF-X, OF-Y, SC-X, SC-Y, ORT, W-ORT, RED-X, RED-Y ROT-X and ROT-Y
(step S208).
[0072] The overlay correction controller 120 generates inputting
values using provided correction values, and then provides the
inputting values to the stepper 104, thereby correcting the
misalignment through an overlay correction by the stepper 104 (step
S210).
[0073] Therefore, misalignments of the active region and word line
of the wafer may be reduced by alignment correction through the
above-described overlay measurement process.
[0074] As described above, by forming an overlay mark to have a
shape and size identical to those of a real pattern in a
semiconductor device formation region of a semiconductor substrate,
the present invention may allow an overlay mismatch between the
region where the semiconductor device is formed and the overlay
mark to be prevented, thereby minimizing misalignment of layers in
a semiconductor device.
[0075] Preferred embodiments of the present invention have been
disclosed herein and, although specific terms are employed, they
are used and are to be interpreted in a generic and descriptive
sense only and not for purpose of limitation. Accordingly, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made without departing from the
spirit and scope of the invention as set forth in the following
claims.
* * * * *