U.S. patent application number 10/924996 was filed with the patent office on 2005-02-03 for dc offset cancellation.
Invention is credited to Barak, Ilan, Francos, Amir, Yellin, Daniel.
Application Number | 20050025255 10/924996 |
Document ID | / |
Family ID | 33030227 |
Filed Date | 2005-02-03 |
United States Patent
Application |
20050025255 |
Kind Code |
A1 |
Francos, Amir ; et
al. |
February 3, 2005 |
DC offset cancellation
Abstract
A transmitter has a transmission path with an IQ modulator and a
feedback path with an IQ demodulator. DC offset is determined by
estimating a DC offset of the IQ demodulator, adaptively estimating
a DC offset of the IQ modulator at least partially from the
demodulator DC offset, subtracting the estimated demodulator DC
offset from the feedback path and subtracting the estimated
modulator DC offset from the transmission path.
Inventors: |
Francos, Amir; (Tel Aviv,
IL) ; Barak, Ilan; (Kfar Saba, IL) ; Yellin,
Daniel; (Ra'anana, IL) |
Correspondence
Address: |
EITAN, PEARL, LATZER & COHEN ZEDEK LLP
10 ROCKEFELLER PLAZA, SUITE 1001
NEW YORK
NY
10020
US
|
Family ID: |
33030227 |
Appl. No.: |
10/924996 |
Filed: |
August 25, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10924996 |
Aug 25, 2004 |
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09661127 |
Sep 13, 2000 |
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6801581 |
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Current U.S.
Class: |
375/296 |
Current CPC
Class: |
H04L 25/063 20130101;
H03C 3/40 20130101 |
Class at
Publication: |
375/296 |
International
Class: |
H04K 001/02 |
Claims
We claim:
1. A method of adaptively estimating a DC offset of an IQ
modulator, the method comprising: providing a predetermined signal
to an input of said IQ modulator and transmitting said signal;
estimating a DC offset of an IQ demodulator from a received version
of said signal; generating a difference signal between said
received signal and said estimated DC offset of said IQ
demodulator; and subtracting a modified rotated version of said
difference signal from a previous value of said DC offset of said
IQ modulator.
2. A method according to claim 1, further comprising: estimating a
phase rotation of a transmission path of a transmitter and a
feedback path of said transmitter; and modifying said difference
signal with said phase rotation.
3. A method according to claim 1, wherein said estimating said DC
offset of said IQ demodulator is undertaken during non-transmission
slots.
4. A transmitter comprising: a transmission path having an IQ
modulator; a feedback path having an IQ demodulator; a demodulator
DC offset estimator to average a received signal along said
feedback path and to estimate a DC offset of said IQ demodulator;
and an adaptive modulator DC offset estimator to estimate a DC
offset of said IQ modulator at least partially from said DC offset
of said IQ demodulator, wherein said adaptive modulator DC offset
estimator is to generate a difference signal between said received
signal and said DC offset of said IQ demodulator and to subtract a
modified rotated version of said difference signal from a previous
value of said DC offset of said IQ modulator.
5. A transmitter according to claim 4, wherein said demodulator DC
offset estimator and said adaptive modulator DC offset estimator
are to operate during non-transmission slots.
6. A transmitter according to claim 5, wherein said
non-transmission slots are non-transmission slots of regular
transmission.
7. A transmitter according to claim 4, wherein said adaptive
modulator DC offset estimator is to modify said difference signal
with a phase rotation of said transmission and feedback paths.
8. An integrated circuit having a transmitter, the transmitter
comprising: a transmission path having an IQ modulator; a feedback
path having an IQ demodulator; a demodulator DC offset estimator to
average a received signal along said feedback path and to estimate
a DC offset of said IQ demodulator; an adaptive modulator DC offset
estimator to estimate a DC offset of said IQ modulator by
generating a difference signal between said received signal and
said demodulator DC offset and subtracting a modified rotated
version of said difference signal from a previous value of said DC
offset of said IQ modulator.
9. An integrated circuit according to claim 8, wherein said
demodulator DC offset estimator and said adaptive modulator DC
offset estimator are to operate during non-transmission slots.
10. An integrated circuit according to claim 9, wherein said
non-transmission slots are non-transmission slots of regular
transmission.
11. An integrated circuit according to claim 8, wherein said
adaptive modulator DC offset estimator is to modify said difference
signal with a phase rotation of said transmission and feedback
paths.
Description
CROSS REFERENCE TOP RELATED APPLICATIONS
[0001] The present invention is a continuation application of U.S.
patent application Ser. No. 09/661,127, filed Sep. 13, 2000, which
application is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention relates to offset cancellation in
general and to DC offset cancellation in mobile communication
systems in particular.
BACKGROUND OF THE INVENTION
[0003] Many transmitters transmit digital information values that
are generated in base band. The base band digital values are
modulated onto a carrier high frequency signal and the combined
signal is amplified before its transmission. The base band values
may be complex values having real and imaginary components which
are traditionally referred to as I and Q components, respectively.
In the modulation of the base band signal and amplification of the
modulation signal, inaccuracies are introduced. These inaccuracies
may cause the transmitter to interfere with signals on carrier
frequencies allocated to other transmitters and therefore should be
at least partially canceled by the transmitter.
[0004] One source of inaccuracy is the IQ modulator and
demodulator, which both suffer from a distortion mechanism called
"local oscillator carrier feedthrough" and "DC offset". For
example, the output of the demodulator can be modeled as:
S(t)=I(t)cos(.omega.t)-Q(t)sin(.omega.t)+LO(t) Equation 1
[0005] where:
LO(t)=A cos(.omega.t+.phi.) Equation 2
[0006] The DC offset mechanism is generally due to LO(t), which is
caused due to leakage of the signal of a local oscillator (used for
carrier modulation) into the demodulator output. The same problem
occurs at the modulator side.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present invention will be understood and appreciated
more fully from the following detailed description taken in
conjunction with the appended drawings in which:
[0008] FIG. 1 is a block diagram illustration of transmission and
feedback paths of a mobile communication unit or a base station, in
accordance with an embodiment of the present invention; and
[0009] FIG. 2 is a block diagram illustration of an alternative
embodiment of the present invention.
[0010] It will be appreciated that for simplicity and clarity of
illustration, elements shown in the figures have not necessarily
been drawn to scale. For example, the dimensions of some of the
elements may be exaggerated relative to other elements for clarity.
Further, where considered appropriate, reference numerals may be
repeated among the figures to indicate corresponding or analogous
elements.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0011] In the following detailed description, numerous specific
details are set forth in order to provide a thorough understanding
of the invention. However, it will be understood by those skilled
in the art that the present invention may be practiced without
these specific details. In other instances, well-known methods,
procedures, components and circuits have not been described in
detail so as not to obscure the present invention.
[0012] Some portions of the detailed description which follow are
presented in terms of algorithms and symbolic representations of
operations on data bits or binary digital signals within a computer
memory. These algorithmic descriptions and representations may be
the techniques used by those skilled in the data processing arts to
convey the substance of their work to others skilled in the
art.
[0013] An algorithm is here, and generally, considered to be a
self-consistent sequence of acts or operations leading to a desired
result. These include physical manipulations of physical
quantities. Usually, though not necessarily, these quantities take
the form of electrical or magnetic signals capable of being stored,
transferred, combined, compared, and otherwise manipulated. It has
proven convenient at times, principally for reasons of common
usage, to refer to these signals as bits, values, elements,
symbols, characters, terms, numbers or the like. It should be
understood, however, that all of these and similar terms are to be
associated with the appropriate physical quantities and are merely
convenient labels applied to these quantities.
[0014] Unless specifically stated otherwise, as apparent from the
following discussions, it is appreciated that throughout the
specification discussions utilizing terms such as "processing,"
"computing," "calculating," "determining," or the like, refer to
the action and/or processes of a computer or computing system, or
similar electronic computing device, that manipulate and/or
transform data represented as physical, such as electronic,
quantities within the computing system's registers and/or memories
into other data similarly represented as physical quantities within
the computing system's memories, registers or other such
information storage, transmission or display devices.
[0015] Embodiments of the present invention may include apparatuses
for performing the operations herein. This apparatus may be
specially constructed for the desired purposes, or it may comprise
a general purpose computer selectively activated or reconfigured by
a computer program stored in the computer. Such a computer program
may be stored in a computer readable storage medium, such as, but
is not limited to, any type of disk including floppy disks, optical
disks, CD-ROMs, magnetic-optical disks, read-only memories (ROMs),
random access memories (RAMs), electrically programmable read-only
memories (EPROMs), electrically erasable and programmable read only
memories (EEPROMs), magnetic or optical cards, or any other type of
media suitable for storing electronic instructions, and capable of
being coupled to a computer system bus.
[0016] Reference is now made to FIG. 1, which generally illustrates
elements used in transmission for both mobile communication units
and the base stations with which they communicate. While FIG. 1
presents certain elements, it will be appreciated that other mobile
units and base stations may or may not include all of the elements
shown in FIG. 1. FIG. 1 shows a transmission path 10, a feedback
path 12 and a DC offset estimator 16. The transmission path 10
generally comprises some or all of the following elements: a
baseband modulator 20, a digital to analog (D/A) converter 24, an
IQ modulator 28 and a power amplifier 30. Baseband modulator 20
converts an incoming bit stream into a baseband signal having I and
Q components. D/A converter 24 converts the shaped digital signal
into an analog signal. IQ modulator 28 modulates the complex
baseband signal into a radio frequency (RF) signal and power
amplifier 30 transmits the RF signal.
[0017] Feedback path 12 comprises some or all of the following
elements: an attenuator 32, an IQ demodulator 34 and an analog to
digital (A/D) converter 40. Attenuator 32 receives the transmitted
radio frequency and IQ demodulator 34 converts the radio frequency
signal into a baseband one. Analog to digital converter 40 converts
the signal into a digital one.
[0018] DC offset estimator 16 generally determines the DC offset
due to IQ modulator 28 and IQ demodulator 34 from data from
feedback path 12. DC offset estimator 16 typically comprises a
demodulator DC offset estimator 50 and an adaptive modulator DC
offset estimator 52. Through a logical switch 54 in feedback path
12, demodulator estimator 50 may receive the output V.sub.f of
analog to digital converter 40 at predefined times. Demodulator
estimator 50 may estimate the DC offset due to IQ demodulator 34
and the result, a signal labeled DC_DEMOD_EST, may be provided to a
summer 56 in feedback path 12. When logical switch 54 connects
analog to digital converter 40 to summer 56, summer 56 may subtract
the estimated DC offset, DC.sub.--DEMOD_EST, from the output of
analog to digital converter 40, thereby providing a signal from
which most, if not all, of the DC offset due to IQ demodulator 34
has been removed.
[0019] Typically, logical switch 54 provides its signal to
demodulator estimator 50 during "non-transmission slots" (i.e.
periods when no signal is being transmitted from or to the unit).
At the same time, a "zero" signal, or one with a known sequence,
may be injected to the input of IQ demodulator 34. This may be
implemented by shutting down power amplifier 30 which results in an
input to IQ demodulator 34 of generally zero. Thus, if there is any
signal measured after analog to digital converter 40, it is due to
the DC offset of IQ demodulator 34.
[0020] The output of IQ demodulator 34 may be measured for a set
number of consecutive symbols NO_SYMBOLS. The two DC offset values
DC_I_DEMOD_EST and DC_QDEMOD EST of IQ demodulator 34 may be
estimated as: 1 DC_I _DEMOD _EST = 1 NO_SYMBOLS i = 1 NO_SYMBOLS I
~ Equation 3 DC_Q _DEMOD _EST = 1 NO_SYMBOLS i = 1 NO_SYMBOLS Q ~ ,
Equation 4
[0021] where , {tilde over (Q)} are the real and imaginary parts,
respectively, of the signal V.sub.f produced by analog to digital
converter 40 and NO_SYMBOLS is the number of symbols used for
averaging. In one embodiment, NO_SYMBOLS=5.
[0022] These two values may be provided to summer 56 to generally
cancel the DC offset of IQ demodulator 34.
[0023] Once the demodulator DC offset has been estimated, the
modulator DC offset may be calculated by operating both
transmission path 10 and feedback path 12. Transmission path 10
also includes a summer 60, before FIR filter 22, which may subtract
the modulator DC offset, DC_MOD_EST, from the predistorted signal
produced by multipliers 46. To determine the modulator DC offset,
PD LUT 42 is bypassed, typically by changing multipliers 46 to
unity, and a zero input signal is provided (typically during a
non-transmission slot) to baseband modulator 20. In addition,
adaptive modulator estimator 52 may assign initial values,
typically obtained from a factory calibration, to summer 60. The
factory calibrated values may be far away from the true (and
unknown) values due to thermal and frequency changes.
[0024] The resultant signal is transmitted by power amplifier 30
and may be received by feedback path 12, operating with logical
switch 54 connecting analog to digital converter 40 to summer 56.
The result is that summer 56 produces two signals e.sub.I and
e.sub.Q which are the feedback path output with the DC offset from
IQ demodulator generally removed. During non-transmission slots,
the two signals may be given mathematically as:
e.sub.I=-DC.sub.--I_DEMOD_EST, Equation 5
e.sub.Q={tilde over (Q)}-DC.sub.--Q_DEMOD_EST, Equation 6
[0025] where , {tilde over (Q)} are defined hereinabove.
[0026] When determining the DC offset of IQ modulator 28, a logical
switch 58 may provide the two signals e.sub.I and e.sub.Q to
adaptive modulator estimator 52, which then operates to minimize
the signals e.sub.I.sup.2 and e.sub.Q.sup.2.
[0027] At the end of each symbol period, adaptive modulator
estimator 52 may compute:
DC.sub.--I_MOD.sub.--C.sub.new=DC.sub.--I_MOD.sub.--C.sub.old-.mu..sub.IRe-
{e.sub.I.sup.rot}, Equation 7
[0028] for the I channel and
DC.sub.--Q_MOD.sub.--C.sub.new=DC.sub.--Q_MOD.sub.--C.sub.old-.mu..sub.QIm-
{e.sub.Q.sup.rot}, Equation 8
[0029] for the Q channel, where .mu..sub.I, .mu..sub.Q, are the
step sizes which control the rate of adaptation,
0.ltoreq..mu..sub.I.ltoreq.1, 0.ltoreq..mu..sub.Q.ltoreq.1 and
e.sub.I.sup.rot and e.sub.Q.sup.rot are rotated errors given
hereinbelow by Equation 9. DC_I_MOD_C.sub.old and
DC_Q_MOD_C.sub.old are the previous values of offset estimation and
initially may be the factory calibrated values.
[0030] Alternatively to using the steepest descent iteration method
(implemented in Equation 7 and Equation 8), other iteration methods
as are known from optimization theory, such as the conjugate
gradient equation and the quasi-Newton equation, may be used to
minimize the signals e.sub.I.sup.2 and e.sub.Q.sup.2. In some
embodiments of the invention, the selected iteration method is
chosen as a tradeoff between the processing power of the
transmitter and the required convergence speed of the output of
adaptive estimator 52. If fast convergence is required and the
transmitter has a relatively high processing power level, a fast
convergence method that requires dense computation (e. g., the
quasi-Newton method) may be used. If, however, low processing power
utilization is more important than fast convergence, simpler
methods, such as the steepest descent method, may be used.
[0031] There is often a phase rotation {circumflex over
(.phi.)}.sub.path along the path from the output of digital to
analog converter 24 in transmission path 10 to the input to analog
to digital converter 40 in feedback path 12. This phase rotation
can be estimated as described hereinbelow with respect to Equation
10 and then used to rotate the errors e.sub.I and e.sub.Q according
to:
e.sub.I.sup.rot=e.sub.Ie.sup.-j{circumflex over
(.phi.)}.sup..sub.path,
e.sub.Q.sup.rot=e.sub.Qe.sup.-j{circumflex over (100
)}.sup..sub.path, Equation 9
[0032] The phase {circumflex over (100 )}.sub.path is measured in
the first transmission slot when data is transmitted. The angle
.theta..sub.inp of the baseband input signal is measured, per
symbol, as is the angle .theta..sub.out of each symbol of the
signal V.sub.f after analog to digital converter 40. The angle is
defined as the angle in the complex plane of value +j{tilde over
(Q)}.
[0033] The phase {circumflex over (.phi.)}.sub.path is the average
value of the difference in the angles. Thus:
{circumflex over
(.phi.)}.sub.path=avg(.theta..sub.out-.theta..sub.inp) Equation
10
[0034] Dunng regular operation, logical switches 54 and 58 are
typically closed and the previously estimated DC offset values may
be utilized in summers 56 and 60. Thus, feedback path 12 produces
signals with minimal, if any, demodulator DC offset and the
transmitted signal may have the modulator DC offset removed.
[0035] If desired, and particularly during long transmission
periods, the DC offset estimators 50 and 52 can be operated again.
To do so, the data of the next non-transmitted slot is used. The DC
offset estimators 50 and 52 are then operated on this data.
[0036] Reference is now made to FIG. 2, which illustrates a further
embodiment of the invention implemented in a transmitter having a
predistorter. Elements, which are similar to those of FIG. 1, have
similar reference numerals.
[0037] FIG. 2 shows transmission path 10, feedback path 12, a
predistorter 14 and DC offset estimator 16. The transmission path
10 generally comprises some or all of the following elements:
baseband modulator 20, a finite impulse response (FIR) filter 22,
digital to analog (D/A) converter 24, an analog filter 26, IQ
modulator 28 and power amplifier 30. FIR filter 22 shapes the
baseband signal as desired. Analog filter 26 filters the analog
signal as necessary.
[0038] Feedback path 12 comprises some or all of the following
elements: attenuator 32, IQ demodulator 34, a filter 36 and analog
to digital (A/D) converter 40. Filter 36 limits any noise to the
bandwidth of the demodulated signal.
[0039] Predistorter 14 comprises a predistorter (PD) lookup table
(LUT) 42 and a PD 25 LUT trainer 44. Pre-distorter 14 compensates
for the non-linearity of power amplifier 30 and changes the signals
entering power amplifier 30 such that the transmitted signals have
substantially linear amplification (rather than the non-linear
amplification, which occurs without the predistortion). Since the
distortion changes due to temperature, aging and other
characteristics of power amplifier 30, the predistortion values are
updated by PD LUT trainer 44, based on feedback received from the
output of power amplifier 30.
[0040] During regular transmission, PD LUT 42 predistorts the
signal from baseband modulator 20 in order to compensate for the
distortion produced by power amplifier 30. To do so, the output of
PD LUT 42 is multiplied with the output of baseband modulator by
multipliers 46 in transmission path 10. PD LUT trainer 44 regularly
updates the values of PD LUT 42 based on data received along
feedback path 12.
[0041] During regular operation, logical switches 54 and 58 are
typically closed and any previously estimated DC offset values may
be utilized in summers 56 and 60. Thus, PD LUT trainer 44 may
receive signals with minimal, if any, demodulator DC offset and the
transmitted signal may be both predistorted and may have the
modulator DC offset removed.
[0042] DC offset estimator 16 operates as described hereinabove.
Specifically, it operates during non-transmission slots and PD LUT
42 is disabled by indicating to multipliers 46 to pass the output
of baseband modulator 20 rather than multiplying it by the output
of PD LUT 42.
[0043] The methods and apparatus disclosed herein have been
described without reference to specific hardware or software.
Rather, the methods and apparatus have been described in a manner
sufficient to enable persons of ordinary skill in the art to
readily adapt commercially available hardware and software as may
be needed to reduce any of the embodiments of the present invention
to practice without undue experimentation and using conventional
techniques.
[0044] It will be appreciated by persons skilled in the art that
the present invention is not limited by what has been particularly
shown and described herein above. Rather the scope of the invention
is defined by the claims that follow:
* * * * *