U.S. patent application number 10/931365 was filed with the patent office on 2005-02-03 for pr2o3-based la-oxide gate dielectrics.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Ahn, Kie Y., Forbes, Leonard.
Application Number | 20050023594 10/931365 |
Document ID | / |
Family ID | 29710030 |
Filed Date | 2005-02-03 |
United States Patent
Application |
20050023594 |
Kind Code |
A1 |
Ahn, Kie Y. ; et
al. |
February 3, 2005 |
Pr2O3-based la-oxide gate dielectrics
Abstract
A dielectric film having a layer of Pr.sub.2O.sub.3 and a layer
of another lanthanide oxide, and a method of fabricating such a
dielectric film produce a reliable gate dielectric with a
equivalent oxide thickness thinner than attainable using SiO.sub.2.
A gate dielectric is formed as a nanolaminate of Pr.sub.2O.sub.3
and a lanthanide oxide selected from the group consisting of
Nd.sub.2O.sub.3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and
Dy.sub.2O.sub.3 by electron beam evaporation. These gate
dielectrics having a lanthanide oxide nanolaminate are
thermodynamically stable such that the nanolaminate forming the
gate dielectric will have minimal reactions with a silicon
substrate or other structures during processing.
Inventors: |
Ahn, Kie Y.; (Chappaqua,
NY) ; Forbes, Leonard; (Corvallis, OR) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH, P.A.
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
29710030 |
Appl. No.: |
10/931365 |
Filed: |
August 31, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10931365 |
Aug 31, 2004 |
|
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10163686 |
Jun 5, 2002 |
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Current U.S.
Class: |
257/314 ;
257/288; 257/411; 257/E21.274; 257/E29.255 |
Current CPC
Class: |
H01L 21/02266 20130101;
H01L 21/31612 20130101; H01L 21/022 20130101; H01L 29/78 20130101;
H01L 2924/0002 20130101; H01L 21/02304 20130101; H01L 21/02192
20130101; H01L 21/28185 20130101; H01L 21/31604 20130101; H01L
29/513 20130101; C23C 14/30 20130101; H01L 2924/0002 20130101; C23C
14/08 20130101; H01L 29/40114 20190801; H01L 21/28194 20130101;
H01L 2924/00 20130101; H01L 29/517 20130101 |
Class at
Publication: |
257/314 ;
257/411; 257/288 |
International
Class: |
H01L 029/76; H01L
031/062; H01L 021/3205; H01L 029/788 |
Claims
What is claimed is:
1. An electronic device comprising: a substrate; and a dielectric
layer, the dielectric layer including: a layer of Pr.sub.2O.sub.3;
and a layer of another lanthanide oxide disposed on the layer of
Pr.sub.2O.sub.3.
2. The electronic device of claim 1, wherein the layer of
Pr.sub.2O.sub.3 and the layer of another lanthanide oxide include a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
3. The electronic device of claim 1, wherein the layer of another
lanthanide oxide includes a layer of a lanthanide oxide selected
from the group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
4. The electronic device of claim 3, wherein the dielectric layer
has an effective dielectric constant ranging from about 11 to about
15.
5. The electronic device of claim 1, wherein the dielectric layer
has an effective dielectric constant ranging from a dielectric
constant of Pr.sub.2O.sub.3 to a dielectric constant of the other
lanthanide oxide.
6. The electronic device of claim 1, wherein the dielectric layer
further includes one or more additional layers of a lanthanide
oxide, each of the additional layers of lanthanide oxide selected
from a group consisting of Pr.sub.2O.sub.3, Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
7. The electronic device of claim 6, wherein the dielectric layer
has an equivalent oxide thickness less than or equal to about 14
.ANG..
8. The electronic device of claim 1, wherein the dielectric layer
is disposed in a transistor.
9. The electronic device of claim 1, wherein the dielectric layer
is disposed in a memory.
10. The electronic device of claim 1, wherein the electronic device
is configured in an electronic system.
11. A transistor comprising: a body region on a substrate between a
first and a second source/drain regions; a film containing
Pr.sub.2O.sub.3 and another lanthanide oxide on the body region
between the first and second source/drain regions; and a gate
coupled to the film; the film being formed by a method including:
forming a layer of Pr.sub.2O.sub.3 onto the body region; and
forming a layer of another lanthanide oxide onto the layer of
Pr.sub.2O.sub.3.
12. The transistor of claim 11, wherein the film includes a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
13. The transistor of claim 11, wherein the layer of another
lanthanide oxide includes a layer of a lanthanide oxide selected
from the group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
14. The transistor of claim 13, wherein the film has an effective
dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
15. The transistor of claim 11, wherein forming a layer of
Pr.sub.2O.sub.3 and forming a layer of another lanthanide oxide
includes forming both layers by electron beam evaporation.
16. A transistor comprising: a body region on a substrate between a
first and a second source/drain regions; a film containing a layer
of Pr.sub.2O.sub.3 and a layer of another lanthanide oxide on the
body region between the first and second source/drain regions; and
a gate coupled to the film.
17. The transistor of claim 16, wherein the layer of
Pr.sub.2O.sub.3 and the layer of the other lanthanide oxide include
a nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide
oxide.
18. The transistor of claim 16, wherein the layer of another
lanthanide oxide includes a layer of a lanthanide oxide selected
from the group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
19. The transistor of claim 18, wherein the film has an effective
dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
20. The transistor of claim 18, wherein the film further includes
one or more additional layers of a lanthanide oxide, each of the
additional layers of a lanthanide oxide selected from a group
consisting of Pr.sub.2O.sub.3, Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
21. The transistor of claim 16, wherein the dielectric layer has an
effective dielectric constant ranging from about 11 to about
15.
22. The transistor of claim 16, wherein the dielectric layer has an
equivalent oxide thickness less than or equal to about 14
.ANG..
23. A transistor comprising: a body region on a substrate between a
first and a second source/drain regions; a gate dielectric disposed
on the body region; a floating gate disposed on the gate
dielectric; a control gate; and a floating gate dielectric
interposed between the floating gate and the control gate, wherein
at least one of the gate dielectric and the floating gate
dielectric includes a film containing Pr.sub.2O.sub.3 and another
lanthanide oxide; the film being formed by a method including:
forming a layer of Pr.sub.2O.sub.3; and forming a layer of another
lanthanide oxide onto the layer of Pr.sub.2O.sub.3.
24. The transistor of claim 23, wherein the film is configured as
the gate dielectric.
25. The transistor of claim 23, wherein the film is configured as
the floating gate dielectric.
26. The transistor of claim 23, wherein the film includes a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
27. The transistor of claim 23, wherein the layer of another
lanthanide oxide includes a layer of a lanthanide oxide selected
from the group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
28. The transistor of claim 23, wherein forming a layer of
Pr.sub.2O.sub.3 and forming a layer of another lanthanide oxide
includes forming both layers by electron beam evaporation.
29. A transistor comprising: a body region on a substrate between a
first and a second source/drain regions; a gate dielectric disposed
on the body region; a floating gate disposed on the gate
dielectric; a control gate; and a floating gate dielectric
interposed between the floating gate and the control gate, wherein
at least one of the gate dielectric and the floating gate
dielectric includes a film containing Pr.sub.2O.sub.3 and another
lanthanide oxide.
30. The transistor of claim 29, wherein the film is configured as
the gate dielectric.
31. The transistor of claim 29, wherein the film is configured as
the floating gate dielectric.
32. The transistor of claim 29, wherein the layer of
Pr.sub.2O.sub.3 and the layer of the other lanthanide oxide include
a nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide
oxide.
33. The transistor of claim 29, wherein the layer of another
lanthanide oxide includes a layer of a lanthanide oxide selected
from the group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
34. The transistor of claim 33, wherein the film further includes
one or more additional layers of a lanthanide oxide, each of the
additional layers of a lanthanide oxide selected from a group
consisting of Pr.sub.2O.sub.3, Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
35. A memory having a memory array comprising: a number of access
transistors, each access transistor including a gate coupled to a
film containing Pr.sub.2O.sub.3 and another lanthanide oxide, the
film formed on a body region on a substrate between a first and a
second source/drain regions; a number of word lines coupled to a
number of the gates of the number of access transistors; a number
of source lines coupled to a number of the first source/drain
regions of the number of access transistors; and a number of bit
lines coupled to a number of the second source/drain regions of the
number of access transistors; the film being formed by a method
including: forming a layer of Pr.sub.2O.sub.3 onto the body region;
and forming a layer of another lanthanide oxide onto the layer of
Pr.sub.2O.sub.3.
36. The memory of claim 35, wherein the film includes a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
37. The memory of claim 35, wherein the layer of another lanthanide
oxide includes a layer of a lanthanide oxide selected from the
group consisting of Nd2O3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and
Dy.sub.2O.sub.3.
38. The memory of claim 37, wherein the film has an effective
dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
39. The memory of claim 35, wherein forming a layer of
Pr.sub.2O.sub.3 and forming a layer of another lanthanide oxide
includes forming both layers by electron beam evaporation.
40. A memory having a memory array comprising: a number of
transistors, each transistor including a gate coupled to a film
containing a layer of Pr.sub.2O.sub.3 and a layer of another
lanthanide oxide, the film disposed above a body region on a
substrate between a first and a second source/drain regions; a
number of word lines coupled to a number of the gates of the number
of transistors; a number of source lines coupled to a number of the
first source/drain regions of the number of transistors; and a
number of bit lines coupled to a number of the second source/drain
regions of the number of transistors.
41. The memory of claim 40, wherein the film is configured as a
floating gate dielectric and the gate is configured as a control
gate.
42. The memory of claim 40, wherein the film is configured as a
gate dielectric and the gate is configured as a control gate.
43. The memory of claim 40, wherein the layer of Pr.sub.2O.sub.3
and the layer of the other lanthanide oxide include a nanolaminate
of Pr.sub.2O.sub.3 and the other lanthanide oxide.
44. The memory of claim 40, wherein the layer of another lanthanide
oxide includes a layer of a lanthanide oxide selected from the
group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
45. The memory of claim 44, wherein the film has an effective
dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
46. The memory of claim 40, wherein the dielectric layer has an
effective dielectric constant ranging from about 11 to about
15.
47. The memory of claim 40, wherein the dielectric layer has an
equivalent oxide thickness less than or equal to about 14
.ANG..
48. The memory of claim 40, the film further includes one or more
additional layers of a lanthanide oxide, each of the additional
layers of a lanthanide oxide selected from a group consisting of
Pr.sub.2O.sub.3, Nd.sub.2O.sub.3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3,
and Dy.sub.2O.sub.3.
49. An electronic system comprising: a processor; a memory having a
memory array, the memory array including: a number of access
transistors, each access transistors having a gate coupled to a
film containing Pr.sub.2O.sub.3 and another lanthanide oxide, the
film located on a body region on a substrate between a first and a
second source/drain regions; a number of word lines coupled to a
number of the gates of the number of access transistors; a number
of source lines coupled to a number of the first source/drain
regions of the number of access transistors; a number of bit lines
coupled to a number of the second source/drain regions of the
number of access transistors; and a system bus that couples the
processor to the memory; the film being formed by a method
including: forming a layer of Pr.sub.2O.sub.3 onto the body region;
and forming a layer of another lanthanide oxide onto the layer of
Pr.sub.2O.sub.3.
50. The electronic system of claim 49, wherein the film includes a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
51. The electronic system of claim 49, wherein forming a layer of
another lanthanide oxide includes forming a layer of a lanthanide
oxide selected from the group consisting of Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
52. The electronic system of claim 51, wherein the film has an
effective dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
53. The electronic system of claim 49, wherein forming a layer of
Pr.sub.2O.sub.3 and forming a layer of another lanthanide oxide
includes forming both layers by electron beam evaporation.
54. An electronic system comprising: a processor; and a memory
having a memory array, the memory array including: a number of
transistors, each transistors having a gate coupled to a film
containing a layer of Pr.sub.2O.sub.3 and a layer of another
lanthanide oxide, the film disposed above a body region on a
substrate between a first and a second source/drain regions; a
number of word lines coupled to a number of the gates of the number
of transistors; a number of source lines coupled to a number of the
first source/drain regions of the number of transistors; a number
of bit lines coupled to a number of the second source/drain regions
of the number of transistors; and a system bus that couples the
processor to the memory.
55. The electronic system of claim 54, wherein the film is
configured as a floating gate dielectric and the gate is configured
as a control gate.
56. The electronic system of claim 54, wherein the film is
configured as a gate dielectric and the gate is configured as a
control gate.
57. The electronic system of claim 54, wherein the film includes a
nanolaminate of Pr.sub.2O.sub.3 and the other lanthanide oxide.
58. The electronic system of claim 54, wherein forming a layer of
another lanthanide oxide includes forming a layer of a lanthanide
oxide selected from the group consisting of Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
59. The electronic system of claim 58, wherein the film has an
effective dielectric constant ranging from a dielectric constant of
Pr.sub.2O.sub.3 to a dielectric constant of the selected lanthanide
oxide.
60. The electronic system of claim 58, wherein the film further
includes one or more additional layers of a lanthanide oxide, each
of the additional layers of a lanthanide oxide selected from a
group consisting of Pr.sub.2O.sub.3, Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3.
61. The electronic system of claim 54, wherein the dielectric layer
has an effective dielectric constant ranging from about 11 to about
15.
62. The electronic system of claim 54, wherein the dielectric layer
has an equivalent oxide thickness less than or equal to about 14
.ANG..
Description
RELATED APPLICATIONS
[0001] This application is a divisional under 37 C.F.R. 1.53(b) of
U.S. Ser. No. 10/163,686 filed on Jun. 5, 2002, which application
is incorporated herein by reference.
[0002] This application is related to the following, co-pending,
commonly assigned applications, incorporated herein by reference:
U.S. application Ser. No. 10/027,315 filed Dec. 20, 2001, entitled:
"Low-Temperature Grown High-Quality Ultra-Thin Praseodymium Gate
Dielectrics."
FIELD OF THE INVENTION
[0003] The invention relates to semiconductor devices and device
fabrication. Specifically, the invention relates to gate dielectric
layers of transistor devices and their method of fabrication.
BACKGROUND OF THE INVENTION
[0004] The semiconductor device industry has a market driven need
to improve speed performance, improve its low static (off-state)
power requirements, and adapt to a wide range of power supply and
output voltage requirements for it silicon based microelectronic
products. In particular, in the fabrication of transistors, there
is continuous pressure to reduce the size of devices such as
transistors. The ultimate goal is to fabricate increasingly smaller
and more reliable integrated circuits (ICs) for use in products
such as processor chips, mobile telephones, or memory devices such
as DRAMs. The smaller devices are frequently powered by batteries,
where there is also pressure to reduce the size of the batteries,
and to extend the time between battery charges. This forces the
industry to not only design smaller transistors, but to design them
to operate reliably with lower power supplies.
[0005] Currently, the semiconductor industry relies on the ability
to reduce or scale the dimensions of its basic devices, primarily,
the silicon based metal-oxide-semiconductor field effect transistor
(MOSFET). A common configuration of such a transistor is shown in
FIG. 1. While the following discussion uses FIG. 1 to illustrate a
transistor from the prior art, one skilled in the art will
recognize that the present invention could be incorporated into the
transistor shown in FIG. 1 to form a novel transistor according to
the invention. The transistor 100 is fabricated in a substrate 110
that is typically silicon, but could be fabricated from other
semiconductor materials as well. The transistor 100 has a first
source/drain region 120 and a second source/drain region 130. A
body region 132 is located between the first source/drain region
and the second source/drain region, where the body region 132
defines a channel of the transistor with a channel length 134. A
gate dielectric, or gate oxide 140 is located on the body region
132 with a gate 150 located over the gate dielectric. Although the
gate dielectric can be formed from materials other than oxides, the
gate dielectric is typically an oxide, and is commonly referred to
as a gate oxide. The gate may be fabricated from polycrystalline
silicon (polysilicon), or other conducting materials such as metal
may be used.
[0006] In fabricating transistors to be smaller in size and
reliably operating on lower power supplies, one important design
criteria is the gate dielectric 140. The mainstay for forming the
gate dielectric has been silicon dioxide, SiO.sub.2. A thermally
grown amorphous SiO.sub.2 layer provides an electrically and
thermodynamically stable material, where the interface of the
SiO.sub.2 layer with underlying Si provides a high quality
interface as well as superior electrical isolation properties. In
typical processing, use of SiO.sub.2 on Si has provided defect
charge densities on the order of 10.sup.10/cm.sup.2, midgap
interface state densities of approximately 10.sup.10/cm.sup.2 eV,
and breakdown voltages in the range of 15 MV/cm. With such
qualities, there would be no apparent need to use a material other
than SiO.sub.2, but increased scaling and other requirements for
gate dielectrics create the need to find other dielectric materials
to be used for a gate dielectric.
[0007] What is needed is an alternate dielectric material for
forming a gate dielectric that has a high dielectric constant
relative to SiO.sub.2, and is thermodynamically stable with respect
to silicon such that forming the dielectric on a silicon layer will
not result in SiO.sub.2 formation, or diffusion of material, such
as dopants, into the gate dielectric from the underlying silicon
layer.
SUMMARY OF THE INVENTION
[0008] A solution to the problems as discussed above is addressed
in embodiments according to the teachings of the present invention.
In one embodiment, a method of forming a gate dielectric includes
forming a layer of Pr.sub.2O.sub.3 on a substrate and forming a
layer of another lanthanide oxide onto the layer of
Pr.sub.2O.sub.3. This second layer is formed of a lanthanide oxide
selected from the group consisting of Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3. Further, the
layer of Pr.sub.2O.sub.3 and the layer of the lanthanide oxide can
be formed as a nanolaminate. Advantageously, a gate dielectric
formed as a combination of layers of Pr.sub.2O.sub.3 and another
lanthanide oxide has a larger dielectric constant than silicon
dioxide, a relatively small leakage current, and good stability
with respect to a silicon based substrate. Embodiments according to
the teachings of the present invention include forming transistors,
memory devices, and electronic systems.
[0009] Other embodiments include structures for transistors, memory
devices, and electronic systems with dielectric gates of layers of
Pr.sub.2O.sub.3 and another lanthanide oxide. Such dielectric gates
provide a significantly thinner equivalent oxide thickness compared
with a silicon oxide gate having the same physical thickness.
Alternatively, such dielectric gates provide a significantly
thicker physical thickness than a silicon oxide gate having the
same equivalent oxide thickness.
[0010] These and other embodiments, aspects, advantages, and
features of the present invention will be set forth in part in the
description which follows, and in part will become apparent to
those skilled in the art by reference to the following description
of the invention and referenced drawings or by practice of the
invention. The aspects, advantages, and features of the invention
are realized and attained by means of the instrumentalities,
procedures, and combinations particularly pointed out in the
appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 depicts a common configuration of a transistor.
[0012] FIG. 2 depicts an embodiment of a deposition process for
forming a gate dielectric using electron beam evaporation according
to the teachings of the present invention.
[0013] FIG. 3 depicts an embodiment of another configuration of a
transistor capable of being fabricated according to the teachings
of the present invention.
[0014] FIG. 4 illustrates a perspective view of an embodiment of a
personal computer incorporating devices made according to the
teachings of the present invention.
[0015] FIG. 5 illustrates a schematic view of an embodiment of a
processing unit incorporating devices made according to the
teachings of the present invention.
[0016] FIG. 6 illustrates a schematic view of an embodiment of a
DRAM memory device according to the teachings of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention.
[0018] The terms wafer and substrate used in the following
description include any structure having an exposed surface with
which to form the integrated circuit (IC) structure of the
invention. The term substrate is understood to include
semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other
layers that have been fabricated thereupon. Both wafer and
substrate include doped and undoped semiconductors, epitaxial
semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator or dielectric is defined to
include any material that is less electrically conductive than the
materials referred to as conductors.
[0019] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate. The following detailed
description is, therefore, not to be taken in a limiting sense, and
the scope of the present invention is defined only by the appended
claims, along with the full scope of equivalents to which such
claims are entitled.
[0020] A gate dielectric 140 of FIG. 1, when operating in a
transistor, has both a physical gate dielectric thickness and an
equivalent oxide thickness (t.sub.eq). The equivalent oxide
thickness quantifies the electrical properties, such as
capacitance, of a gate dielectric 140 in terms of a representative
physical thickness. t.sub.eq is defined as the thickness of a
theoretical SiO.sub.2 layer that would be required to have the same
capacitance density as a given dielectric, ignoring leakage current
and reliability considerations.
[0021] A SiO.sub.2 layer of thickness, t, deposited on a Si surface
as a gate dielectric will also have a t.sub.eq larger than its
thickness, t. This t.sub.eq results from the capacitance in the
surface channel on which the SiO.sub.2 is deposited due to the
formation of a depletion/inversion region. This depletion/inversion
region can result in t.sub.eq being from 3 to 6 Angstroms (.ANG.)
larger than the SiO.sub.2 thickness, t. Thus, with the
semiconductor industry driving to someday scale the gate dielectric
equivalent oxide thickness, t.sub.eq, to under 10 .ANG., the
physical thickness requirement for a SiO.sub.2 layer used for a
gate dielectric would be need to be approximately 4 to 7 .ANG..
[0022] Additional requirements on a SiO.sub.2 layer would depend on
the gate electrode used in conjunction with the SiO.sub.2 gate
dielectric. Using a conventional polysilicon gate would result in
an additional increase in t.sub.eq for the SiO.sub.2 layer. This
additional thickness could be eliminated by using a metal gate
electrode, though metal gates are not currently used in
complementary metal-oxide-semiconductor field effect transistor
(CMOS) technology. Thus, future devices would be designed towards a
physical SiO.sub.2 gate dielectric layer of about 5 .ANG. or less.
Such a small thickness requirement for a SiO.sub.2 oxide layer
creates additional problems.
[0023] Silicon dioxide is used as a gate dielectric, in part, due
to its electrical isolation properties in a SiO.sub.2--Si based
structure. This electrical isolation is due to the relatively large
band gap of SiO.sub.2 (8.9 eV) making it a good insulator from
electrical conduction. Signification reductions in its band gap
would eliminate it as a material for a gate dielectric. As the
thickness of a SiO.sub.2 layer decreases, the number of atomic
layers, or monolayers of the material in the thickness decreases.
At a certain thickness, the number of monolayers will be
sufficiently small that the SiO.sub.2 layer will not have a
complete arrangement of atoms as in a larger or bulk layer. As a
result of incomplete formation relative to a bulk structure, a thin
SiO.sub.2 layer of only one or two monolayers will not form a full
band gap. The lack of a full band gap in a SiO.sub.2 gate
dielectric would cause an effective short between an underlying Si
channel and an overlying polysilicon gate. This undesirable
property sets a limit on the physical thickness to which a
SiO.sub.2 layer can be scaled. The minimum thickness due to this
monolayer effect is thought to be about 7-8 .ANG.. Therefore, for
future devices to have a t.sub.eq less than about 10 .ANG., other
dielectrics than SiO.sub.2 need to be considered for use as a gate
dielectric.
[0024] For a typical dielectric layer used as a gate dielectric,
the capacitance is determined as one for a parallel plate
capacitance: C=.kappa..epsilon..sub.0A/t, where .kappa. is the
dielectric constant, .epsilon..sub.0 is the permittivity of free
space, A is the area of the capacitor, and t is the thickness of
the dielectric. The thickness, t, of a material is related to
t.sub.eq for a given capacitance with the dielectric constant of
SiO.sub.2, .kappa..sub.ox=3.9, associated with t.sub.eq, as
t=(.kappa./.kappa..sub.ox)t.sub.eq=(.kappa./3.9)t.sub.eq.
[0025] Thus, materials with a dielectric constant greater than that
of SiO.sub.2, 3.9, will have a physical thickness that can be
considerably larger than a desired t.sub.eq, while providing the
desired equivalent oxide thickness. For example, an alternate
dielectric material with a dielectric constant of 10 could have a
thickness of about 25.6 .ANG. to provide a t.sub.eq of 10 .ANG.,
not including any depletion/inversion layer effects. Thus, the
reduced equivalent oxide thickness of transistors can be realized
by using dielectric materials with higher dielectric constants than
SiO.sub.2.
[0026] The thinner equivalent oxide thickness, t.sub.eq required
for lower transistor operating voltages and smaller transistor
dimensions may be realized by a significant number of materials,
but additional fabricating requirements makes determining a
suitable replacement for SiO.sub.2 difficult. The current view for
the microelectronics industry is still for Si based devices. This
requires that the gate dielectric employed be grown on a silicon
substrate or silicon layer, which places significant restraints on
the substitute dielectric material. During the formation of the
dielectric on the silicon layer, there exists the possibility that
a small layer of SiO.sub.2 could be formed in addition to the
desired dielectric. The result would effectively be a dielectric
layer consisting of two sublayers in parallel with each other and
the silicon layer on which the dielectric is formed. In such a
case, the resulting capacitance would be that of two dielectrics in
series. As a result, the t.sub.eq of the dielectric layer would be
the sum of the SiO.sub.2 thickness and a multiplicative factor of
the thickness, t, of the dielectric being formed, written as
t.sub.eq=t.sub.SiO2+(.kappa..sub.ox/.kappa.)t.
[0027] Thus, if a SiO.sub.2 layer is formed in the process, the
t.sub.eq is again limited by a SiO.sub.2 layer. In the event that a
barrier layer is formed between the silicon layer and the desired
dielectric in which the barrier layer prevents the formation of a
SiO.sub.2 layer, the t.sub.eq would be limited by the layer with
the lowest dielectric constant. However, whether a single
dielectric layer with a high dielectric constant or a barrier layer
with a higher dielectric constant than SiO.sub.2 is employed, the
layer interfacing with the silicon layer must provide a high
quality interface to maintain a high channel carrier mobility.
[0028] One of the advantages using SiO.sub.2 as a gate dielectric
has been that the formation of the SiO.sub.2 layer results is an
amorphous gate dielectric. Having an amorphous structure for a gate
dielectric is advantageous because grain boundaries in
polycrystalline gate dielectrics provide high leakage paths.
Additionally, grain size and orientation changes throughout a
polycrystalline gate dielectric can cause variations in the film's
dielectric constant. The abovementioned material properties,
including structure, are for the materials in a bulk form. Many
materials having the advantage of a high dielectric constant
relative to SiO.sub.2 also have the disadvantage of a crystalline
form, at least in a bulk configuration. The best candidates for
replacing SiO.sub.2 as a gate dielectric are those with high
dielectric constant, which can be fabricated as a thin layer with
an amorphous form.
[0029] One candidate for forming gate dielectrics is
Pr.sub.2O.sub.3. In co-pending, commonly assigned U.S. patent
applications: entitled "Low-Temperature Grown High-Quality
Ultra-Thin Praseodymium Gate Dielectrics," attorney docket no.
1303.033US1, Ser. No. 10/027,315, Pr.sub.2O.sub.3 is disclosed as a
replacement for SiO.sub.2 in forming gate dielectrics and other
dielectric films in electronic devices such as MOS transistors.
Additionally, in a recent article by H. J. Osten et al., Technical
Digest of IEDM, pp. 653-656 (2000), crystalline praseodymium oxide
on silicon was reported to have outstanding dielectric
properties.
[0030] However, in a recent article by H. Zhang et al., Journal of
the Electrochemical Societ, 148 (4) pp. F63-F66 (2001), it was
noted that dielectric layers using high-.kappa. materials tend to
have a narrower bandgap. The article reported investigating the use
of nanolaminates of ZrO.sub.2/HfO.sub.2, ZrO.sub.2/Ta.sub.2O.sub.5,
and Ta.sub.2O.sub.5/HfO.sub.2, instead of a single layer of either
Ta.sub.2O.sub.5, ZrO.sub.2, or HfO.sub.2. Each nanolaminate, that
is, a composite of thin alternating layers of insulators, was grown
using Atomic Layer Deposition. The dielectric layers formed of
these nanolaminates were reported to have a dielectric constant in
the range of 9 to 16, providing a t.sub.eq reduction factor of
about 3 relative to SiO.sub.2.
[0031] Embodiments according to the teachings of the present
invention provide a novel set of dielectric structures for
replacing SiO.sub.2 as a gate dielectric and as other dielectrics
requiring an ultra-thin equivalent oxide thicknesses, t.sub.eq.
Dielectric layers containing layers of Pr.sub.2O.sub.3 and another
lanthanide oxide for use as the replacement dielectric are formed
in various embodiments. In one embodiment, a dielectric layer is
grown by forming a layer of Pr.sub.2O.sub.3 on a substrate and
forming a layer of another lanthanide oxide onto the layer of
Pr.sub.2O.sub.3. In another embodiment, forming a layer of
Pr.sub.2O.sub.3 on a substrate and forming a layer of another
lanthanide oxide onto the layer of Pr.sub.2O.sub.3 is controlled to
form a thin layer of each material with the combination of the two
alternating layers of insulators forming a nanolaminate. The other
lanthanide oxide used to form the nanolaminate is selected from a
group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3. Alternately, the nanolaminate
formed as the dielectric layer can be formed from multiple
alternating thin layers of lanthanide oxides with the initial layer
deposited being a layer of Pr.sub.2O.sub.3. Advantageously, using
Pr.sub.2O.sub.3 for the initial layer provides a thin amorphous
layer or region at the surface of a silicon based substrate.
[0032] By forming the dielectric layer as a nanolaminate, the
dielectric layer can be grown as a composite whose insulating
properties can be adjusted. The engineering of the nanolaminate
allows the formation of a dielectric layer with a dielectric
constant ranging between the values of the dielectric constants of
the lanthanide oxides which form the dielectric layer. However, in
many cases the dielectric layer will have an effective dielectric
constant less than the dielectric constant of the lanthanide oxides
used to form the dielectric layer. This reduction in the effective
dielectric constant is due to interfacial layers formed between the
silicon substrate surface and the first lanthanide oxide layer of
the nanolaminate.
[0033] In one embodiment, a nanolaminate is grown by forming a
layer of Pr.sub.2O.sub.3 on a substrate by electron beam
evaporation. Subsequently, a layer of another lanthanide oxide is
formed onto the layer of Pr.sub.2O.sub.3 also by electron beam
evaporation. The resulting nanolaminate has a total thickness which
is about the same as the thickness of the initial layer of
Pr.sub.2O.sub.3 formed on the substrate. Thus, each layer in the
nanolaminate is reduced to one-half the original thickness
deposited. Such films are uniformly produced with a t.sub.eq less
than 20 .ANG., typically with about a t.sub.eq of about 14
.ANG..
[0034] FIG. 2 depicts an embodiment of a deposition process for
forming a gate dielectric using electron beam evaporation according
to the teachings of the present invention. This process can be used
to deposit a material forming a film containing a layer of
Pr.sub.2O.sub.3 and a layer of another lanthanide oxide on a
surface such as a body region of a transistor. In FIG. 2, a
substrate 210 is placed inside a deposition chamber 260. The
substrate in this embodiment is masked by a first masking structure
270 and a second masking structure 271. In this embodiment, the
unmasked region 233 includes a body region of a transistor, however
one skilled in the art will recognize that other semiconductor
device structures may utilize this process. Also located within the
deposition chamber 260 is an electron gun 263 and a target 261. The
electron gun 263 provides an electron beam 264 directed at target
261 containing a source material for forming Pr.sub.2O.sub.3 and
other lanthanide oxides on the unmasked region 233 of the substrate
210. The electron gun 263 includes a rate monitor for controlling
the rate of evaporation of the material in the target 261 at which
the electron beam 264 is directed. For convenience, control
displays and necessary electrical connections as are known to those
skilled in the art are not shown in FIG. 2. Alternatively, a
chamber can be used with multiple electron guns, where each
electron gun is directed to different targets containing sources to
form selected lanthanide oxides to be used at different times in
the process.
[0035] During the evaporation process, the electron gun 263
generates an electron beam 264 that hits target 261. In one
embodiment, target 261 contains a ceramic Pr.sub.6O.sub.11 source,
which is evaporated due to the impact of the electron beam 264. The
evaporated material 268 is then distributed throughout the chamber
260. A dielectric layer of Pr.sub.2O.sub.3 is grown forming a film
240 on the surface of the exposed body region 233 that it contacts.
The growth rate can vary with a typical rate of 0.1 .ANG./s. The
resultant Pr.sub.2O.sub.3 layer includes a thin amorphous
interfacial layer of about 0.5 nm thickness separating a
crystalline layer of Pr.sub.2O.sub.3 from the substrate on which it
is grown. This thin amorphous layer is beneficial in reducing the
number of interface charges and eliminating any grain boundary
paths for conductance from the substrate. Other source materials
can be used for forming the Pr.sub.2O.sub.3 layer, as are known to
those skilled in the art.
[0036] Subsequent to the formation of the Pr.sub.2O.sub.3 layer,
another lanthanide oxide is deposited on the film 240 converting
the film 240 from a Pr.sub.2O.sub.3 layer to a nanolaminate of
Pr.sub.2O.sub.3 and the other lanthanide oxide. The other
lanthanide oxide is selected from the group consisting of
Nd.sub.2O.sub.3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and
Dy.sub.2O.sub.3. Depending on the lanthanide oxide selected to form
the nanolaminate, a corresponding source material is used in the
target 261 for electron beam evaporation. The source material for
the particular lanthanide oxide is chosen from commercial materials
for forming the lanthanide oxide by electron bean evaporation, as
is known by those skilled in the art.
[0037] After forming the nanolaminate, the structure is annealed
briefly at 600.degree. C. As a result of this brief anneal, there
is no significant hysteresis in capacitance-voltage (C-V)
measurements. Further, the nanolaminates can be annealed up to
1000.degree. C. for 15 seconds with no degradation in electrical
properties. In one embodiment, such films have a t.sub.eq of 14
.ANG. with a leakage current of approximately 5.times.10.sup.-9
.ANG./cm.sup.2 at a gate voltages of .+-.1 V, with a dielectric
constant ranging from the dielectric constant of a Pr.sub.2O.sub.3
film on silicon, 31, to the dielectric constant of the other
selected lanthanide oxide. Advantageously, this leakage current is
at least 10.sup.4 times lower that the best published value of
HfO.sub.2 or ZrO.sub.2 films with the same t.sub.eq and a 3 nm
thick SiO.sub.2 layer.
[0038] In one embodiment alternating layers of Pr.sub.2O.sub.3 and
another selected lanthanide oxide are formed by controlled electron
beam evaporation providing layers of material of predetermined
thickness. This control allows the engineering of a dielectric with
a predetermined thickness, and composition. Through evaluation of
different lanthanide oxides at various thicknesses and number of
layers, a dielectric layer with a predetermined t.sub.eq in a
narrow range of values can be grown. Alternately, after forming a
Pr.sub.2O.sub.3 layer and a layer of another lanthanide oxide,
additional layers of additional lanthanide oxides can be formed.
Each layer of an additional lanthanide oxide selected from a group
consisting of Pr.sub.2O.sub.3, Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3. Consequently, a dielectric
layer can be engineered with electrical characteristics suited for
a given application. These electrical characteristics include
t.sub.eq and leakage current. A t.sub.eq of less than 20 .ANG. can
be obtained with typically sizes about of about 14 .ANG. to 8.5
.ANG..
[0039] In another embodiment, nanolaminates of lanthanide oxides
are formed by electron beam evaporation. The lanthanide oxides used
in these nanolaminates are chosen from the group consisting of
Pr.sub.2O.sub.3, Nd.sub.2O.sub.3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3,
and Dy.sub.2O.sub.3. The structure of the nanolaminates can be
varied with any one of the group used as the initial layer formed
on a substrate. Typically, the substrate is silicon based, since
these lanthanide oxides are thermodynamically stable with respect
to formation on a silicon surface. In an alternate embodiment,
lanthanide oxide nanolaminates are formed by atomic layer
deposition.
[0040] The Pr.sub.2O.sub.3 film formed on a silicon has a
dielectric constant of about 31 when formed with little or no
interfacial layer between the Pr.sub.2O.sub.3 film and the
substrate. The dielectric constants for the other lanthanide oxides
are also in the range of 25-30. As a result, a dielectric layer
grown by forming a nanolaminate of lanthanide oxides has a
dielectric constant in the range of about 25 to about 31. However,
with an interfacial layer formed between the surface of the
substrate and the first lanthanide oxide, the t.sub.eq of the
dielectric layer is the t.sub.eq of the interfacial layer in
parallel with the lanthanide oxide nanolaminate. Thus, the
dielectric layer formed having an interfacial layer between the
substrate on which it is grown and a lanthanide oxide nanolaminate
can have an effective dielectric constant considerably less than a
dielectric constant associated with a nanolaminate of lanthanide
oxides. This is dependent upon the dielectric constant of the
interfacial material being considerably less than the dielectric
constant of the lanthanide oxides used to form the
nanolaminate.
[0041] As previously noted above, a Pr.sub.2O.sub.3 layer can be
formed on a silicon based substrate having a dielectric constant of
about 31 with an interfacial layer of about 0.5 nm (5 .ANG.). In
another embodiment, for an interfacial layer of about 10.7 .ANG.,
an effective dielectric constant for a thin layer of
Pr.sub.2O.sub.3 on silicon is about 15. Similar effective
dielectric constants are associated with thin layers of
Nd.sub.2O.sub.3, Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and
Dy.sub.2O.sub.3 oxides on silicon. For example, a thin layer of
Nd.sub.2O.sub.3 has an effective dielectric constant of about 12.9
with an interfacial layer of about 8.2 .ANG., a thin layer of
Sm.sub.2O.sub.3 has an effective dielectric constant of about 11.4
with an interfacial layer of about 5.5 .ANG., a thin layer of
Gd.sub.2O.sub.3 has an effective dielectric constant of about 13.9
with an interfacial layer of about 10 .ANG., and a thin layer of
Dy.sub.2O.sub.3 has an effective dielectric constant of about 14.3
with an interfacial layer of about 12 .ANG.. Lanthanide oxides
grown on silicon with these reduced effective dielectric constants
and corresponding interfacial layers can be attained with a
t.sub.eq equal to about 13 .ANG. for Pr.sub.2O.sub.3, about 12.4
.ANG. for Nd.sub.2O.sub.3, about 12.2 .ANG. for Sm.sub.2O.sub.3,
about 13 .ANG. for Gd.sub.2O.sub.3, and about 13.3 .ANG. for
Dy.sub.2O.sub.3. Consequently, nanolaminates of these lanthanide
oxides can be formed with an effective dielectric constants in the
range of 11 to 15 and a t.sub.eq in the range of about 12 .ANG. to
about 14 .ANG..
[0042] The formation of the interfacial layer is one factor in
determining how thin a layer can be grown. An interfacial layer can
be SiO.sub.2 for many processes forming a non-SiO.sub.2 dielectric
on a silicon substrate. However, advantageously, in an embodiment
forming a lanthanide oxide nanolaminate with an initial layer of
Pr.sub.2O.sub.3, a thin amorphous interfacial layer is formed that
is not a SiO.sub.2 layer. Typically, this interfacial layer is
either an amorphous layer primarily of Pr.sub.2O.sub.3 formed
between the silicon substrate and a crystalline form of
Pr.sub.2O.sub.3, or a layer of Pr--Si--O silicate. The dielectric
constant for Pr--Si--O silicate is significantly greater than
SiO.sub.2, but not as high as Pr.sub.2O.sub.3.
[0043] Another factor setting a lower limit for the scaling of a
dielectric layer is the number of monolayers of the dielectric
structure necessary to develop a full band gap such that good
insulation is maintained between an underlying silicon layer and an
overlying conductive layer on the dielectric layer or film. This
requirement is necessary to avoid possible short circuit effects
between the underlying silicon layer and the overlying conductive
layer used. In one embodiment, for a 0.5 nm interfacial layer and
several monolayers of lanthanide grown, an expected lower limit for
the physical thickness of a dielectric layer grown by forming a
lanthanide oxide nanolaminate is anticipated to be in about the 2-4
nm range. Consequently, typical dielectric layers or films can be
grown by forming lanthanide oxide nanolaminates having physical
thickness in the range of 4 to 10 nm. The number of layers used,
the thickness of each layer, and the lanthanide oxide used for each
layer can be engineered to provide the desired electrical
characteristics. Pr.sub.2O.sub.3 used as the initial layer is
expected to provide excellent overall results with respect to
reliability, current leakage, and ultra-thin t.sub.eq.
[0044] Alternate embodiments include forming lanthanide oxide
nanolaminates by electron beam evaporation with target material to
form Pr.sub.2O.sub.3 other than Pr.sub.6O.sub.11, forming
lanthanide oxide nanolaminates by atomic layer deposition, and
electron beam evaporation forming lanthanide oxide nanolaminates
with initial layers of a lanthanide oxide other than
Pr.sub.2O.sub.3. The physical thicknesses can range from about 2 nm
to about 10 nm with typical thickness ranging from about 4 nm to
about 10 nm. Such layers have an effective dielectric constant
ranging from 11 to 31, where a layer with a typical interfacial
layer has an effective dielectric constant in the range 11 to 16
and a layer with a significantly thin interfacial layer can attain
an effective dielectric constant in the range 25 to 31.
Consequently, a range for the equivalent oxide thickness of a
dielectric layer formed as a lanthanide oxide nanolaminate can be
engineered over a significant range. The expected t.sub.eq ranges
for various effective dielectric constants are shown in the
following
1 Physical Physical Physical Physical Thickness Thickness Thickness
Thickness t = 0.5 nm t = 1.0 nm t = 2.0 nm t = 10 nm (5 .ANG.) (10
.ANG.) (20 .ANG.) (100 .ANG.) .kappa. t.sub.eq (.ANG.) t.sub.eq
(.ANG.) t.sub.eq (.ANG.) t.sub.eq (.ANG.) 11 1.77 3.55 7.09 35.45
12 1.63 3.25 6.50 32.50 13 1.50 3.00 6.00 30.00 14 1.39 2.79 5.57
27.86 15 1.30 2.60 5.20 26.00 16 1.22 2.44 4.88 24.38 20 0.98 1.95
3.90 19.50 25 0.78 1.56 3.12 15.60 31 0.63 1.26 2.52 12.58
[0045] As noted previously, various embodiments provide a typical
t.sub.eq of about 14 .ANG.. With careful preparation and
engineering of the lanthanide oxide nanolaminate limiting the size
of interfacial regions, a t.sub.eq down to 2.5 .ANG. or lower is
anticipated.
[0046] The novel process described above provides significant
advantages by providing a straight forward method of forming
dielectric layers having ultra-thin equivalent oxide thicknesses by
electron beam evaporation. Praseodymium oxide-based nanolaminates
provide excellent reliability characteristics, based on
measurements of current density as a function of gate voltage and
stress induced leakage currents for the lanthanide oxides which
form the nanolaminates. The dielectric breakdown occurs a least
above 43 MEV/cm. The lanthanide oxides forming the nanolaminates
retain excellent J-V characteristics even after stress-induced
electrical breakdown. Though the praseodymium oxide forming the
first layer of the nanolaminate is epitaxially oriented with
respect to a substrate on which it is formed, the praseodymium
layer is separated from the substrate surface by a thin amorphous
layer. Additionally, the novel process and novel dielectric layer
structure can be implemented to form transistors, memory devices,
and electronic systems including information handling devices.
[0047] A transistor 100 as depicted in FIG. 1 can be formed by
forming a source/drain region 120 and another source/drain region
130 in a silicon based substrate 110 where the two source/drain
regions 120, 130 are separated by a body region 132. The body
region 132 separated by the source/drain 120 and the source/drain
130 defines a channel having a channel length 134. Pr.sub.2O.sub.3
is formed on the body region 132 by evaporation using a electron
gun at a controlled rate. Subsequently, another lanthanide oxide
selected from the group consisting of Nd.sub.2O.sub.3,
Sm.sub.2O.sub.3, Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3 is formed on
the Pr.sub.2O.sub.3 layer by controlling a rate of electron beam
evaporation. This controlled process forms a film 140 containing a
nanolaminate of Pr.sub.2O.sub.3 and another lanthanide oxide on the
body region 132. A gate 150 is formed over the gate dielectric 140.
Typically, forming the gate 150 includes forming a polysilicon
layer, though a metal gate can be formed in an alternative process.
Forming the substrate, source/region regions, and the gate is
performed using standard processes known to those skilled in the
art. Additionally, the sequencing of the various elements of the
process for forming a transistor is conducted with standard
fabrication processes, also as known to those skilled in the
art.
[0048] The method of forming lanthanide oxide nanolaminates for a
gate dielectric is applied to other transistor structures having
dielectric layers in various embodiments according to the teachings
of the present invention. For example, the structure of FIG. 3
depicts a transistor 300 having a silicon based substrate 310 with
two source/drain regions 320, 330 separated by a body region 332.
The body region 332 between the two source/drain regions 320, 330
defines a channel region having a channel length 334. Located above
the body region 332 is a stack 355 including a gate dielectric 340,
a floating gate 352, a floating gate dielectric 342, and a control
gate 350. The gate dielectric 340 can be formed as described above
with the remaining elements of the transistor 300 formed using
processes known to those skilled in the art. Alternately, both the
gate dielectric 340 and the floating gate dielectric 342 can be
formed by various embodiments in accordance with the present
invention as described above.
[0049] Transistors created by the methods described above may be
implemented into memory devices and electronic systems including
information handling devices. Information handling devices having a
dielectric layer containing a lanthanide oxide nanolaminate can be
constructed using various embodiments of the methods described
above. Such information devices include wireless systems,
telecommunication systems, and computers. An embodiment of a
computer having a dielectric layer containing a lanthanide oxide
nanolaminate is shown in FIGS. 4-6 and described below. While
specific types of memory devices and computing devices are shown
below, it will be recognized by one skilled in the art that several
types of memory devices and information handling devices utilize
the invention.
[0050] A personal computer, as shown in FIGS. 4 and 5, include a
monitor 400, keyboard input 402 and a processing unit 404. The
processor unit 404 typically includes microprocessor 506, memory
bus circuit 508 having a plurality of memory slots 512(a-n), and
other peripheral circuitry 510. Peripheral circuitry 510 permits
various peripheral devices 524 to interface processor-memory bus
520 over input/output (I/O) bus 522. The personal computer shown in
FIGS. 4 and 5 also includes at least one transistor having a gate
dielectric containing a lanthanide oxide nanolaminate in an
embodiment according to the teachings of the present invention.
[0051] Microprocessor 506 produces control and address signals to
control the exchange of data between memory bus circuit 508 and
microprocessor 506 and between memory bus circuit 508 and
peripheral circuitry 510. This exchange of data is accomplished
over high speed memory bus 520 and over high speed I/O bus 522.
[0052] Coupled to memory bus 520 are a plurality of memory slots
512(a-n) which receive memory devices well known to those skilled
in the art. For example, single in-line memory modules (SIMMs) and
dual in-line memory modules (DIMMs) may be used in the
implementation of the present invention.
[0053] These memory devices can be produced in a variety of designs
which provide different methods of reading from and writing to the
dynamic memory cells of memory slots 512. One such method is the
page mode operation. Page mode operations in a DRAM are defined by
the method of accessing a row of a memory cell arrays and randomly
accessing different columns of the array. Data stored at the row
and column intersection can be read and output while that column is
accessed. Page mode DRAMs require access steps which limit the
communication speed of memory circuit 508.
[0054] An alternate type of device is the extended data output
(EDO) memory which allows data stored at a memory array address to
be available as output after the addressed column has been closed.
This memory can increase some communication speeds by allowing
shorter access signals without reducing the time in which memory
output data is available on memory bus 520. Other alternative types
of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as
well as others such as SRAM or Flash memories.
[0055] FIG. 6 is a block diagram of an illustrative DRAM device 600
compatible with memory slots 512(a-n). The description of DRAM 600
has been simplified for purposes of illustrating a DRAM memory
device and is not intended to be a complete description of all the
features of a DRAM. Those skilled in the art will recognize that a
wide variety of memory devices may be used in the implementation of
the present invention. The example of a DRAM memory device shown in
FIG. 6 includes at least one transistor having a gate dielectric
containing a lanthanide oxide nanolaminate in an embodiment
according to the teachings of the present invention.
[0056] Control, address and data information provided over memory
bus 520 is further represented by individual inputs to DRAM 600, as
shown in FIG. 6. These individual representations are illustrated
by data lines 602, address lines 604 and various discrete lines
directed to control logic 606.
[0057] As is well known in the art, DRAM 600 includes memory array
610 which in turn comprises rows and columns of addressable memory
cells. Each memory cell in a row is coupled to a common word line.
The word line is coupled to gates of individual transistors, where
at least one transistor has a gate coupled to a gate dielectric
containing a layer Pr.sub.2O.sub.3 and a layer another lanthanide
oxide in accordance with the method and structure previously
described above. Additionally, each memory cell in a column is
coupled to a common bit line. Each cell in memory array 610
includes a storage capacitor and an access transistor as is
conventional in the art.
[0058] DRAM 600 interfaces with, for example, microprocessor 606
through address lines 604 and data lines 602. Alternatively, DRAM
600 may interface with a DRAM controller, a micro-controller, a
chip set or other electronic system. Microprocessor 506 also
provides a number of control signals to DRAM 600, including but not
limited to, row and column address strobe signals RAS and CAS,
write enable signal WE, an output enable signal OE and other
conventional control signals.
[0059] Row address buffer 612 and row decoder 614 receive and
decode row addresses from row address signals provided on address
lines 604 by microprocessor 506. Each unique row address
corresponds to a row of cells in memory array 610. Row decoder 614
includes a word line driver, an address decoder tree, and circuitry
which translates a given row address received from row address
buffers 612 and selectively activates the appropriate word line of
memory array 610 via the word line drivers.
[0060] Column address buffer 616 and column decoder 618 receive and
decode column address signals provided on address lines 604. Column
decoder 618 also determines when a column is defective and the
address of a replacement column. Column decoder 618 is coupled to
sense amplifiers 620. Sense amplifiers 620 are coupled to
complementary pairs of bit lines of memory array 610.
[0061] Sense amplifiers 620 are coupled to data-in buffer 622 and
data-out buffer 624. Data-in buffers 622 and data-out buffers 624
are coupled to data lines 602. During a write operation, data lines
602 provide data to data-in buffer 622. Sense amplifier 620
receives data from data-in buffer 622 and stores the data in memory
array 610 as a charge on a capacitor of a cell at an address
specified on address lines 604.
[0062] During a read operation, DRAM 600 transfers data to
microprocessor 506 from memory array 610. Complementary bit lines
for the accessed cell are equilibrated during a precharge operation
to a reference voltage provided by an equilibration circuit and a
reference voltage supply. The charge stored in the accessed cell is
then shared with the associated bit lines. A sense amplifier of
sense amplifiers 620 detects and amplifies a difference in voltage
between the complementary bit lines. The sense amplifier passes the
amplified voltage to data-out buffer 624.
[0063] Control logic 606 is used to control the many available
functions of DRAM 600. In addition, various control circuits and
signals not detailed herein initiate and synchronize DRAM 600
operation as known to those skilled in the art. As stated above,
the description of DRAM 600 has been simplified for purposes of
illustrating the present invention and is not intended to be a
complete description of all the features of a DRAM. Those skilled
in the art will recognize that a wide variety of memory devices,
including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other
DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the
implementation of embodiments of the present invention. The DRAM
implementation described herein is illustrative only and not
intended to be exclusive or limiting.
Conclusion
[0064] A gate dielectric containing a layer of Pr.sub.2O.sub.3 and
a layer of another lanthanide oxide, and a method of fabricating
such a gate dielectric are provided that produces a reliable gate
dielectric having an equivalent oxide thickness thinner than
attainable using SiO.sub.2. Gate dielectric structures that are
formed using the methods described herein include nanolaminates of
Pr.sub.2O.sub.3 and another lanthanide oxide selected from the
group consisting of Nd.sub.2O.sub.3, Sm.sub.2O.sub.3,
Gd.sub.2O.sub.3, and Dy.sub.2O.sub.3. These gate dielectric
structures are thermodynamically stable such that the gate
dielectrics formed will have minimal reactions with a silicon
substrate or other structures during processing.
[0065] Transistors, higher level ICs, devices, and electronic
systems are provided utilizing the novel gate dielectric and
process of formation. Gate dielectric layers of lanthanide oxide
nanolaminates are formed having a high dielectric constant
(.kappa.), where the gate dielectrics are capable of a t.sub.eq of
14 .ANG. or thinner, providing suitable substitutes for SiO.sub.2
gate dielectrics. At the same time, the physical thickness of the
Pr.sub.2O.sub.3 layer is much larger than the SiO.sub.2 thickness
associated with the t.sub.eq limit of SiO.sub.2. Forming the larger
thickness provides advantages in processing the gate dielectric. In
addition forming a dielectric layer or film containing a lanthanide
oxide nanolaminate allows the engineering or selection of a
dielectric constant ranging from that of Pr.sub.2O.sub.3 to a
dielectric constant of another lanthanide oxide that is comprised
in the nanolaminate.
[0066] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. It is to be understood that the above
description is intended to be illustrative, and not restrictive.
Combinations of the above embodiments, and other embodiments will
be apparent to those of skill in the art upon reviewing the above
description. The scope of the invention includes any other
applications in which the above structures and fabrication methods
are used. The scope of the invention should be determined with
reference to the appended claims, along with the full scope of
equivalents to which such claims are entitled.
* * * * *