U.S. patent application number 10/869863 was filed with the patent office on 2005-01-27 for semiconductor integrated circuit.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Ueno, Masaji.
Application Number | 20050017809 10/869863 |
Document ID | / |
Family ID | 34082292 |
Filed Date | 2005-01-27 |
United States Patent
Application |
20050017809 |
Kind Code |
A1 |
Ueno, Masaji |
January 27, 2005 |
Semiconductor integrated circuit
Abstract
A semiconductor integrated circuit includes first and second
differential amplification devices to amplify a voltage difference
of input signals inputted from a positive input terminal and a
negative input terminal, first and second addition devices to add
an output of the first differential amplification device and an
output of the first differential amplification, an output stage
control device controlled by the first and second addition devices,
an output stage controlled by the output stage control device, and
an output terminal connected to the output stage.
Inventors: |
Ueno, Masaji; (Kanagawa-ken,
JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
34082292 |
Appl. No.: |
10/869863 |
Filed: |
June 18, 2004 |
Current U.S.
Class: |
330/255 |
Current CPC
Class: |
H03F 3/4521
20130101 |
Class at
Publication: |
330/255 |
International
Class: |
H03F 003/45 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 20, 2003 |
JP |
2003-176079 |
Jun 10, 2004 |
JP |
2004-172157 |
Claims
What is claimed is:
1. A semiconductor integrated circuit, comprising: a first
differential amplification device with a first polarity, the first
differential amplification device being configured to amplify a
voltage difference of two input signals inputted from a positive
input terminal and a negative input terminal respectively; a second
differential amplification device with a second polarity opposite
of the first polarity, the second differential amplification device
being configured to amplify the voltage difference of two input
signals inputted from the positive input terminal and the negative
input terminal respectively; a first addition device configured to
add a non-inverted output of the first differential amplification
device and an inverted output of the second differential
amplification device; a second addition device configured to add a
non-inverted output of the second differential amplification device
and an inverted output of the first differential amplification
device; an output stage control device having first and second
switching elements, the first switching element with the first
polarity controlled by an output signal of the second addition
device, and the second switching element with the second polarity
controlled by an output signal of the first addition device; an
output stage having a third switching element with the first
polarity controlled by an output signal of the first switching
element of the output stage control device, and a fourth switching
element with the second polarity controlled by an output signal of
the second switching element of the output stage control device;
and an output terminal configured to be connected to an output
terminal of the third switching element and an output terminal of
the fourth switching element in common.
2. The semiconductor integrated circuit according to claim 1,
wherein the output stage control device includes an output
stabilization circuit, the output stabilization circuit being
configured to control each operating current of the first and the
second switching elements, and the output stabilization circuit
having a phase compensation function of the output stage.
3. A semiconductor integrated circuit, comprising: a positive input
terminal; a negative input terminal; a first differential
amplification circuit with a first polarity having a first positive
input terminal connected to the positive input terminal, a first
negative input terminal connected to the negative input terminal, a
first non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the first positive input terminal
and the first negative input terminal, and a first inverted output
terminal outputting an inverted output signal being inverted signal
of the output signal of the first non-inverted output terminal; a
second differential amplification circuit with a second polarity
opposite of the first polarity, having a second positive input
terminal connected to the positive input terminal, a second
negative input terminal connected to the negative input terminal, a
second non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the second positive-input terminal
and the second negative input terminal, and a second inverted
output terminal outputting an inverted output signal being inverted
signal of the output signal of the second non-inverted output
terminal; a first current addition device configured to add a
current, the current being configured to flow at the first
non-inverted output terminal of the first differential
amplification circuit and a current, the current being configured
to flow at the second inverted output terminal of the second
differential amplification circuit; a second current addition
device configured to add a current, the current being configured to
flow at the second non-inverted output terminal of the second
differential amplification circuit and a current, the current being
configured to flow at the first inverted output terminal of the
first differential amplification circuit; an output stage control
device having a first switching element with the first polarity
having a control terminal connected to an output terminal of the
second current addition device, and a second switching element with
the second polarity having a control terminal connected to an
output terminal of the first current addition device; an output
stage having a third switching element with the first polarity
having a control terminal connected to an output terminal of the
first switching element, and a fourth switching element with the
second polarity having a control terminal connected to an output
terminal of the second switching element; an output terminal
configured to be connected an output terminal of the third
switching element and an output terminal of the fourth switching
element in common; a first phase compensation circuit connecting
between the output terminal of the third switching element and the
control terminal of the third switching element; and a second phase
compensation circuit connecting between the output terminal of the
fourth switching element and the control terminal of the fourth
switching element.
4. A semiconductor integrated circuit, comprising: a first bias
voltage terminal; a second bias voltage terminal; a positive input
terminal; a negative input terminal; a first differential
amplification circuit with a first polarity having a first positive
input terminal connected to the positive input terminal, a first
negative input terminal connected to the negative input terminal, a
first non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the first positive input terminal
and the first negative input terminal, and a first inverted output
terminal outputting an inverted output signal being inverted signal
of the output signal of the first non-inverted output terminal; a
second differential amplification circuit with a second polarity
opposite of the first polarity, having a second positive input
terminal connected to the positive input terminal, a second
negative input terminal connected to the negative input terminal, a
second non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the second positive-input terminal
and the second negative input terminal, and a second inverted
output terminal outputting an inverted output signal being inverted
signal of the output signal of the second non-inverted output
terminal; a first current addition device configured to add a
current, the current being configured to flow at the first
non-inverted output terminal of the first differential
amplification circuit and a current, the current being configured
to flow at the second inverted output terminal of the second
differential amplification circuit; a second current addition
device configured to add a current, the current being configured to
flow at the second non-inverted output terminal of the second
differential amplification circuit and a current, the current being
configured to flow at the first inverted output terminal of the
first differential amplification circuit; an output stage control
device having a first switching element with the first polarity
having a control terminal connected to an output terminal of the
second current addition device, a second switching element with the
second polarity having a control terminal connected to an output
terminal of the first current addition device, a third switching
element controlling an output voltage of the second switching
element with the first polarity having a control terminal connected
to the first bias voltage terminal, and a fourth switching element
controlling an output voltage of the first switching element with
the second polarity having a control terminal connected to the
second bias voltage terminal; an output stage having a fifth
switching element with the first polarity having a control terminal
connected to an output terminal of the first switching element, and
a sixth switching element with the second polarity having a control
terminal connected to an output terminal of the second switching
element; an output terminal configured to be connected an output
terminal of the fifth switching element and an output terminal of
the sixth switching element in common; a first phase compensation
circuit connecting between the output of the fifth switching
element terminal and the control terminal of the fifth switching
element; and a second phase compensation circuit connecting between
the output terminal of the sixth switching element and the control
terminal of the sixth switching element.
5. The semiconductor integrated circuit according to claim 3,
wherein the first differential amplification circuit includes: a
first n type transistor having a gate electrode connected to the
positive input terminal; a second n type transistor having a gate
electrode connected to the negative input terminal; a first current
source having one terminal connected common to a source electrode
of the first n type transistor and a source electrode of the second
n type transistor, and an opposite side terminal is connected to a
first power supply; a first p type transistor having a drain
electrode and a gate electrode connected to a drain electrode of
the first n type transistor, and a source electrode connected to a
second power supply; a second p type transistor having a drain
electrode being the first non-inverted output terminal and a gate
electrode connected to a drain electrode of the second n type
transistor, and a source electrode connected to the second power
supply; and a third p type transistor having a gate electrode
connected to the gate electrode of the first p type transistor, a
source electrode connected to the second power supply, and a drain
electrode being the first inverted output terminal, and wherein the
second differential amplification circuit includes: a fourth p type
transistor having a gate electrode connected to the positive input
terminal; a fifth p type transistor having a gate electrode
connected to the negative input terminal; a second current source
having one terminal connected common to a source electrode of the
fourth p type transistor and a source electrode of the fifth p type
transistor, and an opposite side terminal connected to the second
power supply; a third n type transistor having a drain electrode
and a gate electrode connected to a drain electrode of the fourth p
type transistor, and a source electrode connected to the first
power supply; a fourth n type transistor having a drain electrode
being the second non-inverted output terminal and a gate electrode
connected to a drain electrode of the fifth p type transistor, and
a source electrode connected to the first power supply; and a fifth
n type transistor having a gate electrode connected to the gate
electrode of the third n type transistor, a source electrode
connected to the first power supply, and a drain electrode being
the second inverted output terminal.
6. The semiconductor integrated circuit according to claim 3,
wherein the first differential amplification circuit includes: a
first n type transistor having a gate electrode connected to the
positive input terminal; a second n type transistor having a gate
electrode connected to the negative input terminal; a first current
source having one terminal connected common to a source electrode
of the first n type transistor and a source electrode of the second
n type transistor, and an opposite side terminal is connected to a
first power supply; a first p type transistor having a drain
electrode and a gate electrode connected to a drain electrode of
the first n type transistor, and a source electrode connected to a
second power supply; a second p type transistor having a drain
electrode being the first non-inverted output terminal and a gate
electrode connected to a drain electrode of the second n type
transistor, and a source electrode connected in series with a first
resister to the second power supply; and a third p type transistor
having a gate electrode connected to the gate electrode of the
first p type transistor, a source electrode connected to the second
power supply, and a drain electrode being the first inverted output
terminal, and wherein the second differential amplification circuit
includes: a fourth p type transistor having a gate electrode
connected to the positive input terminal; a fifth p type transistor
having a gate electrode connected to the negative input terminal; a
second current source having one terminal connected common to a
source electrode of the fourth p type transistor and a source
electrode of the fifth p type transistor, and an opposite side
terminal connected to the second power supply; a third n type
transistor having a drain electrode and a gate electrode connected
to a drain electrode of the fourth p type transistor, and a source
electrode connected to the first power supply; a fourth n type
transistor having a drain electrode being the second non-inverted
output terminal and a gate electrode connected to a drain electrode
of the fifth p type transistor, and a source electrode connected in
series with a second resister to the first power supply; and a
fifth n type transistor having a gate electrode connected to the
gate electrode of the third n type transistor, a source electrode
connected to the first power supply, and a drain electrode being
the second inverted output terminal.
7. The semiconductor integrated circuit according to claim 4,
wherein the first differential amplification circuit includes: a
first n type transistor having a gate electrode connected to the
positive input terminal; a second n type transistor having a gate
electrode connected to the negative input terminal; a first current
source having one terminal connected common to a source electrode
of the first n type transistor and a source electrode of the second
n type transistor, and an opposite side terminal is connected to a
first power supply; a first p type transistor having a drain
electrode and a gate electrode connected to a drain electrode of
the first n type transistor, and a source electrode connected to a
second power supply; a second p type transistor having a gate
electrode connected to the second bias voltage terminal, and a
source electrode connected to the second power supply; a third p
type transistor having a drain electrode being the first
non-inverted output terminal and a gate electrode connected to a
drain electrode of the second n type transistor, and a source
electrode connected to a drain electrode of the second p type
transistor; and a fourth p type transistor having a gate electrode
connected to the gate electrode of the first p type transistor, a
source electrode connected to the second power supply, and a drain
electrode being the first inverted output terminal, and wherein the
second differential amplification circuit includes: a fifth p type
transistor having a gate electrode connected to the positive input
terminal; a sixth p type transistor having a gate electrode
connected to the negative input terminal; a second current source
having one terminal connected common to a source electrode of the
fifth p type transistor and a source electrode of the sixth p type
transistor, and an opposite side terminal connected to the second
power supply; a third n type transistor having a drain electrode
and a gate electrode connected to a drain electrode of the fifth p
type transistor, and a source electrode connected to the first
power supply; a fourth n type transistor having a gate electrode
connected to the first bias voltage terminal, and a source
electrode connected to the first power supply; a fifth n type
transistor having a drain electrode being the second non-inverted
output terminal and a gate electrode connected to a drain electrode
of the sixth p type transistor, and a source electrode connected to
a drain electrode of the fourth n type transistor; and a sixth n
type transistor having a gate electrode connected to the gate
electrode of the third n type transistor, a source electrode
connected to the first power supply, and a drain electrode being
the second inverted output terminal.
8. The semiconductor integrated circuit according to claim 3,
wherein the first current addition device has an output terminal
being connected to the first non-inverted output terminal of the
first differential amplification circuit and the second inverted
output terminal of the second differential amplification circuit,
and wherein the second current addition device has an output
terminal being connected the second non-inverted output terminal of
the second differential amplification circuit and the first
inverted output terminal of the first differential amplification
circuit.
9. The semiconductor integrated circuit according to claim 4,
wherein the first current addition device has an output terminal
being connected to the first non-inverted output terminal of the
first differential amplification circuit and the second inverted
output terminal of the second differential amplification circuit,
and wherein the second current addition device has an output
terminal being connected the second non-inverted output terminal of
the second differential amplification circuit and the first
inverted output terminal of the first differential amplification
circuit.
10. The semiconductor integrated circuit according to claim 3,
wherein the output stage control device includes: sixth and seventh
n type transistors having each source electrode connected to the
first power supply, and each gate electrode connected to the output
terminal of the second current addition device; and sixth and
seventh p type transistors having each source electrode connected
to the second power supply, each gate electrode connected to the
output terminal of the first current addition device, and each
drain electrode connected to each drain electrode of the sixth and
a seventh n type transistors respectively, and wherein the output
stage includes: an eighth n type transistor having a source
electrode connected to the first power supply, a drain electrode
connected the output terminal, and a gate electrode connected to
the drain electrode of the sixth n type transistor, and; an eighth
p type transistor having a source electrode is connected to the
second power supply, a drain electrode connected the output
terminal, and a gate electrode connected to a drain electrode of
the seventh p type transistor.
11. The semiconductor integrated circuit according to claim 3,
wherein the output stage control device includes: sixth and seventh
n type transistors having each source electrode connected to the
first power supply, and each gate electrode connected to the output
terminal of the second current addition device; sixth and seventh p
type transistors having each source electrode connected to the
second power supply, each gate electrode connected to the output
terminal of the first current addition device, and each drain
electrode connected to each drain electrode of the sixth and a
seventh n type transistors respectively; an eighth n type
transistor having a source electrode connected to a drain electrode
of the seventh n type transistor, and a drain electrode connected
to a drain electrode of the seventh p type transistor; an eighth p
type transistor having a source electrode connected to a drain
electrode of the sixth p type transistor, and a drain electrode
connected to a drain electrode of the sixth n type transistor; and
a gate voltage control circuit having a first output terminal
connected to a gate electrode of the eighth n type transistor and a
second output terminal connected to a gate electrode of the eighth
p type transistor to control each gate voltage respectively, and
wherein the output stage includes: a ninth n type transistor having
a source electrode connected to the first power supply, a drain
electrode connected the output terminal, and a gate electrode
connected to the drain electrode of the sixth n type transistor,
and; a ninth p type transistor having a source electrode is
connected to the second power supply, a drain electrode connected
the output terminal, and a gate electrode connected to a drain
electrode of the seventh p type transistor.
12. The semiconductor integrated circuit according to claim 3,
wherein the output stage control device includes: a sixth n type
transistors having a source electrode connected in series with a
third resister to the first power supply, and a gate electrode
connected to the output terminal of the second current addition
device; a sixth p type transistors having a source electrode
connected in series with a fourth resister to the second power
supply, and a gate electrode connected to the output terminal of
the first current addition device; a seventh n type transistor
having a source electrode connected to a drain electrode of the
sixth n type transistor, and a drain electrode connected to a drain
electrode of the sixth p type transistor; a seventh p type
transistor having a source electrode connected to the drain
electrode of the sixth p type transistor, and a drain electrode
connected to the drain electrode of the sixth n type transistor;
and a gate voltage control circuit having a first output terminal
connected to a gate electrode of the seventh n type transistor and
a second output terminal connected to a gate electrode of the
seventh p type transistor to control each gate voltage
respectively, and wherein the output stage includes: an eighth n
type transistor having a source electrode connected to the first
power supply, a drain electrode connected the output terminal, and
a gate electrode connected to the drain electrode of the sixth n
type transistor, and; an eighth p type transistor having a source
electrode is connected to the second power supply, a drain
electrode connected the output terminal, and a gate electrode
connected to a drain electrode of the sixth p type transistor.
13. The semiconductor integrated circuit according to claim 11,
wherein the gate voltage control circuit includes: a tenth n type
transistor having a drain electrode and a gate electrode connected
to the first output terminal, an eleventh n type transistor having
a drain electrode and a gate electrode connected to a source
electrode of the tenth n type transistor, and a source electrode
connected to the first power supply, a tenth p type transistor
having a drain electrode and a gate electrode connected to the
second output terminal, an eleventh p type transistor having a
drain electrode and a gate electrode connected to a source
electrode of the tenth p type transistor, and a source electrode
connected to the second power supply, a third current source having
one terminal connected to the drain electrode of the tenth n type
transistor, and an opposite side terminal connected to the drain
electrode of the tenth p type transistor.
14. The semiconductor integrated circuit according to claim 12,
wherein the gate voltage control circuit includes: a tenth n type
transistor having a drain electrode and a gate electrode connected
to the first output terminal, an eleventh n type transistor having
a drain electrode and a gate electrode connected to a source
electrode of the tenth n type transistor, and a source electrode
connected to the first power supply, a tenth p type transistor
having a drain electrode and a gate electrode connected to the
second output terminal, an eleventh p type transistor having a
drain electrode and a gate electrode connected to a source
electrode of the tenth p type transistor, and a source electrode
connected to the second power supply, a third current source having
one terminal connected to the drain electrode of the tenth n type
transistor, and an opposite side terminal connected to the drain
electrode of the tenth p type transistor.
15. The semiconductor integrated circuit according to claim 4,
wherein the output stage control device includes: a seventh n type
transistor having a gate electrode connected to the first bias
voltage terminal, and a source electrode connected to the first
power supply; an eighth n type transistors having a source
electrode connected to a drain electrode of the seventh n type
transistor, and a gate electrode connected to the output terminal
of the second current addition device; a seventh p type transistor
having a gate electrode connected to the second bias voltage
terminal, and a source electrode connected to the second power
supply; an eighth p type transistors having a source electrode
connected to a drain electrode of the seventh p type transistor,
and a gate electrode connected to the output terminal of the first
current addition device; a ninth n type transistor having a gate
electrode connected to the first bias voltage terminal, a source
electrode connected to a drain electrode of the eighth n type
transistor, and a drain electrode connected to a drain electrode of
the eighth p type transistor; and a ninth p type transistor having
a gate electrode connected to the second bias voltage terminal, a
source electrode connected to the drain electrode of the eighth p
type transistor, and a drain electrode connected to the drain
electrode of the eighth n type transistor, and wherein the output
stage includes: a tenth n type transistor having a source electrode
connected to the first power supply, a drain electrode connected
the output terminal, and a gate electrode connected to the drain
electrode of the eighth n type transistor, and; a tenth p type
transistor having a source electrode is connected to the second
power supply, a drain electrode connected the output terminal, and
a gate electrode connected to a drain electrode of the eighth p
type transistor.
16. The semiconductor integrated circuit according to claim 10,
further including a first phase compensation circuit having a first
condenser connecting between the drain electrode and the gate
electrode of the eighth n type transistor, and a second phase
compensation circuit having a second condenser connecting between
the drain electrode and the gate electrode of the eighth p type
transistor.
17. The semiconductor integrated circuit according to claim 11,
further including a first phase compensation circuit having a first
condenser connecting between the drain electrode of the ninth n
type transistor and the gate electrode of the eighth p type
transistor, and a second phase compensation circuit having a second
condenser connecting between the drain electrode of the ninth p
type transistor and the gate electrode of the eighth n type
transistor.
18. The semiconductor integrated circuit according to claim 12,
further including a first phase compensation circuit having a first
condenser connecting between the drain electrode of the eighth n
type transistor and the gate electrode of the sixth p type
transistor, and a second phase compensation circuit having a second
condenser connecting between the drain electrode of the eighth p
type transistor and the gate electrode of the sixth n type
transistor.
19. The semiconductor integrated circuit according to claim 15,
further including a first phase compensation circuit having a first
condenser connecting between the drain electrode of the tenth n
type transistor and the gate electrode of the eighth n type
transistor, and a second phase compensation circuit having a second
condenser connecting between the drain electrode of the tenth p
type transistor and the gate electrode of the eighth p type
transistor.
Description
CROSS REFERENCE TO RELATED APPLICATION
[0001] This patent application claims the benefit of priority from
Japanese Patent Application No. 2004-172157, filed on Jun. 10,
2004; the content of which is incorporated herein by reference in
its entirety.
FIELD OF THE INVENTION
[0002] This invention relates to a semiconductor integrated circuit
including an output amplifier.
DESCRIPTION OF THE BACKGROUND
[0003] Displaying an LCD (Liquid Crystal Display) is controlled by
an LCD driver. An output stage of the driver has an output
amplifier for an output signal. It is often suitable to use a
Rail-to-Rail amplifier whose output amplitude swings fully in the
power supply voltage range as the output amplifier.
[0004] U.S. Pat. No. 5,311,145 issued May 10, 1994 describes a
circuit of an amplifier which performs Rail-to-Rail operation
including a differential amplifier.
[0005] In addition, since high-speed operation is also required of
an LCD driver, an amplifier having a high Slew Rate (SR) is
needed.
[0006] An article described by T. Itakura et al. entitled, "A
402-Output TFT-LCD Driver IC With Power Control Based on the Number
of Colors Selected" in the IEEE JSSC, vol.38, No3, March 2003,
p.503-510, describes a circuit of an amplifier which has SR
Enhancement. This SR Enhancement contains a Class-C amplifier which
operates during a falling edge of an output signal.
[0007] However, the SR Enhancement has a problem of distorting a
signal waveform generated at end of the falling edge. A Class-C
amplifier switches off at the falling edge of an output signal, and
the above problem is occurred because a driving force of an
amplifier declines rapidly.
[0008] In addition, it is necessary to insert a condenser between a
drain and a gate of an output transistor for phase compensation of
an output amplifier. In order to obtain sufficient phase
compensation, this condenser needs comparatively large capacity.
However, in order to obtain a high SR, it is necessary to flow
large charge and discharge current to the condenser. As a result a
power consumption of the amplifier becomes large. This is a serious
problem for example, in a portable apparatus for which low power
consumption operation is needed.
SUMMARY OF THE INVENTION
[0009] One aspect of the present invention is to provide a
semiconductor integrated circuit that comprises a first
differential amplification device with a first polarity, the first
differential amplification device being configured to amplify a
voltage difference of two input signals inputted from a positive
input terminal and a negative input terminal respectively, a second
differential amplification device with a second polarity opposite
of the first polarity, the second differential amplification device
being configured to amplify the voltage difference of two input
signals inputted from the positive input terminal and the negative
input terminal respectively, a first addition device configured to
add a non-inverted output of the first differential amplification
device and an inverted output of the second differential
amplification device, a second addition device configured to add a
non-inverted output of the second differential amplification device
and an inverted output of the first differential amplification
device, an output stage control device having first and second
switching elements, the first switching element with the first
polarity controlled by an output signal of the second addition
device, and the second switching element with the second polarity
controlled by an output signal of the first addition device, an
output stage having a third switching element with the first
polarity controlled by an output signal of the first switching
element of the output stage control device, and a fourth switching
element with the second polarity controlled by an output signal of
the second switching element of the output stage control device,
and an output terminal configured to be connected to an output
terminal of the third switching element and an output terminal of
the fourth switching element in common.
[0010] One aspect of the present invention is to provide a
semiconductor integrated circuit that comprises a positive input
terminal, a negative input terminal, a first differential
amplification circuit with a first polarity having a first positive
input terminal connected to the positive input terminal, a first
negative input terminal connected to the negative input terminal, a
first non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the first positive input terminal
and the first negative input terminal, and a first inverted output
terminal outputting an inverted output signal being inverted signal
of the output signal of the first non-inverted output terminal, a
second differential amplification circuit with a second polarity
opposite of the first polarity, having a second positive input
terminal connected to the positive input terminal, a second
negative input terminal connected to the negative input terminal, a
second non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the second positive-input terminal
and the second negative input terminal, and a second inverted
output terminal outputting an inverted output signal being inverted
signal of the output signal of the second non-inverted output
terminal, a first current addition device configured to add a
current, the current being configured to flow at the first
non-inverted output terminal of the first differential
amplification circuit and a current, the current being configured
to flow at the second inverted output terminal of the second
differential amplification circuit, a second current addition
device configured to add a current, the current being configured to
flow at the second non-inverted output terminal of the second
differential amplification circuit and a current, the current being
configured to flow at the first inverted output terminal of the
first differential amplification circuit, an output stage control
device having a first switching element with the first polarity
having a control terminal connected to an output terminal of the
second current addition device, and a second switching element with
the second polarity having a control terminal connected to an
output terminal of the first current addition device, an output
stage having a third switching element with the first polarity
having a control terminal connected to an output terminal of the
first switching element, and a fourth switching element with the
second polarity having a control terminal connected to an output
terminal of the second switching element, an output terminal
configured to be connected an output terminal of the third
switching element and an output terminal of the fourth switching
element in common, a first phase compensation circuit connecting
between the output terminal of the third switching element and the
control terminal of the third switching element, and a second phase
compensation circuit connecting between the output terminal of the
fourth switching element and the control terminal of the fourth
switching element.
[0011] One aspect of the present invention is to provide a
semiconductor integrated circuit that comprises a first bias
voltage terminal, a second bias voltage terminal, a positive input
terminal, a negative input terminal, a first differential
amplification circuit with a first polarity having a first positive
input terminal connected to the positive input terminal, a first
negative input terminal connected to the negative input terminal, a
first non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the first positive input terminal
and the first negative input terminal, and a first inverted output
terminal outputting an inverted output signal being inverted signal
of the output signal of the first non-inverted output terminal, a
second differential amplification circuit with a second polarity
opposite of the first polarity, having a second positive input
terminal connected to the positive input terminal, a second
negative input terminal connected to the negative input terminal, a
second non-inverted output terminal configured to output an output
signal, the output signal being amplified a voltage difference of
two input signals inputted from the second positive-input terminal
and the second negative input terminal, and a second inverted
output terminal outputting an inverted output signal being inverted
signal of the output signal of the second non-inverted output
terminal, a first current addition device configured to add a
current, the current being configured to flow at the first
non-inverted output terminal of the first differential
amplification circuit and a current, the current being configured
to flow at the second inverted output terminal of the second
differential amplification circuit, a second current addition
device configured to add a current, the current being configured to
flow at the second non-inverted output terminal of the second
differential amplification circuit and a current, the current being
configured to flow at the first inverted output terminal of the
first differential amplification circuit, an output stage control
device having a first switching element with the first polarity
having a control terminal connected to an output terminal of the
second current addition device, a second switching element with the
second polarity having a control terminal connected to an output
terminal of the first current addition device, a third switching
element controlling an output voltage of the second switching
element with the first polarity having a control terminal connected
to the first bias voltage terminal, and a fourth switching element
controlling an output voltage of the first switching element with
the second polarity having a control terminal connected to the
second bias voltage terminal, an output stage having a fifth
switching element with the first polarity having a control terminal
connected to an output terminal of the first switching element, and
a sixth switching element with the second polarity having a control
terminal connected to an output terminal of the second switching
element, an output terminal configured to be connected an output
terminal of the fifth switching element and an output terminal of
the sixth switching element in common, a first phase compensation
circuit connecting between the output of the fifth switching
element terminal and the control terminal of the fifth switching
element, and a second phase compensation circuit connecting between
the output terminal of the sixth switching element and the control
terminal of the sixth switching element.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a circuit diagram showing a first embodiment of a
semiconductor integrated circuit including an output amplifier
according to the present invention.
[0013] FIG. 2 is a circuit diagram showing a second embodiment of a
semiconductor integrated circuit including an output amplifier
according to the present invention.
[0014] FIG. 3 is a circuit diagram showing a third embodiment of a
semiconductor integrated circuit including an output amplifier
according to the present invention.
[0015] FIG. 4 is a circuit diagram showing a fourth embodiment of a
semiconductor integrated circuit including an output amplifier
according to the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0016] Exemplary embodiments of the present invention will be
explained in reference to the drawing as follows.
[0017] FIG. 1 is a circuit diagram of a semiconductor integrated
circuit including an output amplifier concerning a first embodiment
in accordance with the present invention.
[0018] Output amplifier 10 includes two input terminals (positive
input terminal 14, negative input terminal 15), output terminal 16,
differential amplification circuit 11, output stage control circuit
20, and output stage 30.
[0019] Differential amplification circuit 11 includes N type
differential amplification circuit 12 having n channel transistors
forming an input stage, and P type differential amplification
circuit 13 having p channel transistors.
[0020] If first power supply 1 is set to 0V and second power supply
2 is set to 5V, N type differential amplification circuit 12
carries out differential amplification operation within the range
of 1V to 5V, and P type differential amplification circuit 13
carries out differential amplification operation within the range
of 0V to 4V. Therefore, it can amplify Rail to Rail of 0V to 5V by
combining these two differential amplification circuits.
[0021] N type differential amplification circuit 12 has n type MOS
transistors M1 and M2, p type MOS transistors M3 and M4, and
current source I1.
[0022] P type differential amplification circuit 13 has p type MOS
transistors M5 and M6, n type MOS transistors M7 and M8, and
current source I2.
[0023] Positive input terminal (+input terminal) 14 is connected to
a gate electrode of n type MOS transistor M2 of N type differential
amplification circuit 12, and a gate electrode of p type MOS
transistor M6 of P type differential amplification circuit 13,
respectively.
[0024] Similarly, negative input terminal (-input terminal) 15 is
connected to a gate electrode of n type MOS transistor M1 of N type
differential amplification circuit 12, and a gate electrode of p
type MOS transistor M5 of P type differential amplification circuit
13, respectively.
[0025] An inverted output current of N type differential
amplification circuit 12 flows through p type MOS transistor M4. A
drain electrode of p type MOS transistor M9 which forms first
current mirror circuit CM1 with p type MOS transistor M4 is
connected to non-inverted output terminal 18 of P type differential
amplification circuit 13.
[0026] An inverted output current of P type differential
amplification circuit 13 flows through n type MOS transistor M8. A
drain electrode of an n type MOS transistor M10 which forms second
current mirror circuit CM2 with n type MOS transistor M8 is
connected to non-inverted output terminal 17 of N type differential
amplification circuit 12.
[0027] Output stage control circuit 20 includes two p type MOS
transistors M11 and M12 and two n type MOS transistors M13 and
M14.
[0028] Both gate electrodes of p type MOS transistors M11 and M12
are connected to non-inverted output terminal 17 of N type
differential amplification circuit 12, and both source electrodes
of p type MOS transistors M11 and M12 are connected to second power
supply 2.
[0029] Both gate electrodes of n type MOS transistors M13 and M14
are connected to non-inverted output terminal 18 of P type
differential amplification circuit 13, and both source electrodes
of n type MOS transistors M13 and M14 are connected to first power
supply 1.
[0030] A drain electrode of p type MOS transistor M11 is connected
to a drain electrode of n type MOS transistor M13, and a drain
electrode of p type MOS transistor M12 is connected to a drain
electrode of n type MOS transistor M14.
[0031] As shown in FIG. 1, output stage 30 includes n type MOS
transistor M15 and p type MOS transistor M16.
[0032] N type MOS transistor M15 has a source electrode connected
to first power supply 1, and a drain electrode connected to a drain
electrode of p type MOS transistor M16.
[0033] A source electrode of p type MOS transistor M16 is connected
to second power supply 2.
[0034] A gate electrode of n type MOS transistor M15 is connected
to a drain electrode of n type MOS transistor M13 of output control
circuit 20.
[0035] Similarly, a gate electrode of p type MOS transistor M16 is
connected to a drain electrode of p type MOS transistor M12 of
output stage control circuit 20.
[0036] The drain electrode of n type MOS transistor M15 and the
drain electrode of p type MOS transistor M16 of output stage 30 are
connected in common to output terminal 16 of output amplifier
10.
[0037] First phase compensation condenser C1 is inserted between
the drain electrode and the gate electrode of n type MOS transistor
M15, and second phase compensation condenser C2 is inserted between
the drain electrode and the gate electrode of p type MOS transistor
M16.
[0038] Next, signal processing of output amplifier 10 of the
embodiment shown in FIG. 1 is explained.
[0039] A difference between a voltage inputted from +input terminal
14 and a voltage inputted from -input terminal 15 is amplified by N
type differential amplification circuit 12, and is outputted from
the drain electrode of p type MOS transistor M3.
[0040] Similarly, a difference between a voltage inputted from
+input terminal 14 and a voltage inputted from -input terminal 15
is amplified by P type differential amplification circuit 13, and
is outputted from the drain electrode of n type MOS transistor
M7.
[0041] An inverted output current of N type differential
amplification circuit 12 flows through p type MOS transistor
M4.
[0042] A drain current of p type MOS transistor M9, which
constitutes first current mirror circuit CM1 with p type MOS
transistor M4, is an inverted output signal of N type differential
amplification circuit 12.
[0043] Since the drain electrode of p type MOS transistor M9 is
connected to the drain electrode of n type MOS transistor M7 which
is non-inverted output terminal 18 of P type differential
amplification circuit 13, an inverted output current of N type
differential amplification circuit 12 can be added to a
non-inverted output current of P type differential amplification
circuit 13.
[0044] Similarly, the inverted output current of P type
differential amplification circuit 13 flows through n type MOS
transistor M8.
[0045] A drain current of n type MOS transistor M10, which
constitutes second current mirror circuit CM2 with n type MOS
transistor M8 in FIG. 1, is an inverted output signal of P type
differential amplification circuit 13.
[0046] Since the drain electrode of n type MOS transistor M10 is
connected to the drain electrode of p type MOS transistor M3, which
is non-inverted output terminal 17 of N type differential
amplification circuit 12, an inverted output current of P type
differential amplification circuit 13 can be added to a
non-inverted output current of N type differential amplification
circuit 12.
[0047] Two output signals that results of the addition described
above are inputted into output stage control circuit 20.
[0048] P type MOS transistors M11 and M12 are controlled not only
by the non-inverted output signal of N type differential
amplification circuit 12 but also by an inverted output signal of P
type differential amplification circuit 13.
[0049] Similarly, n type MOS transistors M13 and M14 are controlled
not only by the non-inverted output signal of P type differential
amplification circuit 13 but also by the inverted output signal of
N type differential amplification circuit 12.
[0050] N type MOS transistor M15 and p type MOS transistor M16
constitute output stage 30. Then n type MOS transistor M15 is
controlled by the drain voltage of n type MOS transistor M13
inputted into the gate electrode. And p type MOS transistor M16 is
controlled by the drain voltage of the drain voltage of p type MOS
transistor M12 inputted into the gate electrode.
[0051] That is, n type MOS transistor M15 and p type MOS transistor
M16 may be controlled by tuning a current ratio of the current
mirror circuit of p type MOS transistors M3, M11, and M12, and the
current mirror circuit of n type MOS transistors M7, M13, and M14
finely, respectively.
[0052] In the embodiment illustrated in FIG. 1, both output signals
of N type differential amplification circuit 12 and P type
differential amplification circuit 13 are used as direct control
signals not only to p type MOS transistor M16 but also to n type
MOS transistor M15 of output stage 30, so linear control of output
stage 30 may be realized.
[0053] Thus, it is not necessary to use the Enhancement circuit
which performs Class-C operation for control of one output
transistor in a conventional technology, and it is not necessary to
boost current, which has been done in the conventional
technology.
[0054] As a result, distortion of an output waveform by switching
of Class-C operation may be avoided.
[0055] FIG. 2 shows a second embodiment of a circuit diagram of a
semiconductor integrated circuit including an output amplifier, in
accordance with the present invention.
[0056] In the second embodiment, similar to the first embodiment
described above, output amplifier 10 includes two input terminals
(positive input terminal 14, negative input terminal 15), output
terminal 16, differential amplification circuit 11, and output
stage 30. And output amplifier 10 also includes output stage
control circuit 120.
[0057] Since a structure of differential amplification circuit 11,
first and second current mirror circuits CM1 and CM2 shown in FIG.
2 are the same as those of the first embodiment shown in FIG. 1,
explanation of these parts is omitted.
[0058] In the embodiment shown in FIG. 2, output stage control
circuit 120 has three p type MOS transistors M11, M12, and M17,
three n type MOS transistors M13, M14, and M18, and gate voltage
control circuit 40.
[0059] Both gate electrodes of p type MOS transistors M11 and M12
are connected to non-inverted output terminal 17 of N type
differential amplification circuit 12, and both source electrodes
of p type MOS transistors M11 and M12 are connected to second power
supply 2.
[0060] Both gate electrodes of n type MOS transistors M13 and M14
are connected to non-inverted output terminal 18 of P type
differential amplification circuit 13, and both source electrodes
of n type MOS transistors M13 and M14 are connected to first power
supply 1.
[0061] P type MOS transistor M17 has a source electrode connected
to the drain electrode of p type MOS transistor M11, and a drain
electrode connected to a drain electrode of n type MOS transistor
M13.
[0062] N type MOS transistor M18 has a source electrode connected
to a drain electrode of p type MOS transistor M12, and a drain
electrode connected to a drain electrode of n type MOS transistor
M14.
[0063] Each gate electrode of p type MOS transistor M17 and n type
MOS transistor M18 is connected to gate voltage control circuit
40.
[0064] Gate voltage control circuit 40 consists of p type MOS
transistors M19 and M20, n type MOS transistors M21 and M22, and
current source I3.
[0065] P type MOS transistor M19 has a source electrode connected
to second power supply 2, and a drain electrode connected to a
source electrode of p type MOS transistor M20. A drain electrode of
p type MOS transistor M20 is connected to one terminal of current
source I3.
[0066] N type MOS transistor M21 has a drain electrode connected to
the opposite side terminal of current source 13, and a source
electrode connected to a source electrode of n type MOS transistor
M22. A source electrode of n type MOS transistor M22 is connected
to first power supply 1.
[0067] Each gate electrode of p type MOS transistors M19 and M20
and n type MOS transistors M21 and M22 is connected to the own
drain electrode of each transistor.
[0068] A gate electrode of p type MOS transistor M17 is connected
to the drain electrode of p type MOS transistor M20, and a gate
electrode of n type MOS transistor M18 is connected to the drain
electrode of n type MOS transistor M21.
[0069] Output stage 30 has n type MOS transistor M15 and p type MOS
transistor M16.
[0070] N type MOS transistor M15 has a source electrode connected
to first power supply 1, and a drain electrode connected to a drain
electrode of p type MOS transistor M16. A source electrode of p
type MOS transistor M16 is connected to second power supply 2.
[0071] The drain electrode of n type MOS transistor M15 and the
drain electrode of p type MOS transistor M16 of output stage 30 are
both connected to output terminal 16 of output amplifier 110.
[0072] As shown in FIG. 2, first phase compensation condenser C1 is
inserted between the drain electrode of n type MOS transistor M15
and the source electrode of p type MOS transistor M17. Second phase
compensation condenser C2 is inserted between the drain electrode
of p type MOS transistor M16 and the source electrode of n type MOS
transistor M18.
[0073] Therefore, a phase compensation circuit of n type MOS
transistor M15 includes first phase compensation condenser C1 and p
type MOS transistor M17. And, a phase compensation circuit of p
type MOS transistor M16 includes second phase compensation
condenser C2 and n type MOS transistor M18.
[0074] Next, signal processing of output amplifier 110 of the
second embodiment is explained.
[0075] As in the first embodiment shown in FIG. 1, a difference
between a voltage inputted from +input terminal 14 and a voltage
inputted from -input terminal 15 is amplified by N type
differential amplification circuit 12, and is outputted from the
drain electrode of p type MOS transistor M3.
[0076] Similarly, a difference between a voltage inputted from
+input terminal 14 and a voltage inputted from -input terminal 15
is amplified by P type differential amplification circuit 13, and
is outputted from the drain electrode of n type MOS transistor
M7.
[0077] An inverted-output current of N type differential
amplification circuit 12 flows through p type MOS transistor
M4.
[0078] A drain current of p type MOS transistor M9, which
constitutes first current mirror circuit CM1 with p type MOS
transistor M4, is an inverted output signal of N type differential
amplification circuit 12.
[0079] Since the drain electrode of p type MOS transistor M9 is
connected to the drain electrode of n type MOS transistor M7 which
is non-inverted output terminal 18 of P type differential
amplification circuit 13, an inverted output current of N type
differential amplification circuit 12 can be added to a
non-inverted output current of P type differential amplification
circuit 13.
[0080] Similarly, the inverted output current of P type
differential amplification circuit 13 flows through n type MOS
transistor M8.
[0081] A drain current of n type MOS transistor M10, which
constitutes second current mirror circuit CM2 with n type MOS
transistor M8, is an inverted output signal of P type differential
amplification circuit 13.
[0082] Since the drain electrode of n type MOS transistor M10 is
connected to the drain electrode of p type MOS transistor M3, which
is non-inverted output terminal 17 of N type differential
amplification circuit 12, an inverted output current of P type
differential amplification circuit 13 can be added to a
non-inverted output current of N type differential amplification
circuit 12.
[0083] Two output signals that are results of the addition
described above are inputted into output stage control circuit
120.
[0084] P type MOS transistors M1 and M12 are controlled not only by
the non-inverted output signal of N type differential amplification
circuit 12 but also by an inverted output signal of P type
differential amplification circuit 13.
[0085] Similarly, n type MOS transistors M13 and M14 are controlled
not only by the non-inverted output signal of P type differential
amplification circuit 13 but also by the inverted output signal of
N type differential amplification circuit 12.
[0086] N type MOS transistor M15 of output stage 30 is controlled
by the gate voltage inputted from the drain of n type MOS
transistor M13. And the drain voltage of n type MOS transistor M13
is controlled by controlling of the gate voltage of n type MOS
transistor M17.
[0087] Similarly, p type MOS transistor M16 of output stage 30 is
controlled by the gate voltage inputted from the drain of p type
MOS transistor M12. And the drain voltage of p type MOS transistor
M12 is controlled by controlling a gate voltage of n type MOS
transistor M18.
[0088] Therefore, the voltage inputted to the gate electrode of n
type MOS transistor M15 can be controlled by the gate voltage of p
type MOS transistor M17. And the voltage inputted to the gate
electrode of p type MOS transistor M16 can be controlled by the
gate voltage of n type MOS transistor M18.
[0089] Each gate voltage of p type MOS transistor M17 and n type
MOS transistor M18 is controlled by gate voltage control circuit
40.
[0090] The gate voltage inputted to the gate electrode of p type
MOS transistor M17 is the voltage of the drain electrode of p type
MOS transistor M20. Similarly, the gate voltage inputted to the
gate electrode of n type MOS transistor M18 is the voltage of the
drain electrode of n type MOS transistor M21.
[0091] When the output amplifier 110 is used as a voltage follower
and +input terminal 14 and -input terminal 15 have same potential,
each drain current of n type MOS transistors M13 and M14 is almost
the same as each drain current of p type MOS transistors M11 and
M12, and they will be stable in DC operation.
[0092] In this stable DC condition, a source-gate voltage V.sub.GS
between each gate and each source of n type MOS transistor M15 and
p type MOS transistor M16 which constitute output stage 30 may be
defined as Va.
[0093] In this case, since a drain-source voltage V.sub.DS between
the drain and the source of n type MOS transistor M13 is Va,
V.sub.DS of p type MOS transistor M12 is expressed as (VDD-Va)
(when first power supply 1 is set to 0V, and second power supply 2
is set to VDD.).
[0094] When current source I3 is controlled so that gate voltage
control circuit 40 becomes stable in DC operation, all of V.sub.GS
of p type MOS transistors M19 and M20 and n type MOS transistors
M21 and M22 are Va.
[0095] Then, a drain voltage of p type MOS transistor M20 becomes
(VDD-Va-Va)=(VDD-2Va), and is inputted to the gate electrode of p
type MOS transistor M17.
[0096] Since V.sub.DS of p type MOS transistor M17 which is stable
in DC is also Va, a drain voltage of p type MOS transistor M11
becomes (VDD-2Va)+Va=(VDD-Va). Therefore, V.sub.DS of p type MOS
transistor M11 becomes VDD-(VDD-Va)=Va.
[0097] Similarly, a drain voltage of n type MOS transistor M21
becomes Va+Va=2Va, and is inputted to the gate electrode of n type
MOS transistor M18.
[0098] Since V.sub.DS of n type MOS transistor M18 which is stable
in DC is also Va, a drain voltage of n type MOS transistor M14
becomes 2Va-Va=Va. Therefore, V.sub.DS of n type MOS transistor M14
becomes Va.
[0099] Since both V.sub.DS of p type MOS transistor M11 and
V.sub.DS of n type MOS transistor M14 become Va, a voltage balance
between two output terminals of output stage control circuit 120 is
maintained, and stable voltages can be given to output stage
30.
[0100] Considering a case where there are not p type MOS transistor
M17 and n type MOS transistor M18 in output stage control circuit
120, V.sub.DS of n type MOS transistor M14 may be VDD-Va, and
V.sub.DS of p type MOS transistor M11 may be Va. Then, in this
case, it may be necessary to tune a current ratio of the current
mirror circuit of p type MOS transistors M3, M11, and M12, and the
current mirror circuit of n type MOS transistors M7, M13, and M14
finely.
[0101] On the other hand, p type MOS transistor M17 and n type MOS
transistor M18 which are equipped in output stage control circuit
120 work to keep the output of output stage 30 stable, so it may
not be necessary to adjust the current ratio of p type MOS
transistors M11 and M12 and n type MOS transistors M13 and M14.
[0102] Then, phase compensation of n type MOS transistor M15 is
determined by a combination of first phase compensation condenser
C1 and p type MOS transistor M17. Therefore, since phase
compensation is controllable not only by the capacity of first
phase compensation condenser C1 but also the resistance of p type
MOS transistor M17, it becomes possible to decrease a capacity of
first phase compensation condenser C1.
[0103] Similarly, also in phase compensation of p type MOS
transistor M16, the capacity of second phase compensation condenser
C2 can be decreased.
[0104] Therefore, a current of operation is reducible by decreasing
the capacity of first and second phase compensation condensers C1
and C2.
[0105] Moreover, similar to the first embodiment described above,
both output signals of N type differential amplification circuit 12
and P type differential amplification circuit 13 are used as direct
control signals also not only to p type MOS transistor M16 but also
to n type MOS transistor M15 of output stage 30, so linear control
of output stage 30 may be realized.
[0106] In addition, gate voltage control circuit 40 is not
restricted to this mentioned circuit. What is necessary is just to
be able to control p type MOS transistor M17 and n type MOS
transistor M18 like this embodiment.
[0107] FIG. 3 is a circuit diagram of a semiconductor integrated
circuit including an output amplifier according to a third
embodiment.
[0108] Output amplifier 210 of the third embodiment includes two
input terminals (positive input terminal 14, negative input
terminal 15), output terminal 16, differential amplification
circuit 211, output stage control circuit 220, and output stage
30.
[0109] Since a structure of gate voltage control circuit 40, first
and second current mirror circuits CM1 and CM2 shown in FIG. 3 are
the same as those of the second embodiment shown in FIG. 2,
detailed explanation of these parts is omitted.
[0110] Differential amplification circuit 211 of this embodiment
includes N type differential amplification circuit 212 and P type
differential amplification circuit 213. Although, as for N type
differential amplification circuit 212, n type MOS transistor M7 is
connected to first power supply 1 through resistance R2 unlike N
type differential amplification circuit 12 of the second
embodiment, the operation is similar to that of N type differential
amplification circuit 12. And, although, as for P type differential
amplification circuit 213, p type MOS transistor M3 is connected to
first power supply 2 through resistance R1 unlike P type
differential amplification circuit 13 of the second embodiment, the
operation is similar to that of P type differential amplification
circuit 13. Then, detailed explanation of differential
amplification circuit 211 is omitted.
[0111] On the other hand, as for output stage control circuit 220
of this embodiment, the circuit composition differs from output
stage control circuit 120 of the second embodiment. Output stage
control circuit 120 has the circuit for controlling n type MOS
transistor M15 and p type MOS transistor M16 which constitute the
output stage 30, respectively. However, output stage control
circuit 220 has a circuit for controlling n type MOS transistor M15
and p type MOS transistor M16 in common.
[0112] In this exemplary embodiment, output stage control circuit
220 includes a source electrode of p type MOS transistor M17 and a
drain electrode of n type MOS transistor M18 connected to a drain
electrode of p type MOS transistor M11, having a gate electrode is
connected to non-inverted output terminal 17 of N type differential
amplification circuit 212. And a drain electrode of p type MOS
transistor M17 and a source electrode of n type MOS transistor M18
and a drain electrode of n type MOS transistor M18 are connected
common to a drain electrode of n type MOS transistor M13, having a
gate electrode is connected to non-inverted output terminal 18 of P
type differential amplification circuit 213.
[0113] Then, the drain electrode of p type MOS transistor M11 is
connected to a gate electrode of p type MOS transistor M16 of
output stage 30, and the drain electrode of n type MOS transistor
M13 is connected to a gate electrode of n type MOS transistor M15
of output stage 30.
[0114] On the other hand, a gate electrode of p type MOS transistor
M17 and a gate electrode of the n type MOS transistor M18 are
connected to a drain electrode of p type MOS transistor M20 of gate
voltage control circuit 40, and a drain electrode of n type MOS
transistor M21 respectively as well as the second embodiment.
[0115] In addition, in this embodiment, a source electrode of p
type MOS transistor M11 and a source electrode of p type MOS
transistor M3, which constitutes a current mirror circuit with p
type MOS transistor M11 are connected in series with resisters R3
and R1 to second power supply 2, respectively.
[0116] Similarly, a source electrode of n type MOS transistor M13
and a source electrode of n type MOS transistor M7, which
constitutes a current mirror circuit with n type MOS transistor M13
are connected in series with resisters R4 and R2 to first power
supply 1, respectively.
[0117] These resisters R1-R4 may suppress change of the
characteristic of current mirror circuits by variation in
thresholds of transistors.
[0118] Moreover, in this embodiment, first phase compensation
condenser C1 is inserted between a drain electrode of n type MOS
transistor M15 and the source electrode of n type MOS transistor
M13, and second phase compensation condenser C2 is inserted between
a drain electrode of p type MOS transistor M16 and a source
electrode of p type MOS transistor M11.
[0119] Therefore, a phase compensation circuit of n type MOS
transistor M15 includes first phase compensation condenser C1 and n
type MOS transistor M13. And, a phase compensation circuit of p
type MOS transistor M16 includes second phase compensation
condenser C2 and p type MOS transistor M11.
[0120] Also in operation of this embodiment, a voltage inputted to
the gate electrode of n type MOS transistor M15 may be controlled
by a gate voltage of p type MOS transistor M17, and a voltage
inputted to the gate electrode of p type MOS transistor M16 is
controlled by gate voltage of n type MOS transistor M18. Therefore,
output stage 30 of this embodiment may also operate stably.
[0121] In this embodiment, since the number of transistors which
constitute output stage control circuit 220 can be reduced, a
consumption current of a semiconductor integrated circuit can be
lessened.
[0122] Moreover, phase compensation in this embodiment is performed
with first phase compensation condenser C1 and n type MOS
transistor M13, and also with second phase compensation condenser
C2 and a p type MOS transistor M11.
[0123] Therefore, phase compensation is controllable also by a
resistance value of n type MOS transistor M13 and a resistance
value of p type MOS transistor M11. Accordingly, also in this
embodiment, each capacity of first and second phase compensation
condensers C1 and C2 can be decreased.
[0124] FIG. 4 illustrates a circuit diagram of a semiconductor
integrated circuit including an output amplifier according to a
fourth embodiment.
[0125] Output amplifier 310 of the fourth embodiment, similar to
the third embodiment shown in FIG. 3, includes two input terminals
(positive input terminal 14, negative input terminal 15), output
terminal 16, differential amplification circuit 311, output stage
control circuit 320, and output stage 30. And output amplifier 310
includes more two input terminals (bias voltage terminal 50, bias
voltage terminal 60). With respect to each portion of this
embodiment, the same portion of the third embodiment is designated
by the same numeral, and its detailed explanation is omitted.
[0126] Differential amplification circuit 311 of this embodiment
includes N type differential amplification circuit 312 and P type
differential amplification circuit 313. Although, as for N type
differential amplification circuit 312, n type MOS transistor M7 is
connected to first power supply 1 through n type MOS transistor M24
unlike N type differential amplification circuit 212 of the third
embodiment, the operation is similar to that of N type differential
amplification circuit 212. And, although, as for P type
differential amplification circuit 313, p type MOS transistor M3 is
connected to first power supply 2 through p type MOS transistor M23
unlike P type differential amplification circuit 213 of the third
embodiment, the operation is similar to that of P type differential
amplification circuit 13. Then, detailed explanation of
differential amplification circuit 311 is omitted.
[0127] On the other hand, unlike the third embodiment, output stage
control circuit 320 may not contain a gate voltage control circuit
40 being included in output stage control circuit 220 of the third
embodiment.
[0128] Instead, output amplifier 310 is equipped a bias voltage
terminal 50 and a bias voltage terminal 60 as external terminals.
Then, bias voltage terminal 50 provides a bias voltage for n type
MOS transistors, and bias voltage terminal 60 provides a bias
voltage for p type MOS transistors, respectively.
[0129] A gate electrode of p type MOS transistor M17 of output
stage control circuit 320 is connected to bias voltage terminal 60,
and a gate electrode of p type MOS transistor M18 is connected to
bias voltage terminal 50. Moreover, the fourth embodiment includes
p type MOS transistors M23 and M25, instead of resisters R1 and R3
of the third embodiment, having each gate electrode is connected to
bias voltage terminal 60, and also includes n type MOS transistors
M24 and M26, instead of resisters R2 and R4 of the third
embodiment, having each gate electrode is connected to bias voltage
terminal 50.
[0130] Accordingly, a drain electrode of p type MOS transistor M23
is connected to a source electrode of a p type MOS transistor M3,
and a source electrode of p type MOS transistor M23 is connected to
second power supply 2. A drain electrode of p type MOS transistor
M25 is connected to a source electrode of a p type MOS transistor
M11, and a source electrode of p type MOS transistor M25 is
connected to second power supply 2.
[0131] Similarly, a drain electrode of n type MOS transistor M24 is
connected to a source electrode of an n type MOS transistor M7, and
a source electrode of n type MOS transistor M24 is connected to
first power supply 1. A drain electrode of n type MOS transistor
M26 is connected to a source electrode of an n type MOS transistor
M13, and a source electrode of n type MOS transistor M26 is
connected to first power supply 1.
[0132] Each `ON` resistance of these p type MOS transistors M23 and
M25 and n type MOS transistors M24 and M26 is used instead of each
resistance of resisters R1-R4 being used in the third
embodiment.
[0133] In this embodiment, similar to the third embodiment, first
phase compensation condenser C1 is disposed between a drain
electrode of n type MOS transistor M15 and the source electrode of
n type MOS transistor M13, and second phase compensation condenser
C2 is disposed between a drain electrode of p type MOS transistor
M16 and the source electrode of p type MOS transistor M11.
[0134] Therefore, a phase compensation circuit of n type MOS
transistor M15 has first phase compensation condenser C1 and n type
MOS transistor M13. And a phase compensation circuit of p type MOS
transistor M16 has second phase compensation condenser C2 and p
type MOS transistor M11.
[0135] Also in operation of this embodiment, a voltage inputted to
a gate electrode of n type MOS transistor M15 is controlled by a
gate voltage of p type MOS transistor M17, and a voltage inputted
to a gate electrode of p type MOS transistor M16 is controlled by a
gate voltage n type MOS transistor M18. Therefore, output stage 30
of this embodiment also operates stably.
[0136] According to this embodiment, since gate voltage control
circuit 40 is not built in, the number of transistors which
constitute output amplifier 310 can be reduced. Generally, an LCD
driver may typically require many output amplifiers of the same
composition to drive many pixels of an LCD simultaneously.
Therefore, using output amplifier 10 of this embodiment brings the
effect of decreasing markedly a transistor count to an integrated
circuit for such an LCD driver.
[0137] Moreover, in this embodiment, since p type MOS transistors
M23 and M25 and n type transistor M24 and M26 are used as
resistance elements, a chip area of such integrated circuit can be
greatly small rather than it forms a resistance element by a
poly-silicon layer, etc.
* * * * *