U.S. patent application number 10/189339 was filed with the patent office on 2005-01-27 for arrangement for energy conditioning.
Invention is credited to Anthony, Anthony A. JR., Anthony, William M..
Application Number | 20050016761 10/189339 |
Document ID | / |
Family ID | 34084958 |
Filed Date | 2005-01-27 |
United States Patent
Application |
20050016761 |
Kind Code |
A9 |
Anthony, Anthony A. JR. ; et
al. |
January 27, 2005 |
Arrangement for energy conditioning
Abstract
Circuit arrangement embodiments that use relative groupings of
energy pathways that include shielding circuit arrangements that
can sustain and condition electrically complementary energy
confluences.
Inventors: |
Anthony, Anthony A. JR.;
(Erie, PA) ; Anthony, William M.; (Erie,
PA) |
Correspondence
Address: |
NEIFELD IP LAW, PC
2001 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
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Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 0029632 A1 |
February 13, 2003 |
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Family ID: |
34084958 |
Appl. No.: |
10/189339 |
Filed: |
July 2, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10189339 |
Jul 2, 2002 |
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10115159 |
Apr 2, 2002 |
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10115159 |
Apr 2, 2002 |
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09845680 |
Apr 30, 2001 |
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6580595 |
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09845680 |
Apr 30, 2001 |
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09815246 |
Mar 22, 2001 |
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6469595 |
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09815246 |
Mar 22, 2001 |
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09777021 |
Feb 5, 2001 |
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6687108 |
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09777021 |
Feb 5, 2001 |
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09632048 |
Aug 3, 2000 |
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6738249 |
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09632048 |
Aug 3, 2000 |
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09594447 |
Jun 15, 2000 |
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6636406 |
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09594447 |
Jun 15, 2000 |
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09579606 |
May 26, 2000 |
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6373673 |
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09579606 |
May 26, 2000 |
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09460218 |
Dec 13, 1999 |
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6331926 |
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09460218 |
Dec 13, 1999 |
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09056379 |
Apr 7, 1998 |
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6018448 |
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09056379 |
Apr 7, 1998 |
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09008769 |
Jan 19, 1998 |
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6097581 |
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09008769 |
Jan 19, 1998 |
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08841940 |
Apr 8, 1997 |
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5909350 |
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60302429 |
Jul 2, 2001 |
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60310962 |
Aug 8, 2001 |
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60349954 |
Jan 18, 2002 |
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60388388 |
Jun 12, 2002 |
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Current U.S.
Class: |
174/250 ;
174/261; 174/262; 333/12; 361/794 |
Current CPC
Class: |
H01L 2924/12042
20130101; H01L 2924/30107 20130101; H01L 2924/3025 20130101; H01L
2224/16235 20130101; H01L 2924/3011 20130101; H01L 2924/12042
20130101; H01L 24/16 20130101; H01L 2924/3011 20130101; H05K 1/0231
20130101; H01L 2924/30107 20130101; H05K 2201/086 20130101; H01L
2924/00 20130101; H01L 23/552 20130101; H01L 2924/00 20130101; H01L
2924/00 20130101; H01L 2924/3025 20130101; H01L 2924/10253
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2224/48235 20130101; H05K 1/0233 20130101; H01L 24/48 20130101;
H01L 2924/10253 20130101; H01L 2924/14 20130101 |
Class at
Publication: |
174/250 ;
174/261; 174/262; 361/794; 333/012 |
International
Class: |
H05K 007/06; H05K
009/00 |
Claims
1. A device, comprising: at least a first and a second plurality of
pathways; wherein said first plurality further comprises at least:
two pathways arranged electrically isolated from each other and
orientated in a first complementary relationship; wherein at least
a first number of pathways of said second plurality is arranged
electrically isolated from a second number of pathways of said
second plurality; and wherein the at least two pathways of said
second plurality are electrically isolated from said first
plurality.
2. The device of claim 1, wherein at least two pathways of said
first number of pathways of said second plurality are electrically
coupled to one another; and wherein at least two pathways of said
second number of pathways of said second plurality are electrically
coupled to one another.
3. The device of claim 1, wherein said first number of pathways of
said second plurality is an odd number greater than one; wherein
said second number of pathways of said second plurality is an odd
number greater than one; wherein at least two pathways of said
first number of pathways of said second plurality are electrically
coupled to one another; and wherein at least two pathways of said
second number of pathways of said second plurality are electrically
coupled to one another.
4. The device of claim 1, further comprising a spacing material
that at least spaces apart two pathways of said circuit.
5. The device of claim 4, wherein said spacing material comprises a
dielectric.
6. The device of claim 1, wherein said first number of pathways of
said second plurality are in a first alignment; and wherein said
second number of pathways of said second plurality are in a second
alignment.
7. The device of claim 1, wherein said first number of pathways of
said second plurality are in a first superposed alignment; and
wherein said second number of pathways of said second plurality are
in a second superposed alignment.
8. The device of claim 6, wherein the first alignment and the
second alignment are in a superposed alignment.
9. The device of claim 7, wherein the first and the second
superposed alignment are in position at least one on top of the
other.
10. The device of claim 1, wherein at least two pathways of said
first number of pathways are arranged electrically coupled to one
another in a first alignment; wherein at least two pathways of said
second number of pathways are arranged electrically coupled to one
another in a second alignment; wherein said first number of
pathways is an odd number of pathways greater than one, and wherein
said second number of pathways is an odd number of pathways greater
than one; and wherein a total number of pathways of said first
plurality is at least an even number greater than two.
11. The device of claim 1, wherein at least two pathways of said
first number of pathways of said second plurality are arranged in a
first superposed alignment electrically coupled to one another;
wherein at least two pathways of said second number of pathways of
said second plurality are arranged in a second superposed alignment
electrically coupled to one another; wherein a total number of
pathways of second plurality is an odd number greater than one; and
wherein a total number of pathways of said first plurality is pat
least an even number greater than two.
12. The device of claim 10, further comprising a spacing material
that at least spaces apart pathways of said circuit
arrangement.
13. The device of claim 11, wherein four pathways of the circuit
arrangement are electrically isolated from one another.
14. The device of claim 1, wherein said first plurality of pathways
is a plurality of shielded pathways; and wherein said second
plurality of pathways is a plurality of shielding pathways.
15. An electrical arrangement comprising: at least a first and a
second plurality of pathways; wherein the first plurality includes
at least one pair of pathways electrically isolated from each other
and arranged in mutual complementary position; wherein at least a
first number of pathways of said second plurality is arranged
electrically isolated from a second number of pathways of said
second plurality, and wherein said second plurality includes at
least two pathways electrically isolated from said first plurality;
wherein at least two pathways of said first number of pathways of
said second plurality are electrically coupled to one another; and
wherein at least two pathways of said second number of pathways of
said second plurality are electrically coupled to one another.
16. The electrical arrangement of claim 15, further comprising a
spacing material that at least spaces apart pathways of said
circuit arrangement.
17. The electrical arrangement of claim 15, wherein at least four
pathways of the circuit arrangement are electrically isolated from
one another.
18. The electrical arrangement of claim 15, wherein at least sip:
pathways of the circuit arrangement are electrically isolated from
one another.
19. The electrical arrangement of claim 15, wherein said second
plurality includes at least two pathways arranged co-planar to one
another; and wherein at least four pathways of the circuit
arrangement are electrically isolated from one another.
20. The electrical arrangement of claim 15, wherein said second
plurality includes at least two pathways arranged co-planar to one
another; and wherein at least four pathways of the circuit
arrangement are electrically isolated from one another.
21. The electrical arrangement of claim 15, wherein said first and
said second plurality are arranged in a non co-planar stacking;
and
21. The electrical arrangement of claim 15, wherein said first and
said second plurality are arranged in a non co-planar stacking; and
wherein four pathways of the circuit arrangement are electrically
isolated from one another.
22. The electrical arrangement of claim 15, wherein said first
plurality of pathways comprises a plurality of vias; and wherein
said second plurality of pathways is a plurality of shielding
pathways.
23. A device comprising: at least four pluralities of pathways;
wherein only respective pathways of each one plurality of said
pluralities are electrically coupled to one another; and wherein at
least two pluralities of said at least four pluralities provide
shielding for at least two other pluralities of said at least four
pluralities of pathways.
24. A device comprising: at least a first, a second, a third and a
four plurality of pathways; wherein only respective pathways of
each said plurality are electrically coupled to one another;
wherein said first plurality shields said second plurality; and
wherein said third plurality shields said fourth plurality.
25. A circuit arrangement comprising: at least a first and a second
plurality of shielding pathways; at least a first and a second
plurality of shielded pathways; and wherein said shielding pathways
and said shielded pathways are alternately arranged within said
circuit arrangement; wherein only respective pathways of each said
plurality are electrically coupled to one another; and wherein each
of said pluralities of said circuit arrangement are electrically
isolated from one another.
26. A system, comprising: an integrated circuit package having at
least one integrated circuit; a plurality of pathways conductively
coupled together; a first plurality of shields conductively coupled
together; a second plurality of shields conductively coupled
together and electrically isolated from at least said first
plurality; and wherein each of said shields and said pathways are
alternately arranged, and wherein said shields develop at least one
low impedance pathway suitable for energy propagation away from
said integrated circuit; and wherein said pathways develop a low
inductance pathway suitable for energy propagation within said
integrated circuit package, said energy propagation being
conditioned by at least said plurality of shields.
27. The system of claim 26, wherein said first and said second
pluralities of shields are respectively in a substantially coplanar
relationship.
28. The system of claim 26, wherein said first and said second
pluralities of shields are respectively in a substantially coplanar
relationship.
29. The system of claim 26, wherein one of said first or said
second plurality of shields comprises a centering one of said
shields, and wherein said first arid said second pluralities of
shields and said pathways are arranged in a substantially balanced
and complementary symmetrical arrangement about said centering
one.
30. The system of claim 26, wherein one of said first or said
second plurality of shields comprises a centering one of said
shields, and wherein said first and said second pluralities of
shields and said pathways are substantially aligned about said
centering one.
31. The system of claim 26, wherein each of said first plurality
and said second plurality of shields comprises an odd number of
shields.
Description
[0001] This application is a continuation-in-part of co-pending
application Ser. No. 10/115,159, filed Apr. 2, 2002, which is a
continuation-in-part of co-pending application Ser. No. 09/845,680,
filed Apr. 30, 2001, which is a continuation-in-part of co-pending
application Ser. No. 09/815,246 filed Mar. 22, 2001, which is a
continuation-in-part of co-pending application Ser. No. 09/777,021
filed Feb. 5, 2001, which is a continuation-in-part of co-pending
application Ser. No. 09/594,447 filed Aug. 3, 2000, which is a
continuation-in-part of co-pending application Ser. No. 09/594,447
filed Jun. 15, 2000, which is a continuation-in-part of co-pending
application Ser. No. 09/579,606 filed May 26, 2000, now issued as
U.S. Pat. No. 6,373,673, which is a continuation-in-part of
co-pending application Ser. No. 09/460,218 filed Dec. 13, 1999, now
issued as U.S. Pat. No. 6,331,926, which is a continuation of
application Ser. No. 09/056,379 filed Apr. 7, 1998, now issued as
U.S. Pat. No. 6,018,448, which is a continuation-in-part of
application Ser. No. 09/008,769 filed Jan. 19, 1998, now issued as
U.S. Pat. No. 6,097,581, which is a continuation-in-part of
application Ser. No. 08/841,940 filed Apr. 8, 1997, now issued as
U.S. Pat. No. 5,909,350.
TECHNICAL FIELD
[0002] In addition, this application claims the benefit of U.S.
Provisional Application No. 60/302,429, filed Jul. 2, 2001, U.S.
Provisional Application No. 60/310,962, filed Aug. 8, 2001, U.S.
Provisional Application No. 60/349,954, filed Jan. 8, 2002, and
U.S. Provisional Application No. (Not assigned), filed Jun. 12,
2002.
[0003] This application relates to balanced shielding arrangements
that use complementary relative groupings of energy pathways, such
as pathways for various energy propagations for multiple energy
conditioning functions. These shielding arrangements may be
operable as discrete or non-discrete embodiments that can sustain
and condition electrically complementary energy confluences.
BACKGROUND
[0004] Today, as the density of electronics within applications
increases, unwanted noise byproducts of the increased density may
limit the performance electronic circuitry. Consequently, the
avoidance of the effects of unwanted noise byproducts, such as by
isolation or immunization of circuits against the effects of the
undesirable noise is an important consideration for circuit
arrangements and circuit design.
[0005] Differential and common mode noise energy may be generated
by, and may propagate along or around, energy pathways, cables,
circuit board tracks or traces, high-speed transmission lines,
and/or bus line pathways. These energy conductors may act as, for
example, an antenna that radiates energy fields. This
antenna-analogous performance may exacerbate the noise problem in
that, at higher frequencies, propagating energy utilizing prior art
passive devices may experience increased levels of energy parasitic
interference, such as various capacitive and/or inductive
parasitics.
[0006] These increases may be due, in part, to the combination of
constraints resulting from functionally or structurally limitations
of prior art solutions, coupled with the inherent manufacturing or
design imbalances and performance deficiencies of the prior art.
These deficiencies inherently create, or induce, unwanted and
unbalanced interference energy that may couple into associated
electrical circuitry, thereby making at least partial shielding
from these parasitics and electromagnetic interference desirable.
Consequently, for broad frequency operating environments, solving
these problems necessitates at least a combination of simultaneous
filtration, careful systems layout having various grounding or
anti-noise arrangements, as well as extensive isolating in
combination with at least partial electrostatic and electromagnetic
shielding.
[0007] Thus, a need exists for a self-contained,
energy-conditioning arrangement utilizing simplified energy pathway
arrangements, which may additionally include other elements,
amalgamated into a discreet or non-discreet component, which may be
utilized in almost any circuit application for providing effective,
symmetrically balanced, and sustainable, simultaneous energy
conditioning functions selected from at least a decoupling
function, transient suppression function, noise cancellation
function, energy blocking function, and energy suppression
functions.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Understanding of the present invention will be facilitated
by consideration of the following detailed description of the
preferred embodiments of the present invention taken in conjunction
with the accompanying drawings, in which like numerals refer to
like parts and in which:
[0009] FIG. 1 is a relative location compass operable for
determining relative locations of the various pathway extensions
disclosed;
[0010] FIGS. 1A-1C show relative locations of the various pathway
extensions disclosed according to an aspect of the present
invention;
[0011] FIG. 2A shows a circuit schematic of the plan view of an
embodiment of 2B according to an aspect of the resent
invention;
[0012] FIG. 2B is a plan view of an embodiment according to an
aspect of the present invention;
[0013] FIG. 3A shows a circuit schematic of the plan view of an
embodiment of 3B according to an aspect of the present
invention;
[0014] FIG. 3B is a plan view of an embodiment according to an
aspect of the present invention;
[0015] FIG. 3C shows a plan view of a shield according to an aspect
of the present invention;
[0016] FIG. 4A shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0017] FIG. 4B shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0018] FIG. 4C shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0019] FIG. 4D shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0020] FIG. 4E shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0021] FIG. 4F shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0022] FIG. 4G shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0023] FIG. 4H shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0024] FIG. 4I shows a relative plan view of an embodiment
according to an aspect of the present invention;
[0025] FIG. 5A shows a stacked multiple, circuit network including
groups of pathways according to an aspect of the present
invention;
[0026] FIG. 5B shows a stacked shield according to an aspect of the
present invention;
[0027] FIG. 5C shows a relative plan view of a stacked multiple,
non-shared circuit network having VIAs including groups of pathways
according to an aspect of the present invention;
[0028] FIG. 6 shows a relative plan view of circuit arrangement
variant according to an aspect of the present invention; and,
[0029] FIG. 7 shows a relative plan view of circuit arrangement
variant according to an aspect of the present invention;
DETAILED DESCRIPTION
[0030] This application is a continuation-in-part of co-pending
application Ser. No. 10/115,159, filed Apr. 2, 2002, which is a
continuation-in-part of co-pending application Ser. No. 09/845,680,
filed Apr. 30, 2001, which is a continuation-in-part of co-pending
application Ser. No. 09/815,246 filed Mar. 22, 2001, which is a
continuation-in-part of co-pending application Ser. No. 09/777,021
filed Feb. 5, 2001, which is a continuation-in-part of co-pending
application Ser. No. 09/594,447 filed Aug. 3, 2000, which is a
continuation-in-part of co-pending application Ser. No. 09/594,447
filed Jun. 15, 2000, which is a continuation-in-part of co-pending
application Ser. No. 09/579,606 filed May 26, 2000, now issued as
U.S. Pat. No. 6,373,673, which is a continuation-in-part of
co-pending application Ser. No. 09/460,218 filed Dec. 13, 1999, now
issued as U.S. Pat. No. 6,331,926, which is a continuation of
application Ser. No. 09/056,379 filed Apr. 7, 1998, now issued as
U.S. Pat. No. 6,018,448, which is a continuation-in-part of
application Ser. No. 09/008,769 filed Jan. 19, 1998, now issued as
U.S. Pat. No. 6,097,581, which is a continuation-in-part of
application Ser. No. 08/841,940 filed Apr. 8, 1997, now issued as
U.S. Pat. No. 5,909,350, each of which is incorporated by reference
herein.
[0031] In addition, this application claims the benefit of U.S.
Provisional Application No. 60/302,429, filed Jul. 2, 2001, U.S.
Provisional Application No. 60/310,962, filed Aug. 8, 2001, U.S.
Provisional Application No. 60/349,954, filed Jan. 8, 2002, and
U.S. Provisional Application No. (Not assigned), filed Jun. 12,
2002, each of which is incorporated by reference herein.
[0032] It is to be understood that the figures and descriptions of
the present invention have been simplified to illustrate elements
that are relevant for a clear understanding of the present
invention, while eliminating, for the purpose of clarity, many
other elements found in typical energy conditioning systems and
methods. Those of ordinary skill in the art will recognize that
other elements and/or steps are desirable and/or required in
implementing the present invention. However, because such elements
and steps are well known in the art, and because they do not
facilitate a better understanding of the present invention, a
discussion of such elements and steps is not provided herein. The
disclosure herein is directed to all such variations and
modifications to such elements and methods known to those skilled
in the art. Additionally, it will be apparent to those skilled in
the art that terms used herein that may include a whole, or a
portion of a whole, such as "energy", "system", circuit, and the
like, are contemplated to include both the portions of the whole,
and the entire of the whole, as used, unless otherwise noted.
[0033] As used herein, an "energy pathway" or "pathway" may be at
least one, or a number, of conductive materials, each one operable
for sustained propagation of energy. Pathways may be conductive,
thereby better propagating various electrical energies as compared
to non-conductive or semi-conductive materials directly or
indirectly coupled to, or adjacent to, the pathways. An energy
pathway may facilitate propagation of a first energy by allowing
for various energy conditioning functions, such as conditioning
functions arising due to any one or a number of aspects, such as,
but not limited to, the shielding, the orientation and/or the
positioning of the energy pathways within the energy pathway
arrangement, which various arrangements having an orientation
and/or positioning thereby allow for interaction of the first
energy with propagating energies that are complementary to at least
the first energy. An energy pathway may include an energy pathway
portion, an entire energy pathway, a conductor, an energy
conductor, an electrode, at least one process-created conductor,
and/or a shield. A plurality of energy pathways may include a
plurality of each device or element discussed hereinabove with
respect to energy pathway. Further, as used generally herein, a
conductor may include, for example, an individual conductive
material portion, a conductive plane, a conductive pathway, a
pathway, an electrical wire, a via, an aperture, a conductive
portion such as a resistive lead, a conductive material portion, or
an electrical plate, such as plates separated by at least one
medium 801, for example.
[0034] A shield may include a shielding electrode, a shielding
pathway portion, a shielded pathway, a shielded conductor, a
shielded energy conductor, a shielded electrode, and/or at least
one process-created shielded pathway portion. A plurality of
shields may include a plurality of the devices discussed
hereinabove with respect to a shield.
[0035] As used generally herein, a pathway may be complementary
positioned, or complementary orientated, with respect to a
main-body 80, 81, having various pathway extensions, designated
79"X", 812"X", 811"X" and 99"X". Main-bodies 80, 81 may be in
three-dimensional physical relationships individually, in pairs,
groups, and/or pluralities as to distance, orientation, position,
superposition, non-superposition, alignment, partial alignment,
lapping, non-lapping, and partial lapping. Superposed main-body
pathway 80, may, for example include a pairing of physically
opposing and oppositely orientated main-body pathways 80 that are
any one of, or any combination of, electrically null, electrically
complementary, electrically differential, or electrically
opposite.
[0036] A pathway arrangement may include at least a shield at least
partially shielding at least one energy pathway, or a group of
shields forming a shield structure that at least partially
shielding, via a conductive shielding, at least a conductively
isolated pairing of at least two energy pathways, such as vias,
apertures or complementary paired pathways.
[0037] An exemplary embodiment may allow energy propagation on a
conductively isolated pairing, such as complementary paired
pathways, causing energy propagation on common shields, or at least
one grouping of shields, serving an isolated circuit. This
embodiment may allow a low inductance pathway to form among at
least a single pair of isolated and separate parallel pathways
serving at least one separate and distinct isolated circuit system.
An exemplary embodiment may allow for the development of at least
low inductance pathway for utilization of energy propagating on at
least one parallel pathway of at least two sets of isolated and
separate parallel pathways and the development along at least one
parallel pathway of at least one other low inductance pathway for
utilization of energy propagating along at least one other separate
and distinct isolated circuit system.
[0038] An exemplary embodiment utilized as part of a circuit
assembly may have at least one pathway of relatively lower
inductance, while other pathways may be electrically coupled to an
energy source or an energy load. A pathway of a second plurality of
pathways may have a lower impedance operable for portions of energy
to be taken away from either of the same at least one energy source
or at least one energy load of the circuit assembly. This same
pathway of low impedance may not be electrically directly coupled
to either the same at least one energy source or at least one
energy load of the circuit assembly as the one pathway of lower
inductance. A system may have both a pathway of least inductance
and a pathway of least impedance which are not the same
pathway.
[0039] In contrast to capacitors found in the industry wherein an
equivalent series inductance (ESL) of a capacitor device is
normally size dependant, in the present invention the pathway of
least impedance and the pathway of least inductance for a circuit
for energy conditioning may be achieved independent of the physical
size of the device. These aspects depend on a predetermined
capacitance developed by a predetermined layers in the present
invention.
[0040] Arranging the pathways allows the resistance of the
conductive material of the pathways to primarily determine the
energy delivery, or relative efficiency or effect between at least
one source of energy and one energy utilizing load of an integrated
circuit, for example. The ESL may be a negligible factor, rather
than a primary factor for delivery outcome or decoupling void of
debilitating inductances.
[0041] In an illustrative pathway arrangement illustrated in FIGS.
1A, 1B, 1C, 5A and 5B, wherein the various propagating energies may
be complementary, the pathway arrangement, upon placement into a
circuit arrangement, may allow for energy propagation within or
along certain energy pathways of the pathway arrangement, thereby
allowing for the mutual interaction of opposite portions of
pathway-soured magnetic fields produced by the propagation of
energy field currents emanating outwardly from each set of the
complementary conductors. This mutual interaction maybe a mutual
cancellation in embodiments wherein certain pathways may be
partially or totally physically shielded from other complementary
pathways, and may be placed within an influencing distance of those
other complementary pathways. Further, a substantial similarity in
size and shape of the respective complementary pathways, including
the spaced-apart relationship and the interpositioning of a
shielding between pathways, and the conductively isolated
relationship of the pathways, may contribute to this mutual
cancellation effect. Additionally, the shielding operations may be
predicated on a relative positioning of a mating of the paired
pathways relative to the conductive electrostatic shielding. At
least the complementary energy conditioning functions and
electrostatic shielding dynamics discussed herein may operate on
various energy propagating in various directions along various
predetermined pathways, and may operate on circuits having dynamic
operation utilizing the pathway arrangement.
[0042] A sub-combination of electromagnetically/electrostatically
actuated impedance states may develop along or within a pathway
arrangement, or along or within a closely coupled external
conductive portion conductively coupled to separate or multiple
groupings of shields, to thereby form an energy conditioning
circuit. These electromagnetically/electrostatically actuated
impedance states may develop, for example, because of the
energization of one paired set of pathways of one circuit portion,
but not necessarily develop on another paired set of pathways from
another circuit portion, for example.
[0043] According to an aspect of the present invention, each shield
may include a main-body 81. Main-bodies 81 may collectively and
conductively couple to one another and at the same time may
substantially immure and shield the main-body 80 of the energy
pathways. In other embodiments of the present invention, the
collective shielding main-body 81 may only partially immure or
shield the pathway main-body 80s in at least one portion of the
shielding.
[0044] According to an aspect of the present invention, a balanced,
symmetrical, pathway arrangement may result from the symmetry of
certain superposed shields, from complementary pathway sizing and
shaping, and/or from reciprocal positioning and pairing of the
complementary pathways. Manufacturable balanced or symmetrical
physical arrangements of pathways, wherein dynamic energy
propagation, interactions, pairings or match-ups of various dynamic
quantities occur, may operate at less than a fundamental limit of
accuracy of testing equipment. Thus, when portions of these
complementary energy quantities interact simultaneously, the energy
may be beyond the quantifiable range of the typical testing
equipment. Thus, the extent to which the measurement may be
obtained may employ increased controllability, and thereby the
electrical characteristics and the effect on electrical
characteristics may be controlled, such as by predetermining the
desired measurability, behavior or enhancement to be provided, and
by a correspondent arrangement of the elements, such as
specifically by an arrangement of the elements to provide the
desired measurability or effect. For example, a desired electrical
characteristic may be predetermined for a desired enhancement by
varying at least a portion of the complementary balance, size,
shape, and symmetry of at least one pathway paring, as set forth
herein below and as illustrated in FIGS. 1A, 1B, 1C, 5A and 5B, for
example.
[0045] Thus, the extent of energy interactions, mutual energy
propagation timings and interferences, for example, may be
controlled by tolerances within the pathway arrangement. A
manufacturing process, or computer tolerance control, such as
semiconductor process control, may control these tolerances, for
example. Thus, the pathways of an embodiment may be formed using
manufacturing processes, such as passive device processes, apparent
to those skilled in the art. Mutual energy propagation measurements
may thereby be cancelled or suppressed by the formation, and
process of formation, of the pathway arrangement.
[0046] A pathway arrangement may, as set forth hereinabove, include
a sequentially positioned grouping of pathways in an amalgamated
electronic structure having balanced groupings of pathways. The
balanced grouping may include a predetermined pathway architecture
having a stacked hierarchy of pathways that are symmetrical and
complementary in number, and that are positioned complementary to
one another, thereby forming pairs, each of which pair is
substantially equidistant from each side of a centrally positioned
shield, wherein each shield may provide a symmetrical balancing
point for both each pair pathway and the overall pathway hierarchy
as depicted in FIGS. 1A to 4I, for example. Thus, predetermined
identically sized, shaped and complementary positioned pathways may
be present on either side of a centrally positioned shield for each
separate circuit portion. A total circuit may have its
complementary portions symmetrically divided into a complementary
physical format including a reverse-mirror image positioning of
paired shielded, complementary sized and shaped pathways,
sandwiching at least one interposing shield.
[0047] According to an aspect of the present invention, each
pathway may be, for example, a first interconnect substrate
wrapping around, or holding, an integrated circuit wafer, a
deposit, an etching, or a resultant of a doping process, and the
shield may be, for example, a pathway substrate, an energy
conditioning embodiment or energy conditioning substrate, a
deposit, an etching, a resultant of a doping process, and may have,
for example, resistive properties. Additional elements may be
utilized, including conductive and nonconductive elements, between
the various pathways. These additional elements may take the form
of ferromagnetic materials or ferromagnetic-like dielectric layers,
and/or inductive-ferrite dielectric derivative materials.
Additional pathway structural elements may be utilized, including
conductive and nonconductive multiple pathways of different
conductive material compositions, conductive magnetic
field-influencing material hybrids and conductive polymer sheets,
various processed conductive and nonconductive laminates, straight
conductive deposits, multiple shielding pathway pathways utilizing
various types of magnetic material shields and selective shielding,
and conductively doped and conductively deposited on the materials
and termination solder, for example, in addition to various
combinations of material and structural elements, to provide a host
of energy conditioning options.
[0048] Non-conductor materials may also provide structural support
of the various pathways, and these non-conductor materials may aid
the overall energized circuit in maintaining the simultaneous,
constant and uninterrupted energy propagation moving along the
pathways. Dielectric materials for example, may include one or more
layers of material elements compatible with available processing
technology. These dielectric materials may be a semiconductor
material such as silicon, germanium, gallium arsenide, or a
semi-insulating and insulating material such as, but not limited to
any K, high K and low K dielectrics.
[0049] Pathway and conductor materials may be selected from a group
consisting of Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd and other such
conductive materials and metals. Combinations of these metal
materials are suitable for the purposes discussed herein, and may
include appropriate metal oxides, such as ruthenium oxide, which,
depending on the exigencies of a particular application, may be
diluted with a suitable metal. Other pathways may be formed of a
substantially non-resistive conductive material. Any substances and
processes that may create pathways from conductive, non-conductive,
semi-conductive material, and/or Mylar films printed circuit board
materials, or any substances or processes that may create
conductive areas such as doped polysilicons, sintered
polycrystallines, metals, polysilicon silicates, or polysilicon
silicide may be used within or with the pathway arrangement.
[0050] An exemplary embodiment of the present invention may utilize
an internal shield structural architecture to insure energy
balancing configurations within the various arrangements, rather
than a specific external circuit balance. This balancing
configuration is dependent upon the relative positioning of all the
shields in relationship to the shared and centrally positioned
shield, and the actual paired shields positioned in specific
quantities, to simultaneously provide shielding for the
electrically opposing shielded paired pathways utilized by
propagating energy. This allows these electrically opposing
complementary pathways to be located both electrically and
physically on the opposite sides of the centrally positioned and
shared common conductive shield. This interposition of the central
and shared shields may create a voltage divider that divides
various circuit voltages in half and that provides, to each of the
oppositely paired shielded conductors, one half of the voltage
energy normally expected. The energized circuitry, including
shielded conductors, may be balanced electrically or in a
charge-opposing manner and with respect to a centrally positioned
shield, to a common and shared pathway, or to each respective,
isolated circuit system portion. Each common circuit member of an
isolated circuit system may be attached or coupled to a common area
or common pathway, thereby providing an external common zero
voltage. Thus, the embodiment may have multiple sets of shields
electrically or physically located between at least one of the
various electrically or charge opposing, shielded pairs or grouped
complementary pairs of pathways in an interposed shielding
relationship, supported with additional outer sandwiching shields,
designated herein as--IM that are additionally coupled and, in
part, form the shielding structure.
[0051] An exemplary embodiment may also be placed into one or more
energy circuits that utilize different energy sources and that may
supply one or more separate and distinct energy-utilizing loads.
When energized for multiple energy conditioning operations and for
providing simultaneous and effective energy conditioning functions,
such as electromagnetic interference filtering, suppression, energy
decoupling and energy surge protection, each separate and distinct
circuit is utilizing the multiple commonly shared universal shield
structure and circuit reference image, or node.
[0052] According to an aspect of the present invention,
energy-conditioning functions may maintain an apparent balanced
energy voltage reference and energy supply for each respective
energy-utilizing load within a circuit. This energized arrangement
may allow for specific energy propagation utilizing a single, or
multiple, isolated pathway arrangement, and may not require
balancing on a single, centralized shield. A shield may be
physically and electrically located between one or multiple energy
sources and one or multiple energy utilizing loads, depending upon
the number of separate and isolated pathways. Thus shielding
relative, centralized pathways may be in both co-planar and stacked
variants of exemplary embodiment.
[0053] When the internally positioned paired shielded pathways are
subsequently attached, or conductively coupled, to externally
manufactured pathways, the internally positioned paired shields may
be substantially enveloped within the cage-like shield structure,
thereby minimizing internally generated energy strays and
parasitics that may normally escape or couple to an adjacent
shielded pathway. These shielding modes utilize propagating energy
to the various pathways and may be separate of the electrostatic
shield effect created by the energization of the shield structure.
The propagating energy propagating in a complementary manner
provides energy fields of mutually opposed, mutually cancelled
fields as a result of the close proximity of opposite propagation.
The complementary and paired pathways may provide an internally
balanced opposing resistance load function.
[0054] A device according to an aspect of the present invention may
mimic the functionality of at least one electrostatically shielded
transformer. Transformers may be widely used to provide common mode
isolation dependent upon a differential mode transfer across the
inputs in order to magnetically link the primary windings to the
secondary windings to transfer energy. As a result, common mode
voltage across the primary winding is rejected. One flaw inherent
in the manufacturing of transformers is the propagating energy
source capacitance between the primary and secondary windings. As
the frequency of the circuit increases, so does capacitive
coupling, until circuit isolation may be compromised. If enough
parasitic capacitance exists, high frequency RF energy may pass
through the transformer and cause an upset in the circuits on the
other side of the isolation gap subjected to the transient event. A
shield may be provided between the primary and secondary windings
by coupling to a common pathway reference source designed to
prevent capacitive coupling between the multiple sets of windings.
A device according to an aspect of the present invention improves
upon, and reduces the need for, transformers in circuits. The
device may use a physical and relative, common pathway shield to
suppress parasitics and also may use relative positioning of common
pathway shields, a complementary paired pathway layering, the
various couplings of the pathway layering, and an external
conductive coupling to a conductive area per isolated circuit
system, in combination with the various external circuitry, to
effectively function as a transformer. If an isolated circuit
system is upset by transients, the electrostatically shielded,
transformer function of the device discussed herein may be
effective for transient suppression and protection, and may
simultaneously operate as a combined differential mode and common
mode filter. Each set of relative shields and relative conductors
may be conductively coupled to at least the same external pathway
to provide a transformer functionality for example,
[0055] Propagated electromagnetic interference may be the product
of both electric and magnetic fields. A device according to an
aspect of the present invention may be capable of conditioning
energy that uses DC, AC, and AC/DC hybrid-type propagation,
including conditioning energy in systems that may contain different
types of energy propagation formats and in systems that may contain
more than one circuit propagation characteristic.
[0056] In an exemplary embodiment, perimeter conductive coupling
material for coupling or connecting, by conductive joining, of
external portions of a typical embodiment into an assembly may be
accomplished by conductive or non-conductive attachments to various
types of angled, parallel or perpendicular, as those terms apply
relative to at least another pathway, conductors known as apertures
or blind or non-blind VIAs, passing through, or almost through,
portions respectively of an exemplary embodiment. Couplings to at
least one or more load(s), such as a portion of an integrated
circuit, for one aspect of the invention may involve a selective
coupling, or not, to these various types of conductors, such as
apertures and VIAs.
[0057] Fabricating a pathway may include forming one or more plated
through hole (PTH) via(s) through one or more levels of a pathway.
Electronic packages commonly include multiple interconnect levels.
In such a package, the invention may include layerings of patterned
conductive material on one interconnect level that may be
electrically insulated from patterned conductive material on
another interconnect level, such as by dielectric material
layers.
[0058] Connections or couplings between the conductive material at
the various interconnect levels may be made by forming openings,
referred to herein as vias or apertures, in the insulating portions
or layers, that in turn can provide an electrically conductive
structure such that the patterned or shaped conductive material
portions or pathways from different levels are brought into
electrical contact with each other. These structures can extend
through one or more of the interconnect levels. Use of conductive,
non-conductive or conductively-filled apertures and VIAs allows
propagating energy to transverse an exemplary embodiment as if
utilizing a by-pass or feed-through pathway configuration of an
embodiment. An embodiment may serve as a support, a system or a
subsystem platform that may contain both or either active and
passive components layered to provide the benefits described for
conditioning propagated energy between at least one source and at
least one load.
[0059] An aspect of the present invention may provide a conductive
architecture or structure suitable for inclusion in a packaging or
an integrated circuit package having other elements. Other elements
may be directly coupled to the device for simultaneous physical and
electrical shielding by allowing simultaneous energy interactions
to take place between grouped and energized complementary
conductors that are fed by other pathways. Typical capacitive
balances found between at least one shielding pathway may be found
when measuring opposite sides of the shared shield structure per
isolated circuit, and may be maintained at measured capacitive
levels within this isolated circuit portion, even with the use of
common non-specialized dielectrics or pathway conductive materials.
Thus, complementary capacitive balancing, or tolerance balancing
characteristics, of this type of electrical circuit due to element
positioning, size, separations and attachment positioning allow an
exemplary embodiment having an isolated circuit system manufactured
at 3% capacitive tolerance, internally, to pass to a conductively
coupled and energized isolated circuit system a maintained and
correlated 3% capacitive tolerance between electrically opposing
and paired complementary pathways of each respective isolated
circuit system, with respect to the dividing shield structures
placed into the isolated circuit system.
[0060] An exemplary embodiment may allow utilization of relatively
inexpensive dielectrics, conductive materials and various other
material elements in a wide variety of ways. Due to the nature of
the architecture, the physical and electrical dividing structure
created may allow the voltage dividing and balancing among the
grouped, adjacent elements, and may allow for the minimization of
the effect of material hysteresis and piezoelectric phenomenon to
such a degree that propagating energy normally disrupted or lost to
these effects may be essentially retained in the form of active
component switching response time, as well as instantaneous ability
to appear to the various energy-utilizing loads as an apparent open
energy flow simultaneously on both electrical sides of a pathway
connecting or coupling from an energy source to a respective load,
and from the load back to the source.
[0061] A structured layer may be shaped, buried within, enveloped
by, or inserted into various electrical systems and sub-systems to
perform line conditioning or decoupling, for example, and to aid in
or to allow for a modifying of an electrical transmission of energy
to a desired or predetermined electrical characteristic. Expensive,
specialized, dielectric materials that attempt to maintain specific
or narrow energy conditioning or voltage balancing may no longer be
needed for bypass, feed through, or energy decoupling operations
for a circuit.
[0062] A device according to an aspect of the present invention
may, as set forth hereinabove, be placed between each isolated
circuit and a paired plurality of pathways or differential
pathways. This exemplary device may operate effectively across a
broad frequency range, as compared to a single discrete capacitor
or inductor component, and may continue to perform effectively
within an isolated circuit system operating beyond, for example, a
GHz.
[0063] As set forth hereinabove, the exemplary device may perform
shielding functions in this broad frequency range. A physical
shielding of paired, electrically opposing and adjacent
complementary pathways may result from the size of the common
pathways in relationship to the size of the complementary pathways,
and from the energized, electrostatic suppression or minimization
of parasitics originating from the sandwiched complementary
conductors and preventing external parasitics. Further, the
positioning of the shielding, relative to shielding that is more
conductive, may be used to protect against inductive energy and
"H-Field" coupling. This technique is known as mutual inductive
cancellation.
[0064] Parasitic coupling is known as electric field coupling. The
shielding function discussed hereinabove provides primary shielding
of the various shielded pathways electrostatically against electric
field parasitics. Parasitic coupling involving the passage of
interfering propagating energy because of mutual or stray parasitic
energy originating from the complementary conductor pathways may be
thereby suppressed. A device according to an aspect of the present
invention may, for example, block capacitive coupling by enveloping
oppositely phased conductors in the universal shield architecture
with stacked conductive hierarchical progression, thereby providing
an electrostatic or Faraday shield effect with respect to the
pathway positioning as to the respective layering and position,
both vertically and horizontally, of the pathways. The shielding
pathway architecture may be used to suppress and prevent internal
and external parasitic coupling between potentially noisy
conductors and victim conductors, such as by an imposition of a
number of common pathway layers that are larger than the smaller
paired complementary pathways, but that are positioned between each
of the complementary pathway conductor pairs to suppress and to
contain the stray parasitics.
[0065] Further, as set forth hereinabove, positioning of the
shielding, relative to shielding that is more conductive, may be
used against inductive energy and "H-Field" coupling. This
cancellation is accomplished by physically shielding energy, while
simultaneously using a complementary and paired pathway positioned
to allow for the insetting of the contained and paired
complementary pathways within an area size correspondent to the
shield size. A device according to an aspect of the present
invention is adapted to use shields separately as internal shields
or groupings, thereby substantially isolating and sandwiching pairs
of electrically opposing complementary pathways, and thereby
providing a physically tight or minimized energy and circuit loop
propagation path between each shield and the active load. Close
proximity of shields and non-shields may allow energy along shields
even if a direct electrical isolation exists because of 801
material type or the spacing.
[0066] Flux cancellation of propagating energy along paired and
electrically opposing or differential pathways may result from
spacing of pathways apart by a very small distance for oppositely
phased electrically complementary operations, thereby resulting in
a simultaneous stray parasitic suppression and containment function
attributable to tandem shielding, and thereby enhancing energy
conditioning.
[0067] In attaining minimum areas for various current loops in an
isolated circuit system, additional shielding energy currents may
be distributed around component shielding architectures. A
plurality of shields as described hereinabove may be electrically
coupled as either an isolated circuit's reference node, or chassis
ground, and may be relied on as a commonly used reference pathway
for a circuit. Thus, the various groups of internally paired,
complementary pathways may include propagating energy originating
from one or more energy sources propagating along external pathways
coupled to the circuit by a conductive material. Energy may thus
enter the device, undergo conditioning, and continue to each
respective load.
[0068] The shielding structure may allow for a portion of a shield
to operate as the pathway of low impedance for dumping and
suppressing, as well as at least partially blocking return of
unwanted electromagnetic interference noise and energy into each of
the respective energized circuits. In an embodiment, internally
located shields may be conductively coupled to a conductive area,
thereby adaptively utilizing shielding structure for low impedance
dumping and suppressing and at least partially blocking return
blocking of unwanted electromagnetic interference noise and energy.
Additionally, another set of internally located shields may be
conductively coupled to a second conductive area, thereby utilizing
shields for low impedance dumping, suppressing and at least
partially blocking the return of unwanted electromagnetic
interference noise and energy. The conductive areas may be
electrically or conductively isolated from one another.
[0069] Simultaneous suppression of energy parasitics may be
attributed to the enveloping shielding pathway structure, in
combination with the cancellation of mutually opposing energy
fields, and may be further attributed to the electrically opposing
shielded pathway pathways and propagating energy along the various
circuit pathways interacting within the various isolated circuits
to undergo a conditioning effect taking place upon the propagating
energy. This conditioning may include minimizing effects of H-field
energy and E-field energy through simultaneous functions, such as
through isolated circuits that contain and maintain a defined
electrical area adjacent to dynamic simultaneous low and high
impedance pathways of shielding in which various paired pathways
have their respective potentials respectively switching as a result
of a given potential located on a shielding and used
instantaneously and oppositely by these pairings with respect to
the utilization by energy found along paired routings of the low
and high impedance shields.
[0070] The various distance relationships created by the positional
overlapping of energy routings within the isolated circuits combine
with the various dynamic energy movements to enhance and cancel the
various degrees of detrimental energy disruptions normally
occurring within active components or loads. The efficient energy
conditioning functions occurring within the passive layering
architecture allow for development of a dynamic "0" impedance
energy "black hole", or energy drain, along a third pathway coupled
common to both complementary pathways and adapted to allow energy
to be contained and dissipated upon the shielding, within the
various isolated circuits and attached or conductively coupled
circuits. Thus, electrically opposing energies may be separated by
dielectric material and/or by an interposition shield structure,
thereby allowing dynamic and close distance relationship within a
specific circuit architecture, and thereby taking advantage of
propagating energy and relative distances to allow for exploitation
of mutual enhancing cancellation phenomenon and an electrostatic
suppression phenomenon to exponentially allow layered conductive
and dielectric elements to become highly efficient in energy
handling ability.
[0071] According to an aspect of the present invention, a device
may utilize a single low impedance pathway or a common low
impedance pathway as a voltage reference, while utilizing a circuit
maintained and balanced within a relative electrical reference
point, thereby maintaining minimal parasitic contribution and
disruptive energy parasitics in the isolated circuit system. The
various attachment schemes described herein may allow a "0" voltage
reference, as discussed hereinabove, to develop with respect to
each pair or plurality of paired complementary conductors located
on opposite sides of the shared central shield, thereby allowing a
voltage to be maintained and balanced, even with multiple
Simultaneous Switching Operations states among transistor gates
located within an active integrated circuit, with minimal
disruptive energy parasitics in an isolated circuit.
[0072] Shields may be joined using principals of a cage-like
conductive shield structure to create one or more shieldings. The
conductive coupling of shields together with a larger external
conductive area may suppress radiated electromagnetic emissions and
as a larger area provides a greater conductive area in which
dissipation of voltages and surges may occur. One or more of a
plurality of conductive or dielectric materials having different
electrical characteristics may be maintained between shields. A
specific complementary pathway may include a plurality of commonly
conductive structures performing differentially phased conditioning
with respect to a "mate", or paired, plurality of oppositely phased
or charged structures forming half of the total sum of manufactured
complementary pathways, wherein one half of the complementary
pathways forms a first plurality of pathways, and wherein the
second half forms a second plurality of pathways. The sum of the
complementary pathways of the first and the second plurality of
pathways may be evenly separated electrically, with an equal number
of pathways used simultaneously, but with half the total sum of the
individual complementary pathways operating from, for example, a
range of 1 degree to approximately 180 degrees electrically out of
phase from the oppositely positioned groupings. Small amounts of
dielectric material, such as microns or less, may be used as the
conductive material separation between pathways, in addition to the
interposing shield, which dielectric may not directly physically or
conductively couple to any of the complementarily operating
shielded pathways.
[0073] An external ground area may couple or conductively connect
as an alternative common pathway. Additional numbers of paired
external pathways may be attached to lower the circuit impedance.
This low impedance phenomenon may occur using alternative or
auxiliary circuit return pathways.
[0074] A shield architecture may allow shields to be joined
together, thereby facilitating energy propagation along a newly
developed low impedance pathway, and thereby allowing unwanted
electromagnetic interference or noise to move to this created low
impedance pathway.
[0075] Referring now to FIGS. 1A through FIG. 5B, which generally
show various common principals of both common and individual
variants of an exemplary embodiment configured in a co-planar
variant (FIGS. 1A-4I) and a stacked variant (FIGS. 5A and 5B).
[0076] In FIG. 1A, there are shown relative locations of the
various pathway extensions disclosed according to an aspect of the
present invention. A portion of a relative balanced and
complementary-symmetrical arrangement utilizing a center shielding
pathway designated 8"XX"-"X"M is adapted in the arrangement as the
fulcrum of balanced conductive portions in a co-planar variant. A
pathway arrangement including at least a first and a second
plurality of pathways, wherein the first plurality has at least one
pair of pathways arranged electrically isolated from each other and
orientated in a first complementary relationship, is illustrated.
Additionally, at least a first half of the second plurality is
arranged electrically isolated from a second half of the second
plurality, wherein at least two pathways of the second plurality
are electrically isolated from the pathways of first plurality. The
pathway arrangement may also include a material having properties,
such as dielectric, ferromagnetic, or varistor for example, spacing
apart pathways of the pathway arrangement. The pathways of the
first half of the second plurality are electrically coupled to one
another, and the pathways of the second half of the second
plurality are electrically coupled to one another. A total number
of pathways of the first half of the second plurality may be an odd
number greater than one, and a total number of pathways of a second
half of the second plurality may also be an odd number greater than
one. According to an aspect of the present invention, the pathways
of the first half of the second plurality are positioned in a first
superposed alignment, while the pathways of the second half of the
second plurality are positioned in a second superposed alignment,
with the first and second superposed alignments in a mutual
superposed alignment herein defined as a co-planar arrangement.
[0077] In a non co-planar arrangement, the pathways of the first
half of the second plurality may be positioned in a first
superposed alignment, and the pathways of the second half of the
second plurality may be positioned in a second superposed
alignment, with the first and second superposed alignments in
arrangement one atop the other. In one arrangement, at least four
pathways are electrically isolated.
[0078] An illustrative embodiment of the present invention may
include at least three pluralities of pathways, including a first
plurality of pathways and a second plurality of pathways. The first
and second pluralities of pathways may include pathway members of
the first plurality having an equal and opposite pathway member
found in the second plurality of pathways. Members of the first and
second pluralities of pathways may be substantially the same size
and shape, and may be positioned complementary, and may also
operate in an electrically complementary manner. Thus, the pairings
of the first and second pluralities of pathways may result in
identical numbers of members of the first and second pluralities of
pathways. An exemplary embodiment may provide at least a first and
a second shield allowing for development of individual isolated low
circuit impedance pathways. Structurally, the shields may be
accomplished by a third plurality of pathways and a fourth
plurality of pathways. Each shielding plurality may include shields
of equal size and shape. Each of the third and fourth plurality of
pathways may be conductively coupled. Conductive coupling may be
accomplished by a variety of methods and materials known to those
possessing an ordinary skill in the pertinent arts. Thus, when the
third and a fourth plurality are grouped as two sets of shields
utilizing the first and second plurality receiving shielding, the
third and fourth pluralities may be coupled to a common pathway to
develop a low circuit impedance pathway for energy propagation for
conditioning of the circuit energy.
[0079] Pathways may additionally be arranged in a bypass
arrangement, such that when placed face to face, main-body pathways
80 may be aligned superposed, with the exception of any pathway
extensions such as 812NNE, 811NNE, 812SSW and 811SSW of the lower
sub-circuit portion, for example, shown as mirror images depicted
in FIG. 5A and FIG. 5B, for example.
[0080] Within the pluralities, individual pathway members may be of
substantially the same size and shape and may be conductively
coupled. However, individual pathway members of one plurality may
not be conductively coupled to members of a different plurality of
pathways. There may be situations wherein members of one plurality
may be connected to members of a different plurality, such as
wherein a first plurality of shields and a second plurality of
shields are externally coupled to the same conductor.
[0081] Common elements may include energy flow in accordance with
conceptual energy indicators 600, 601, 602, 603 depicting the
dynamic energy movements in co-planar shielded by-pass pathways,
such as those shown in FIGS. 1A-1C. An embodiment may provide for
at least multiple shields for development of multiple isolated low
circuit impedance pathways for multiple circuits.
[0082] Referring still to FIG. 1A, pathways may be shielded by the
relative, common pathways, and may include a main-body pathway 80
with at least one pathway extension 812"X". The shields shown
include a main-body shield pathway 81 with at least one pathway
extension designated 99"X"/79"X". The shields may sandwich and
envelope the main-body 799, including a conductive inner pathway
formed of conductive materials from the family of noble or base
metals traditionally used in co-fired electronic components or
conductive material, such as Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd, or
combination materials such as metal oxide and glass frit. A
capacitance and a resistance value may be achieved in one family of
pathways, as described hereinabove, such as by use of ruthenium
oxide as the resistive material and Ag/Pd as the conductive
material. Further, variations in pathway geometry may yield
different resistance and capacitance values. Variations may be
achieved by altering the materials from which the pathways are
made. For example, a conductive metal, such as silver, may be
selectively added to the metal oxide/glass frit material to lower
the resistance of the material.
[0083] A plurality of pathways, 865-1 and 865-2, are shown
positioned co-planar and spaced apart on a same portion of material
801. Each pathway of the co-planar pathways 865-1 and 865-2, may be
formed of conductive material 799, or a hybrid of conductive
material and another material, herein designated as 799"x". Each co
planar pathway 865-1 and 865-2 may also be formed as a bypass
pathway, wherein each pathway includes a main-body pathway 80
having a corresponding main-body edge and perimeter, 803A and 803B,
respectively and at least one pathway contiguous extension 812"X".
Each co-planar pathway 865-1 and 865-2, may include at least one
pathway contiguous extension 812SSW and 811SSW with a portion of
the main-body edge 803A and 803B extending therefrom. Extension
812"X" is a portion of the pathway material formed in conjunction
with a main-body pathway 80 from which it extends. Main-body
pathway 80, an 812"X" may be found as an extension of material 799
or 799"x" extending beyond an accepted average perimeter edge
803"X". Extensions 812"X" and 79"X" may be found respectively
positioned as a contiguous portion of the pathway from which it is
formed. Each main-body pathway may have edge 803A, 803B positioned
relative and spaced apart a distance 814F from the embodiment edge
817 Embodiment edge 817 may include a material 801. Co-planar
main-body pathway's edge 803"x" may be positioned and spaced apart
a distance 814J. Pathway extensions 812SSW and 811SSW may
conductively couple a respective pathway main-body 80 to an outer
pathway 890SSW and 891SSW, which may be positioned at edge 817. The
co-planar arranged, main-body pathway 80 may be positioned
"sandwiched "between the area of registered coverage of two
layering of co-planar, main-body pathway 81s.
[0084] Combining mutually opposing fields causes a cancellation or
minimization effect. The closer the complementary, symmetrically
oriented shields, the better the resulting mutually opposing
cancellation effect on opposing energy propagation. The more
superposed the orientation of the complementary, symmetrically
oriented shields is, the better the resulting suppression of
parasitics and cancellation effect.
[0085] Referring still to FIG. 1A, the edges of the plurality of
co-planar shields may be represented by dotted lines 805A and 805B.
Main-body pathways 81 of each of the plurality of shields are
larger than a sandwiching main-body pathway 80 of any corresponding
sandwiched pathway. This may create an inset area 806 relative to
the positions of the shields and remaining pathways. The size of
main-bodies 80 and 81 may be substantially similar, and thus the
insetting positioning relationships may be minimal in certain
embodiments. Increased parasitic suppression may be obtained by
insetting pathways, including a main-body 80, to be shielded by
larger pathway main-body 81s. For example, an inset of a main-body
80 of pathways 865-1 inset may be separated a distance of 1 to 20+
times the spacing provided by the thickness of the material 801
separating pathway 865-1 and adjacent center co-planar pathway
800-IM-1, as illustrated in FIG. 1B.
[0086] Plurality of co-planar shield edges 805A and 805B may be
positioned and spaced apart a distance 814K, and may be a distance
814 relative to edges 805A and 805B and the edge 817. Other
distances 814J relative from either edges 803A and 803B may be
provided. Further, distance 814F may be present between one 803"X"
and an edge 817. Each coplanar shield may include a plurality of
contiguous pathway extension portions, such as, for example,
portions 79NNE, 79SSE, 99NNE and 99SSE, extending from the
plurality of coplanar shield edges 805A and 805B. Plurality of
co-planar shields may include a plurality of outer pathway material
901NNE, 901SSE, 902NNE and 902SSE positioned at the edge 817.
Conceptual energy indicators 602 represent the various dynamic
energy movements within the co-planar pathways 865-1 and 865-2.
Unwanted energy may be transferred to the coplanar shields in
accordance with the provision by the shields providing for a low
impedance pathway, which shields may additionally be electrically
coupled to another pathway or conductive area.
[0087] Referring now to FIGS. 1B and 1C, layer sequences are
illustrated for a first plurality of co-planar pathways 865-1,
865-2, a second plurality of co-planar pathways 855-1, 855-2, and a
third plurality of co-planer pathways 825-1-IM, 825-2-IM, 815-1,
815-2, 800-1-IM, 800-2-IM, 810-1, 810-2, and 820-1-IM, 820-2-IM.
The first, second, and third pluralities may be stacked to form an
embodiment 3199, 3200, 3201. The third plurality of co-planar
pathways may provide shielding. Main-bodies 81 of the plurality of
co-planer shields 825-1-IM, 825-2-IM; 815-1, 815-2; 800-1-IM,
800-2-IM; 810-1, 810-2; and 820-1-IM, 820-2-IM may be substantially
similar in size and shape, and may be spaced apart in co-planar
locations on different layers of material 801. The first plurality
of co-planar pathways 865-1 and 865-2 may have at least the
corresponding, opposing, and complementary second plurality of
co-planar pathways 855-1 and 855-2. These first and second
pluralities of co-planar pathways, when oriented face to face, may
have main-body pathways 80s co-registered and aligned except for
the various contiguous pathway extensions 812"X", 811 "X". As shown
in FIGS. 1B and 1C, a pair of outer co-planar pathways 820-1-IM,
825-1-IM may serve as pathway shields, thereby improving the
shielding effectiveness of the other conductively coupled
pluralities of pathways with a main-body 81s.
[0088] As illustrated in the varied embodiments 3199, 3200, 3201,
the location of extensions 79NNE, 79SSE, of shields 825-1-1M,
815-1, 800-1-IM, 810-1, and 820-1-IM and extensions 99NNE, 99SSE of
the shields 825-2-IM, 815-2, 800-2-IM, 810-2, and 820-2-IM, may be
varied. In FIG. 1B, for example, extensions 79NNE and 99NNE may be
arranged spaced apart, diagonally from extensions 79SSE and 99SSE
and on opposite sides of shield main-body 81. In FIG. 1C, for
example, extensions 79NNE and 99NNE may be arranged spaced apart in
line with extensions 79SSE and 99SSE on opposite sides of shield
main-body 81. In FIG. 1B, extensions 812NNE and 811NNE may be
arranged spaced apart, extending toward the same edge 812 of layer
of material 801, and extensions 812SSW and 811SSW may be arranged
spaced apart, each extending toward the opposite edge 812 of layer
of material 801. In FIG. 1C, pathways 865-1 and 865-2 may be mirror
images, as discussed hereinabove. Comparably to FIG. 1B, extensions
812NNE and 811NNE may be arranged spaced apart, extending toward
opposite edges 817 of layer of material 801. Extensions 812SSW and
811SSW may be arranged spaced apart, extending toward the opposite
edge of layer of material 801, such that extensions 812NNE and
811SSW extend toward opposite edges 812"X" of the respective layer
of material 801.
[0089] Referring now to FIGS. 2A and 2B, FIG. 2A illustrates a
schematic plan view of a an embodiment of FIG. 2B according to an
aspect of the present invention. FIG. 2B depicts a pathway
arrangement including a layout of a first, a second, a third, a
fourth, a fifth, a sixth, a seventh, a eighth, a ninth and a tenth
pathway, wherein at least the third and the fourth pathway, for
example, may be co-planar and arranged spaced apart from each
other. FIG. 2B illustrates the first and the second pathway
arranged below the third and the fourth pathway, and the fifth and
the sixth pathway arranged above the third and the fourth pathway,
and the seventh and the eighth pathway arranged above the fifth and
the sixth pathway, and the ninth and the tenth pathway, arranged
above the seventh and the eighth pathway. These pathways have
various respective internal contiguous pathway extensions 812"X",
811"X", 79"X" and 99"X", and may be discrete components having the
same minimal numbers of layering. Internal contiguous pathway
extensions 812"X", 811"X", 79"X" and 99"X", and conductively
coupled external pathways 890"X", 891"X" 802"X" and 902"X", may be
coupled to the inner pathway of the plurality of co-planar pathways
of the main-body pathway 80 and 81.
[0090] Referring now to FIGS. 3A and 3B, in FIG. 3A there is shown
a schematic plan view of an embodiment of FIG. 3B, wherein outer
pathways may be selectively conductively coupled in at least two
isolated circuit portions. FIG. 3B depicts an pathway arrangement
including a minimal layout of a first, a second, a third, a fourth,
a fifth, a sixth, a seventh, a eighth, a ninth and a tenth pathway,
wherein at least the third and the fourth pathway, for example, are
co-planar and arranged spaced apart from each other. The device
shown in FIG. 3B may have the first and the second pathway arranged
below the third and the fourth pathway, and the fifth and the sixth
pathway arranged above the third and the fourth pathway, and the
seventh and the eighth pathway arranged above the fifth and the
sixth pathway, and the ninth and the tenth pathway arranged above
the seventh and the eighth pathway. These pathways have various
respective internal contiguous pathway extensions 812"X", 811"X",
79"X" and 99"X", and may be discrete components having the same
minimal number of layering.
[0091] Referring now to FIG. 3C, a plan view of a shield according
to an aspect of the present invention is illustrated. The
embodiment depicted in FIG. 3C includes at least one additional
pathway, as compared to the device of FIG. 3B This additional
pathway 1100-IM"X" may be one of at least a plurality of shields in
the stack of pathways, which shields may span across the two
circuit portions. Pathway 1100-IM"X" may be one of at least two
outer sandwiching shields in the stack of pathways. Shields may
span across the two circuits by adding a centrally arranged
1100-IM"X" pathway electrically coupled to the outer 1100-IM"X"
shields. Pathways 1100-IM"X" may have at least one extension, and
are illustrated with two extensions 1099NNE and 1099SSE, and may
allow for sandwiching shields for all of the pathways within the
present invention. At least three shields may be coupled together
and may include a centering shield dividing an energy load or
energy source of an isolated circuit or dividing two isolated
circuits.
[0092] A shield 00GS may be electrically isolated from other
shields and may be arranged to effect an energy propagation of an
isolated circuit. An isolated circuit may be sandwiched by a
shield. A shield may be electrically coupled to a conductive area
that is isolated from any other conductive areas thereby effecting
an energy propagation.
[0093] FIGS. 4A-4I depict assembled components of various
embodiments according to aspects of the present invention. The
arrangements of FIG. 4A to FIG. 4I may include minimal layouts of a
first, a second, a third, a fourth, a fifth, a sixth, a seventh, a
eighth, a ninth and a tenth pathway, wherein at least the third and
the fourth pathway, for example, are co-planar and arranged spaced
apart from each other. The first and the second pathway may be
arranged below the third and the fourth pathway, and the fifth and
the sixth pathway may be arranged above the third and the fourth
pathway, and the seventh and the eighth pathway may be arranged
above the fifth and the sixth pathway, and the ninth and the tenth
pathway may be arranged above the seventh and the eighth pathway.
These pathways have various respective internal contiguous pathway
extensions 812"X", 811"X", 79"X" and 99"X", and may be an assembled
final discrete component, for example.
[0094] Referring to FIG. 5A, there is shown a stacking of multiple,
non-shared circuits including groups of pathways according to an
aspect of the present invention. Included in FIG. 5A is a marker
1000 showing a continuation of the stacking arrangement to the next
column of FIG. 5A. Conceptual energy indicators 600, 601, 602, 603
indicate energy flow. Material 799 may be deposited on material 801
for component 6900 shields designated 815-1, 800-1, 810-1-IM,
815-2, 800-2-IM, and 810-2. Shields 810-A and 810-B are separated
shields of at least part of an isolated circuit system. Shields
815-A and -B are separated shields of at least part of an isolated
circuit system. Shields 820-A and 820-B are separated shields at
least part of an isolated circuit system. Shields 825-A and 825-B
are separated shields at least part of an isolated circuit system.
Conductors 855-1 and 855-2 are separated and shielded pathways in
bypass configuration. Conductors 865-1 and 865-2 are separated and
shielded pathways in bypass configuration. In FIG. 5A, a pathway
arrangement is depicted including at least six orientations of
pathways of two types of pathways, wherein each orientation of the
pathways of the at least six orientations of pathways provides
conductive isolation from the remaining orientations of
pathways.
[0095] Referring to FIG. 5B, there is shown a stacked shield
structure according to an aspect of the present invention. FIG. 5B
depicts an embodiment similar to that of FIG. 5A, wherein two sets
of 855"X" and 865"X" pathways are omitted for purposes of clarity,
and wherein the shields of FIG. 5A are oriented in flip-flop for
each relative set of 855"X" and 865"X" pathways. The 79"X" pathway
extensions may be rotated 90 degrees relative to the various
pathway extensions 811"x" and 812"X". A dynamic result of this
configuration, as illustrated by the conceptual energy indicators,
may be enhanced by nulling the extensions of the two sets of 855"X"
and 865"X" pathways of the two isolated circuits, and by relatively
positioning the shield of each isolated circuit pairing 855A and
865A approximately 90 degrees null to the various pathway
extensions of 855B and 865B.
[0096] Referring to FIG. 5B, there is shown a stacked shield
structure according to an aspect of the present invention. FIG. 5B
depicts an embodiment similar to that of FIG. 5A, wherein two sets
of 855"X" and 865"X" pathways are omitted for purposes of clarity,
and wherein the shields of FIG. 5A are oriented in flip-flop for
each relative set of 855"X" and 865"X" pathways. The 79"X" pathway
extensions may be rotated 90 degrees relative to the various
pathway extensions 811"x" and 812"X". A dynamic result of this
configuration, as illustrated by the conceptual energy indicators,
may be enhanced by nulling the extensions of the two sets of 855"X"
and 865"X" pathways of the two isolated circuits, and by relatively
positioning the shield of each isolated circuit pairing 865B and
865A approximately 90 degrees null to the various pathway
extensions of 865B and 865A.
[0097] As discussed hereinabove, in an embodiment of the present
invention, multiple complementary or paired shielded pathways may
include the first and second pluralities of pathways. Energy may
utilize the various paired, feed-through or bypass pathway layers
in a generally parallel and even manner, for example. Pathway
elements may include non-insulated and conductive apertures, and
conductive through-VIAs, to provide propagating energy and maintain
a generally non-parallel or perpendicular relationship, and
additionally maintain a separate electrical relationship with an
adjoining circuit. These pathways may maintain balance internally,
and may facilitate an electrical opposition along opposing
complementary pairings. This relationship among complementary pairs
of pathways may occur while the pathways and the energy are
undergoing an opposite operational usage within the shielding
structure attached externally.
[0098] Referring now to FIG. 5C, there is shown a relative plan
view of a stacked multiple, non-shared circuit network having VIAs
and including groups of pathways according to an aspect of the
present invention. The device according to an aspect of the present
invention depicted in FIG. 5C includes a hole-through energy
conditioner. Hole-through energy conditioners may be formed such
that many of the energy propagation principals disclosed herein are
retained, including the use of multiple sets of shields for energy
conditioning possessing. FIG. 5C, further depicts null pathway sets
with pathway arrangement 6969. Pathway arrangement 6969 is similar
to FIG. 5B, with the absence of pathway extensions 79"X", 811"x"
and 812"X", and with the substitution of 8879"X", 8811"X" and
8812"X" VIAs functioning from a different direction relative to the
main-body 80 and 81.
[0099] Referring still to FIG. 5C, during the manufacturing
process, conductive holes 912, VIAS or conductive apertures may be
used to interconnect 8806 an integrated circuit, and may be formed
through one or more pathway layers using mechanical drilling, laser
drilling, etching, punching, or other hole formation techniques.
Each specific interconnection 8806 may enable various pathways to
be electrically connected or insulated. Each specific
interconnection 8806 may extend through all layers of pathway
arrangement 6969, or may be bounded above or below by one or more
layers. Pathway arrangement 6969 may include an organic substrate,
such as an epoxy material, or patterned conductive material. If an
organic substrate is used, for example, standard printed circuit
board materials such as FR-4 epoxy-glass, polymide-glass,
benzocyclobutene, Teflon, other epoxy resins, or the like could be
used in various embodiments. In alternate embodiments, a pathway
arrangement could include an inorganic substance, such as ceramic,
for example. In various embodiments, the thickness of the levels
may be approximately 10-1000 microns. Interconnections 8806 between
the various conductive layers may also be formed by selectively
removing dielectric and conductive materials, thereby exposing the
conductive material of the lower conductive layers 904, and by
filling the holes so formed by the removal with a conductive paste
799A or electrolytic plating 799B, for example.
[0100] Interconnections 8806 may couple exposed conductive layers
to a relative side of the pathway arrangement 6969.
Interconnections 8806 may take the form of pads or lands to which
an integrated circuit may be attached, for example.
Interconnections 8806 may be formed using known techniques, such as
by filling the selectively removed portions of dielectric with
conductive paste, electrolytic plating, photolithography, or screen
printing, for example. The resulting pathway arrangement 6969
includes one or more layers of patterned conductive material 904,
separated by non-conducting layers, and interconnected by
interconnects 8806. Different techniques may be used to
interconnect and isolate the various layers of patterned conductive
material 799. For example, rather than forming and selectively
removing portions of the various conducting 799 and non-conducting
layers 801, openings between the various layers may be included by
selectively adding the desired portions of the conducting 799 and
non-conducting layers 801. Removal techniques, such as chemical
mechanical planarization, may be used to physically abrade away
multiple layers of different types of conducting and non-conducting
materials, resulting in the desired openings for various
interconnects.
[0101] Pathway arrangement 6969 may be configured using a
multi-aperture, multilayer energy conditioning pathway set, with a
substrate format adapted to condition propagating energy. Pathway
arrangement 6969 may condition propagating energy by utilizing a
combined energy conditioning methodology of conductively filled
apertures, known in the art as VIAs 8879"X", 8811"X" and 8812"X",
in combination with a multi-layer common conductive Faraday
cage-like shielding technology with immured propagational pathways.
Interconnecting pathway arrangement and an IC may be achieved with
wire bonding interconnection, flip-chip ball-grid array
interconnections, microBall-grid interconnections, combinations
thereof, or any other standard industry accepted methodologies. For
example. a "flip chip" type of integrated circuit, meaning that the
input/output terminations as well as any other pathways on the chip
may occur at any point on its surface. After the IC chip is
prepared for attachment to pathway arrangement 6969, the chip may
be flipped over and attached, by solder bumps or balls to matching
pads on the top surface of pathway arrangement 6969. Alternatively,
an integrated circuit may be wire bonded by connecting input/output
terminations to pathway arrangement 6969 using bond wires to pads
on the top surface of pathway arrangement 6969.
[0102] The circuits within pathway arrangement 6969 may act as a
source to load pathway arrangement requiring capacitance, noise
suppression, and/or voltage dampening. This capacitance may be
provided by formation of the capacitance developed and embedded
within pathway arrangement 6969. This capacitance may be coupled to
the integrated circuit loads using a paired pathway and the shield,
as described above. Additional capacitance may be provided to a
circuit electrically coupled to an integrated circuit to provide
voltage dampening and noise suppression. Close proximity of
off-chip energy sources may provide a capacitance each along the
low inductance path to the load. Common shielding pathways may be
utilized as the "0" voltage circuit reference node for both
off-chip energy sources the common conductive interposer energy
pathway configurations.
[0103] Pathway arrangement 6969 may be connected to an integrated
circuit by commonly accepted industry connection methods and
couplings 799A and 799B, including Bumpless Build-Up Layer (BBUL)
packaging. This technology enables higher performance, thinner and
lighter packages, and lowers power consumption. In a BBUL package,
the silicon die or IC is embedded in a package with a pathway
arrangement operable as a first level interconnect. Thus, the BBUL
package as a whole is not just attached to one surface of the IC.
For example, electrical connections between the die and one or more
of the various shields and the package may be made with copper
lines, not necessarily C4 solder bumps. These features combine to
make the package thinner and lighter than other IC packages, while
delivering higher performance and reducing power consumption. BBUL
may enhance the ability of a manufacturer to couple multiple
silicon components to pathway arrangement 6969. Shielded pathways
8811, 8812, and 8879 may be electrically connected between
respective energy sources and respective load of the IC by common
industry methodologies, thereby allowing for conditioning of
propagating energy. Shields 8879 may conductively coupled to a
shield including 1055-2. A shield and its other conductive portions
including 8811 and 8812 may be electrically coupled to a respective
complementary pathway which poses no polarity charge of
significance before hook-up, thereby preventing each layer 8811 and
8812 from changing energy propagation direction functions, such
preventing layer 8811 and 8812 from changing from input and output
to output and input, respectively, as is understood by those
possessing an ordinary skill in the pertinent arts.
[0104] For stacked variants depicted in FIGS. 5A, 5B and 5C, adding
three pathways 1100-IM-"X", including one between 810-1 and 815-2,
designated as 1100-IM-"C", may bisect a balanced symmetry of the
total number of pathways located into equal numbers on opposite
sides of 1100-IM-"C". The addition of 1100-IM-1 and 1100-IM-2,
electrically coupled to 1100-IM-C, creates a common or a shield
structure (not all shown). Shields of a shield structure may be of
substantially the same size or not. Shields may or may not be
physically isolated from any other shields for any one or more
embodiments of the present invention. Thus, shields may or may not
be electrically or conductively isolated from any other shields for
any one or more embodiments of the present invention.
[0105] An odd number of shields may be coupled together thereby
allowing formation of a common reference or node utilizing all
other shields. The number of shields 1100-IM-"X" is not confined to
using extensions 1099NNE and 1099SSE such as shield 00GS, as any
number of extensions in almost any direction may be used to
facilitate a coupling. A relative balanced and
complementary-symmetrical arrangement may be formed with respect to
a center shield 8"XX" or shield 800/800-IM for a as the arrangement
fulcrum of balanced conductive portions. At least a partial flux
field cancellation of energy propagating along or between paired
and electrically opposing complementary pathways occurs in this
balanced but shifted embodiment. Further, simultaneous stray energy
parasitics, complementary charged suppression, physical and
electrical shielding containment and a faraday effect may also
occur. This result is achieved because the magnetic flux energies
travel at least partially along the shield wherein the RF return
path is parallel and adjacent to a corresponding pathway. Thus, the
magnetic flux energy may be measured or observed relative to a
return
[0106] Shifted pathways may be in relative balance and
complementarily and symmetrically positioned with respect to center
shields, such as shields 800/800-"X"-IM, and may include a
relatively shifted, balanced, complementary, and symmetrical
arrangement of predetermined shields and pathways complementarily
sandwiched around a centrally positioned shield, such as
800/800-IM, for example.
[0107] The exemplary embodiments of FIGS. 1A, 1B, 1C, through FIG.
41, for example may include these `shifted` embodiments. These
shifted embodiments may include a multiplicity of layers having a
shielding, a pathway, a shielding, an pathway, and a shielding.
Each of these multiplicity of layers may be centered and
complementary about a center shield 800/800-"X"-IM, such as for
co-planar variants, and the entire multiplicity of layers may be
centered about a main center shield. Complementarity and balance
may be maintained about the center shield, and the main center
shield, although individual shields may be shifted to create
discrete imbalances as between a given matched pathway pair, for
example. Shifting may expose a portion of at least one pathway
outside the perimeter of the superposed shielding, thereby allowing
for parasitics and thereby varying, for example, impedance
characteristics.
[0108] For example, a given pathway may be shifted 5 points to the
left. This shifting may be accounted for in the matched pairs about
a center shield, and, consequently, either an adjacent matched pair
pathway of opposing polarity may be shifted 5 points, or 5 adjacent
pathways of opposite polarity may each shift 1 point, thereby
maintaining complementarity and balance. Further, pathways may
remain within the perimeter of the superposed shielding, and
nonetheless be shifted thereunder. Such a shifting under the
shielding may, nonetheless, make desirable a balancing. However,
certain exemplary embodiments not shown may include situations
wherein pathways are pulled toward the center of a shield, and
remain under the shield evidencing differing electrical
characteristics, such as inductive behavior, in a balanced or
unbalanced state.
[0109] Referring now to FIG. 6, there is shown a stacked multiple
circuit including embodiment 6900, conductive energy pathways,
isolated energy sources, isolated energy-utilizing loads, and
isolated common conductive pathways. The conductive energy pathways
may be conductively coupled to embodiment 6900 by a conductive
coupling material, such as, for example, by a solder or industry
equivalent. Vias 315, conductive pathways continuing below the
surface of the substrate, may couple to the conductive pathways,
and may include conductive material that serves as a contiguous
conductive pathway for propagating energies. The isolated common
conductive pathways may not be directly coupled to the isolated
energy sources or the isolated energy-utilizing loads. As discussed
hereinabove, embodiment 6900 may include four pluralities of
pathways including electrodes and shields, with each plurality
electrically isolated. The shields may be conductively coupled. The
conductively coupled shields may be externally coupled to an
isolated common conductive pathway, which is not directly
conductively coupled to the electrodes, using a conductive coupling
material. As shown in FIG. 6 an electrode, 815-1, 800-1-IM and
810-1, may be conductively coupled to 802GA, 802 GB. A shield,
815-2, 800-2-IM, and 810-2, may be conductively coupled to 902GA
and 902 GB. These couplings may not be conductively coupled to the
first plurality of electrodes or the second plurality of
electrodes. In this configuration, both isolated circuits may be
utilizing the isolated and separate voltage references and an
isolated common impedance path such as REF 1 and REF 2 in FIG.
6.
[0110] Referring now to FIG. 7, there is shown a stacked co-planar
multiple circuit including embodiment 3210, conductive energy
pathways, isolated energy sources, isolated energy-utilizing loads,
and isolated common conductive pathways. The conductive energy
pathways may be conductively coupled to embodiment 3210 by a
conductive coupling material. Vias 315, conductive pathways
continuing below the surface of the substrate, may couple to the
conductive pathways and may include conductive material that serves
as a contiguous conductive pathway for propagating energies. The
isolated common conductive pathways may not be directly coupled to
the isolated energy sources or the isolated energy-utilizing loads.
As discussed hereinabove, embodiment 3210 may include four
pluralities of pathways including electrodes and shields, with each
plurality electrically isolated. The conductively coupled shields
may be externally coupled to an isolated common energy pathway,
which is not directly conductively coupled to the first or the
second plurality of electrodes in this co-planar arrangement. A
third plurality of electrodes, 815-1, 800-1-IM and 810-1 may be
conductively coupled to 802GA, 802GB, 815-2 and 800-2-IM, and also,
may be conductively coupled to 902GA, 902GB, and may not be
conductively coupled to the first plurality or the second
plurality. In this configuration, both isolated circuits may be
utilizing a separate and a respective isolated and separate voltage
reference and a separate and a respective isolated impedance path,
a separate and a respective isolated common impedance path and at
least one separate and respective low inductance pathway such as
REF 1 and REF 2 in FIG. 7.
[0111] Referring now to FIG. 4A thru to FIG. 7, the termination
electrodes 890A, 890B, and 891A, 891B, 802GA, 802GB, and 902GA,
902GB, may be monolithic or multi-layered. Termination electrodes
802GA, 802GB, 902GA, 902GB, may be located at other respective
portions of a sintered body. Each main body electrode layers 81 or
80, and the associate electrode extensions 99/79G"X" or 812"X", may
define an electrode which extends to, and conductively couples to,
the associated termination electrodes 802GA, 802GB, 902GA, 902GB
and 890A, 890B, and 891A, 891B.
[0112] The present invention may be utilized for many energy
conditioning functions that utilize commonly coupled shielding
structure element for emulating a center tap of resistor/voltage
divider network. This resistor/voltage divider network may be
normally constructed using a ratio of various integrated circuit
resistors. However, various integrated circuit resistors may be
replaced by a device according to an aspect of the present
invention, the device utilizing, for example, specific
conductive/resistive materials 799A or naturally occurring
resistance properties of pathway material 799, or utilizing a
varied physical layout. A voltage dividing function may be present
as portions of a common and shared pathway shield structure are
utilized to define a common voltage reference located at both
respective sides of the common pathway shield structure.
[0113] In embodiments, whether initially stacked vertically during
a manufacturing process, or in combination with a co-planar
pairings as described hereinabove, the number of complementary
pathways pairings may be multiplied in a predetermined manner to
create a number of pathway element combinations of a generally
physically or electrically parallel nature.
[0114] Further, although not shown, a device of the present
invention may be fabricated in silicon and directly incorporated
into integrated circuit microprocessor circuitry or microprocessor
chip packaging. Any suitable method for depositing electrically
conductive materials may be used, such as plating, sputtering,
vapor, electrical, screening, stenciling, vacuum, and chemical
including chemical vapor deposition (CVD).
[0115] While certain embodiments have been herein described in
position as "upper" or "above", or "lower" or "below", or any other
positional or directional description, it will be understood that
these descriptions are merely relative and are not intended to be
limiting.
[0116] The present invention may be implemented in a number of
different embodiments, including a energy conditioning embodiment
as an energy conditioner for an electronic assembly, an energy
conditioning substrate, an integrated circuit package, an
electronic assembly or an electronic system in the form of a energy
conditioning system, and may be fabricated using various methods.
Other embodiments will be readily apparent to those of ordinary
skill in the art.
* * * * *