U.S. patent application number 10/921054 was filed with the patent office on 2005-01-27 for apparatus and method for fabricating semiconductor devices.
Invention is credited to Kim, Chang Gyu, Kim, Wan Shick.
Application Number | 20050016686 10/921054 |
Document ID | / |
Family ID | 19716432 |
Filed Date | 2005-01-27 |
United States Patent
Application |
20050016686 |
Kind Code |
A1 |
Kim, Chang Gyu ; et
al. |
January 27, 2005 |
Apparatus and method for fabricating semiconductor devices
Abstract
Disclosed is apparatus and method for fabricating semiconductor
devices, in particular comprising a wafer chuck for holding a
semiconductor wafer on which a predetermined thin layer is
deposited; a processing chamber for injecting etching gas toward
the wafer to form a predetermined pattern; and a clamp or a shadow
ring provided on an edge of the wafer being held by the wafer chuck
and preventing the edge from being etched, and thereby forming a
protective step around the edge. Therefore, during a subsequent CMP
process, the pattern adjacent to the edge of the wafer can be
prevented from being over-polished, and reliability as well as
productivity of the semiconductor devices can be improved.
Inventors: |
Kim, Chang Gyu;
(Kyoungki-do, KR) ; Kim, Wan Shick; (Kyoungki-do,
KR) |
Correspondence
Address: |
SEYFARTH SHAW
55 EAST MONROE STREET
SUITE 4200
CHICAGO
IL
60603-5803
US
|
Family ID: |
19716432 |
Appl. No.: |
10/921054 |
Filed: |
August 18, 2004 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10921054 |
Aug 18, 2004 |
|
|
|
10306238 |
Nov 27, 2002 |
|
|
|
6797625 |
|
|
|
|
Current U.S.
Class: |
156/345.51 ;
257/E21.244; 257/E21.304; 438/694 |
Current CPC
Class: |
H01L 21/3212 20130101;
H01L 21/31053 20130101 |
Class at
Publication: |
156/345.51 ;
438/694 |
International
Class: |
H01L 021/44; C23F
001/00 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 29, 2001 |
KR |
2001-74875 |
Claims
1. An apparatus for fabricating semiconductor devices, comprising:
a wafer chuck for holding a semiconductor wafer on which various
thin layers has been deposited; a processing chamber for injecting
etching gas toward the wafer to form a predetermined pattern; and a
clamp, attached to an edge of the wafer being held by the wafer
chuck, for preventing the edge from being etched.
2. An apparatus as claimed in claim 1, wherein the clamp forms a
protective step on the edge by constraining the edge from being
etched.
3. An apparatus for fabricating semiconductor devices comprising: a
wafer chuck for holding a semiconductor wafer on which various thin
layers has been deposited; a processing chamber for injecting
etching gas toward the wafer to form a predetermined pattern; and a
shadow ring, provided in the chamber upwardly spaced apart from the
wafer being held by the wafer chuck, for preventing the edge from
being etched.
4. An apparatus as claimed in claim 3, wherein the shadow ring
forms a protective step on the edge by constraining the edge from
being etched.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the invention
[0002] The present invention relates to an apparatus and method for
fabricating semiconductor devices, and more particularly for
forming a protective step which can prevent an edge of a
semiconductor wafer from being over-polished during a
chemical-mechanical polishing (CMP) process.
[0003] 2. Description of the Prior Art
[0004] In general, a CMP process has been applied as a
planarization process for insulation layers as well as a damascene
process for metallic layers.
[0005] The CMP process is employed in polishing a semiconductor
wafer surface by using the friction between slurry and a pad, in
which various consumables, such as slurry, a pad, a backing film, a
diamond conditioner, etc., are used. The polishing property of this
process is dependant upon pressure distribution between the pad and
the wafer while the wafer is polished in close contact with the
pad.
[0006] When the amount of polishing on one surface of a blanket
wafer is uniformly maintained, pressure on the other surface of the
wafer may be controlled. When the amount of polishing on an edge of
the wafer is controlled, pressure on a retainer ring on the
circumference of the CMP equipment may be controlled. However,
there is a problem in that it is difficult to control the level of
polishing resulting from a chip layout, a pattern density, a
pattern height and so forth.
[0007] Before such a CMP process is performed, the wafer undergoes
deposition of various thin layers, and then a predetermined pattern
is formed on the wafer by photolithography and etching
processes.
[0008] In the photolithography process, to inhibit photoresist
contamination as well as particle generation, the photoresist
applied on the wafer, in particular on the edge of the wafer, is
subjected to rinsing.
[0009] The photolithography and etching processes will be
specifically described below with reference to attached
drawings.
[0010] Referring to FIG. 1A, to form a pattern prior to the CMP
process, various thin layers are deposited on the wafer 10, and
then the resulting wafer is subjected to photolithography as well
as etching processes so as to form a predetermined pattern
thereon.
[0011] Specifically, in the photolithography process, a
predetermined insulation layer is deposited on the wafer 10, an
anti-reflection layer and a photoresist layer are in turn applied
on the insulation layer, an edge 12 of the wafer is rinsed, only
photoresist on the edge 12 is removed, the remnant photoresist is
photosensed in the presence of a mask, and a predetermined pattern
11 is formed by a reactive ion etching (RIE) process.
[0012] In general, in the RIE process, the wafer is wholly exposed
to reactive gas, thereby a pattern area free from photoresist is
etched together with the edge 12 of the wafer from which
photoresist was rinsed and removed. Therefore, a height difference
is formed in proportion to the etched amount.
[0013] In the CMP process after the thin layers are deposited on
the pattern 11 which is generated by the RIE process, the edge 12
from which a part of photoresist was rinsed and removed is
over-polished, which incurs damage of the wafer 10 as shown in FIG.
1B.
[0014] To avoid this problem, a dummy chip has been used, but it
acts as a factor which decreases the yield of semiconductor
devices. In addition, when the photoresist is not rinsed, the edge
of the wafer may be free from damage. However, the wafer may not
only be contaminated by the non-rinsed photoresist during
transporting of the wafer. The edge thereof may be formed with
particles.
SUMMARY OF THE INVENTION
[0015] Accordingly, the present invention has been made to solve
the above-mentioned problems occurring in the prior art, and an
object of the present invention is to provide an apparatus for
fabricating semiconductor devices, in which during an etching
process an edge of a semiconductor wafer is constrained from being
etched by using a clamp.
[0016] Another object of the present invention is to provide an
apparatus for fabricating semiconductor devices, in which during an
etching process an edge of a semiconductor wafer is constrained
from being etched by using a shadow ring.
[0017] Another additional object of the present invention is to
provide a method for fabricating semiconductor devices, in which
during a CMP process after formation of a protective step on an
edge of a semiconductor wafer, over-polishing, which results in a
height difference between the edge and a pattern of the wafer, is
prevented.
[0018] In order to accomplish these objects, according to one
embodiment of the present invention, there is provided an apparatus
for fabricating semiconductor devices, comprising: a wafer chuck
for holding a semiconductor wafer on which various thin layers has
been deposited; a processing chamber for injecting etching gas
toward the wafer to form a predetermined pattern; and a clamp,
attached to an edge of the wafer being held by the wafer chuck, for
preventing the edge from being etched.
[0019] According to another embodiment of the present invention,
there is provided an apparatus for fabricating semiconductor
devices, comprising: a wafer chuck for holding a semiconductor
wafer on which various thin layers has been deposited; a processing
chamber for injecting etching gas toward the wafer to form a
predetermined pattern; and a shadow ring, provided in the chamber
upwardly spaced apart from the wafer being held by the wafer chuck,
for preventing the edge from being etched.
[0020] According to another additional embodiment of the present
invention, there is provided a method for fabricating semiconductor
devices using a semiconductor wafer formed with various thin layers
thereon, comprising the steps of: covering the thin layers with
photoresist and then partially removing the photoresist from an
edge of the wafer; etching the wafer except for the edge which is
free from the photoresist with etching gas, so as to form a
predetermined pattern; forming a protective step on the edge at the
same time as the pattern is being formed; and performing
planarization of the wafer formed with the pattern and the
protective step.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects, features and advantages of the
present invention will be more apparent from the following detailed
description taken in conjunction with the accompanying drawings, in
which:
[0022] FIGS. 1A and 1B illustrate the procedures for forming a
semiconductor device according to the prior art;
[0023] FIG. 2 is a cross-sectional view of a processing chamber for
ion etching in an apparatus for fabricating a semiconductor device
according to one preferred embodiment of the present invention;
[0024] FIG. 3 is a cross-sectional view of a processing chamber for
ion etching in an apparatus for fabricating a semiconductor device
according to another preferred embodiment of the present invention;
and
[0025] FIGS. 4A and 4B illustrate the procedures for forming a
semiconductor device according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] Hereinafter, a preferred embodiment of the present invention
will be described with reference to the accompanying drawings. In
the following description and drawings, the same reference numerals
are used to designate the same or similar components, and so
repetition of the description on the same or similar components
will be omitted.
[0027] Referring to FIG. 2, in an apparatus for fabricating
semiconductor devices, a processing chamber 100 used in an ion
etching process is housed with a wafer chuck 101 for holding a
wafer 102, a gas injection head 103 for injecting gas toward the
wafer 102, and a clamp 104 for grasping the wafer 102 and
preventing an edge of the wafer from being etched.
[0028] The wafer 102 is subjected to deposition of various thin
layers thereon, and then patterned in a predetermined pattern by a
photolithography process and an etching process.
[0029] In the photolithography process, to restrict photoresist
contamination and particle generation, the edge of the wafer 102 is
rinsed, and only then is the photoresist on the edge removed.
[0030] The edge of the wafer 102 is grasped by the clamp 104, so
that it is not etched during the etching process. As a result, the
edge of the wafer is formed with a protective step.
[0031] In the CMP process following the etching process, a surface
of the wafer 102 is worked by slurry supplied from the exterior as
well as friction applied from a pad, so that the wafer 102 has a
different level of polishing resulting from a layout of the device,
a pattern density, a pattern thickness and so forth.
[0032] According to previous process in the art, during the CMP
process after depositing various thin layers and forming the
pattern, the edge of the wafer may be formed at a different height
than the rest of the wafer. However, according to the process of
the present invention, this different height can be prevented by
provision of the protective step on the edge.
[0033] Therefore, the protective step around the edge of the wafer
makes it possible to obtain planarization of the insulation layer
deposited on the pattern of the wafer 102 for the CMP process and
to prevent the edge of the wafer from being over-polished, and thus
reliability and productivity of the semiconductor device can be
increased.
[0034] Referring to FIG. 3, a processing chamber 100 according to
another embodiment of the present invention is housed with a wafer
chuck 101 for holding a wafer 102, a gas injection head 103 for
injecting gas toward the wafer 102, and a shadow ring 105 for
preventing an edge of the wafer 102 from being etched.
[0035] The wafer 102 is subjected to deposition of various thin
layers thereon, and then patterned in a predetermined pattern by a
photolithography process and an etching process.
[0036] In the photolithography process, to restrict photoresist
contamination and particle generation, the edge of the wafer 102 is
rinsed, and only then is the photoresist on the edge removed.
[0037] The edge of the wafer 102 is prevented from being etched
during the etching process by the shadow ring 105, so that it is
formed with a protective step.
[0038] In the CMP process following the etching process, a surface
of the wafer 102 is worked in cooperation with slurry supplied from
the exterior as well as friction applied from a pad, so that the
wafer 102 has a different level of polishing resulting from a
layout of the device, a pattern density, a pattern thickness and so
forth.
[0039] According to previous process in the art, during the CMP
process after depositing various thin layers and forming the
pattern, the edge of the wafer may be formed at a different height
than the rest of the wafer. However, according to the process of
the present invention, this different height can be prevented by
provision of the protective step on the edge.
[0040] Therefore, the protective step around the edge of the wafer
makes it possible to obtain planarization of the insulation layer
deposited on the pattern of the wafer 102 for the CMP process and
to prevent the edge of the wafer from being over-polished, and thus
reliability and productivity of the semiconductor device can be
increased.
[0041] The procedures for processing the semiconductor device using
the processing chamber as above-mentioned will be described with
reference to FIGS. 4A and 4B.
[0042] Referring to FIG. 4A, various thin layers is deposited on a
wafer 200, and then a predetermined pattern 210 is formed with the
resulting wafer by using a photolithography process and an etching
process. The layer deposited on the wafer 200 is an insulation
layer such as an oxide layer or a silicon nitride layer, or a
conductive layer such as a titan layer, a titan nitride layer, a
tungsten layer, an aluminum layer or a copper layer.
[0043] In the photolithography for patterning the wafer, the top
surface of the wafer with the deposited layer is covered with
photoresist so as to form the pattern 210. Only the photoresist
applied on an edge of the wafer is removed through rinsing so as to
prevent the remnant photoresist contamination and particle
generation. Here, the rinsed edge has a width of less than 3
millimeters.
[0044] The edge free from the photoresist is not exposed to etching
gas due to a clamp 104 provided in the processing chamber.
Therefore, the edge protected from the etching gas by means of the
clamp 104 is provided with a protective step 220 after completion
of the etching process.
[0045] This protective step 220 gets rid of the height difference
between the pattern 210 and the edge resulting from the CMP process
which follows the etching process, so that it can prevent the
pattern 210 and the edge from being over-polished.
[0046] Up to now, one preferred embodiment of the present invention
has been described, for example, with respect to formation of the
protective step using the clamp 104. Similarly, the shadow ring 105
is installed in the processing chamber 100 upwardly spaced apart
from the wafer chuck 101, so that the edge of the wafer is
protected from etching conditions during the etching process, thus
forming the protective step 220. With respect to formation of the
protective step 220, this configuration can also obtain the same
effects as the previous configuration.
[0047] FIG. 4 shows the wafer 200, which is formed with the
protective step 220 and the pattern 210 by the CMP process. This
protective step 220 allows the pattern 210 and the edge to avoid
being over-polished resulting from the height difference between
the pattern 210 and the edge during the CMP process.
[0048] As seen from the above, in the pattern formation process
prior to the planarization process for fabricating semiconductor
devices, to restrain the edge of the wafer from being etched during
the etching process, the edge is provided with the protective step
through employment of the clamp or the shadow ring. Therefore,
during the CMP process following the pattern formation process, the
edge can be prevented from being over-polished, and thus
reliability as well as productivity of the semiconductor devices
can be increased.
[0049] Although a preferred embodiment of the present invention has
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying
claims.
* * * * *