Mocvd Of Tio2 Thin Film For Use As Feram H2 Passivation Layer

Abstract

A method of forming an H.sub.2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiO.sub.x thin film, where 0<x<2, on a damascene structure; plasma space etching of the Ti or TiO.sub.x thin film to form a TiO.sub.x sidewall; annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film; depositing a layer of ferroelectric material; and metallizing the structure to form a FeRAM.

Description

FIELD OF THE INVENTION

[0001] This invention relates to oxide thin film processes for H.sub.2 passivation layers, ferroelectric memory device structures and integrated processes for ferroelectric non-volatile memory devices, and specifically, to a method of depositing a TiO.sub.2 thin film which is used as an H.sub.2 passivation layer.

BACKGROUND OF THE INVENTION

[0002] Metal, Ferroelectrics, Insulator, and Silicon (MFMIS) and Metal, Ferroelectrics, Insulator, and Silicon (MFIS) transistor ferroelectric memory devices have been proposed for use as FeRAM devices. In the integration processes of such devices, forming gas annealing generally is necessary to reduce trapped charges in high-k gate oxides and to improve the contact between metal connections and the source and the drain. However, forming gas annealing degrades the properties of ferroelectric thin films. Therefore, a H.sub.2 passivation layer, covering the ferroelectric thin film, is an important structure in fabrication of IT ferroelectric memory devices.

SUMMARY OF THE INVENTION

[0003] A method of forming an H.sub.2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiO.sub.x thin film, where 0<x<2, on a damascene structure; plasma space etching of the TiO.sub.x thin film to form a TiO.sub.x sidewall; annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film; depositing a layer of ferroelectric material; and metallizing the structure to form a FeRAM.

[0004] It is an object of the invention to provide a TiO.sub.2 thin film as a H.sub.2 passivation layer for improving the properties of 1 T ferroelectric memory devices.

[0005] Another object of the invention is to provide a TiO.sub.x thin film having good step coverage on a damascene structure.

[0006] A further object of the invention is to use a plasma space etching process on a TiO.sub.x thin film to form a TiO.sub.2 thin film as a H.sub.2 passivation layer.

[0007] This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIGS. 1-8 depict steps in device formation according to the method of the invention.

[0009] FIGS. 9 and 10 are microphotographs of the structure during device fabrication.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the method of the invention, TiO.sub.x may be deposited in either of two embodiments to make TiO.sub.2 as a H.sub.2 passivation layer. In the first embodiment of the method of the invention, a CVD process is used to deposit Ti or TiO.sub.x thin films on a damascene structure, providing good step coverage, followed by plasma space etching of the TiO.sub.x thin film to form a TiO.sub.x sidewall, and annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film. The second embodiment of the method of the invention includes a CVD process to deposit a TiO.sub.x or TiO.sub.2 thin film on a damascene structure, again providing good step coverage, annealing the TiO.sub.x thin film to form a TiO.sub.2 thin film, and plasma space etching the TiO.sub.2 thin film to form a sidewall on the trench structure.

[0011] Referring initially to FIG. 1, a silicon wafer 10 is prepared for fabrication of IC devices, which preparation may include doping to form a P-type silicon wafer, including threshold adjustment ion implantation, for use as a substrate for a Lead Germanium Oxide (Pb.sub.5Ge.sub.3O.sub.- 11) (PGO) MFMPOS one-transistor FeRAM device. FIG. 1 depicts the structure following wafer preparation, STI and filling of the trenches so formed with oxide 12, growth of a gate oxide 14 and deposition of a polysilicon layer 16, and, in this example, ion implantation to form an N.sup.+ source 18 and an N.sup.+ drain 20. The oxide is smoothed by CMP, photoresist is applied and the polysilicon layer etched.

[0012] FIG. 2 depicts the structure following CVD of oxide, which is smoothed by CMP, stopping at the level of polysilicon layer 16. A larger size bottom electrode 22, which, in the preferred embodiment, is an Iridium electrode is deposited and patterned. Another layer of oxide 24 is deposited by CVD and smoothed by CMP, stopping at the level of the Iridium layer. tetraethylorthosilicate oxide (oxane or TEOS) 26 is deposited by CVD, patterned and etched to form trench structures.

[0013] FIG. 3 depicts the structure following CVD of a TiO.sub.x layer 28, where 0<x<2. As will be apparent to those of skill in the art, when x=0, the CVD is only of titanium. The MOCVD process includes preparing a MOCVD precursor, including dissolving 0.2 mol Ti(OC.sub.3H.sub.7).sub.4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC.sub.3H.sub.7).sub.4. The precursor solution is injected into a vaporizer at temperature in the range of between about 80.degree. C. to 120.degree. C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases. The feed line is maintained at between about 80.degree. C. to 120.degree. C., the deposition temperature is between about 380.degree. C. to 420.degree. C., the deposition pressure is maintained at between about 0.5 torr to 5 torr, and the deposition time ranges from between about five minutes to thirty minutes, depending on the required TiO.sub.2 thickness. TiO.sub.x layer 28 may be, in the first embodiment of the method of the invention, plasma space etched, then annealed in an oxygen atmosphere to form a TiO.sub.2 thin film. The structure is HF dipped to clean the surface of Iridium bottom electrode 20, resulting in the structure depicted in FIG. 4. The plasma space etching process for TiO.sub.x thin film 22 includes setting TCP Rf power at about 370 W and setting the bias power to about 130 W at a chamber pressure of about 5 torr. The etching chemicals used in the process include BCl.sub.3 at a flow rate of about 30 sccm, and Cl.sub.2 at a flow rate of about 58 sccm.

[0014] FIG. 5 depicts the structure following selective deposition of a ferroelectric thin film 24 by MOCVD. The upper surface of the FE and TiO.sub.x extend above the level of the lastly deposited oxide layer because PGO may be selectively deposited on iridium and TiO.sub.2, but will not form on SiO.sub.2, therefor, the PGO will only be deposited on those areas which have exposed iridium and TiO.sub.2.

[0015] FIG. 6 depicts the structure following CMP of ferroelectric thin film 30, surrounding TiO.sub.x 28, and oxide 26.

[0016] FIG. 7 depicts the structure following deposition and annealing of a high-k oxide 32, deposition of a top electrode layer 34, and patterning and etching of the top electrode layer to form top electrodes 34.

[0017] FIG. 8 depicts the FeRAM constructed according to the first embodiment of the method of the invention following etching of contact holes and metallization 36.

[0018] FIG. 9 depicts the structure following deposition of TiO.sub.x thin film layer 28, which illustrates deposition on oxide trench structures with very good step coverage.

[0019] FIG. 10 depicts the structure after plasma space etching, and illustrates the TiO.sub.x side wall thin film formed on oxide trench structures.

[0020] In the second embodiment of the method of the invention, the same processes are followed, as described in connection with FIGS. 1-3. The annealing step, described in connection with FIG. 7, is next performed, converting TiO.sub.x to TiO.sub.2, which is then followed by the steps described in connection with FIGS. 4-6 and 8.

[0021] Thus, a method for MOCVD TiO.sub.2 thin film as FeRAM H.sub.2 passivation layer has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

Claims

1. A method of forming an H.sub.2 passivation layer in an FeRAM, comprising: preparing a silicon substrate, including doping to form a P-type silicon wafer, including threshold adjustment ion implantation, shallow trench isolation, of a gate oxide, deposition of a polysilicon layer, ion implantation to form an N.sup.+ source and an drain; smoothing the oxide by CMP, and patterning and etching the polysilicon layer; depositing a layer of TiO.sub.x thin film, where 0<x<2, on a damascene structure; plasma space etching of the TiO.sub.x thin film to form a TiO.sub.x sidewall; annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film; depositing a layer of ferroelectric material; and metallizing to form a FeRAM.

2. The method of claim 1 wherein said plasma space etching precedes said annealing.

3. The method of claim 1 wherein said annealing precedes said plasma space etching.

4. CANCELLED

5. The method of claim 1 which includes, after said preparing depositing a layer of oxide; smoothing the oxide by CMP, stopping at the level of the polysilicon layer; depositing a bottom electrode; depositing another layer of oxide by CVD; smoothing the other layer of oxide by CMP, stopping said smoothing at the level of the bottom electrode; depositing yet another layer of oxide by CVD; and patterning and etching the oxide layers to form trench structures.

6. The method of claim 1 wherein said plasma space etching of the TiO.sub.x thin film includes setting TCP RF power at about 370W, setting the bias power to about 130 W at a chamber pressure of about 5 torr; and using etching including BCl.sub.3 at a flow rate of about 30 sccm and Cl.sub.2 at a flow rate of about 58 sccm.

7. The method of claim 1 wherein said depositing a layer of TiO.sub.x thin film, where 0<x<2, includes preparing a MOCVD precursor, including dissolving about 0.2 mol Ti(OC.sub.3H.sub.7).sub.4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC.sub.3H.sub.7).sub.4.

8. The method of claim 7 which further includes injecting the precursor solution into a CVD chamber vaporizer at temperature in the range of between about 80.degree. C. to 120.degree. C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases; maintaining a CVD chamber feed line at a temperature of between about 80.degree. C. to 120.degree. C.; maintaining the deposition temperature at between about 380.degree. C. to 420.degree. C.; maintaining the deposition pressure at between about 0.5 torr to 5 torr, and continuing the deposition process for between about five minutes to thirty minutes.

9. A method of forming an H.sub.2 passivation layer in an FeRAM, comprising: preparing a silicon substrate, depositing a layer of TiO.sub.x thin film, where 0<x<2, on a damascene structure; plasma space etching of the TiO.sub.x thin film to form a TiO.sub.x sidewall, including setting TCP Rf power at about 370W, setting the bias power to about 130 W at a chamber pressure of about 5 torr; and using etching including BCl.sub.3 at a flow rate of about 30 sccm and Cl.sub.2 at a flow rate of about 58 sccm; annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film; depositing a layer of ferroelectric material; and metallizing to form a FeRAM.

10. The method of claim 9 wherein said preparing a silicon substrate includes doping to form a P-type silicon wafer, including threshold adjustment ion implantation, shallow trench isolation growth of a gate oxide, deposition of a polysilicon layer, ion implantation to form an N.sup.+ source and an drain; smoothing the oxide by CMP, and patterning and etching the polysilicon layer.

11. The method of claim 10 which includes, after said preparing, depositing a layer of oxide; smoothing the oxide by CMP; stopping at the level of the polysilicon layer; depositing a bottom electrode; depositing another layer of oxide by CVD, smoothing the other layer of oxide by CMP, stopping said smoothing at the level of the bottom electrode; depositing ye another layer of oxide by CVD; and patterning and etching of the oxide layers to form trench structures.

12. CANCELLED

13. The method of claim 9 wherein said depositing a layer of TiO.sub.x thin film, where 0<x<2, includes preparing a MOCVD precursor, including dissolving about 0.2 mol Ti(OC.sub.3H.sub.7).sub.4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC.sub.3H.sub.7).sub.4.

14. The method of claim 13 which further includes injecting the precursor solution into a CVD chamber vaporizer at temperature in the range of between about 80.degree. C. to 120.degree. C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases; maintaining a CVD chamber feed line at a temperature of between about 80.degree. C. to 120.degree. C.; maintaining the deposition temperature at between about 380.degree. C. to 420.degree. C.; maintaining the deposition pressure at between about 0.5 torr to 5 torr, and continuing the deposition process for between about five minutes to thirty minutes.

15. A method of forming an H.sub.2 passivation layer in an FeRAM, comprising: preparing a silicon substrate; depositing a layer of TiO.sub.x thin film, where 0<x<2, on a damascene structure, including preparing a MOCVD precursor, including dissolving about 0.2 mol Ti(OC.sub.3H.sub.7).sub.4 in Octane, resulting in a precursor solution having a concentration of 0.2 mol Ti(OC.sub.3H.sub.7).sub.4; annealing the TiO.sub.x side wall thin film to form a TiO.sub.2 thin film; plasma space etching of the TiO.sub.2 thin film to form a TiO.sub.2 sidewall; depositing a layer of ferroelectric material; and metallizing to form a FeRAM.

16. The method of claim 15 wherein said preparing a silicon substrate includes doping to form a P-type silicon wafer, including threshold adjustment ion implantation, shallow trench isolation, growth of a gate oxide, deposition of a polysilicon layer, ion implantation to form an N.sup.+ source and an drain; smoothing the oxide by CMP, and patterning and etching the polysilicon layer.

17. The method of claim 16 which includes, after said preparing, depositing a layer of oxide; smoothing the oxide by CMP, stopping at the level of the polysilicon layer; depositing a bottom electrode; depositing another layer of oxide by CVD, smoothing the other layer of oxide by CMP, stopping said smoothing at the level of the bottom electrode; depositing yet another layer of oxide by CVD; and patterning and etching both of the oxide layers to form trench structures.

18. The method of claim 15 wherein said plasma space etching of the TiO.sub.x thin film includes setting TCP RF power at about 370W, setting the bias power to about 130 W at a chamber pressure of about 5 torr and using etching including BCl.sub.3 at a flow rate of about 30 sccm and Cl.sub.2 at a flow rate of about 58 sccm.

19. CANCELLED

20. The method of claim 15 which further includes injecting the precursor solution into a CVD chamber vaporizer at temperature in the range of between about 80.degree. C. to 120.degree. C. by a liquid controller at a rate of between about 0.1 ml/min to 0.5 ml/min to form a precursor gases; maintaining a CVD chamber feed line at a temperature of between about 80.degree. C. to 120.degree. C.; maintaining the deposition temperature at between about 380.degree. C. to 420.degree. C.; maintaining the deposition pressure at between about 0.5 torr to 5 torr, and continuing the deposition process for between about five minutes to thirty minutes.