U.S. patent application number 10/693083 was filed with the patent office on 2004-12-16 for packaging assembly and method of assembling the same.
Invention is credited to Homma, Soichi, Tomono, Akira.
Application Number | 20040253803 10/693083 |
Document ID | / |
Family ID | 33509134 |
Filed Date | 2004-12-16 |
United States Patent
Application |
20040253803 |
Kind Code |
A1 |
Tomono, Akira ; et
al. |
December 16, 2004 |
Packaging assembly and method of assembling the same
Abstract
A packaging assembly includes a substrate; chip-site lands
disposed on the first surface; first solder balls connected to the
chip-site lands; second solder balls connected to the first solder
balls including solder materials having higher melting temperatures
than the first solder balls; a semiconductor chip having a
plurality of bonding pads connected to the second solder balls on a
surface of the semiconductor chip; and an underfill resin disposed
around the first and second solder balls.
Inventors: |
Tomono, Akira;
(Yokohama-shi, JP) ; Homma, Soichi; (Yokohama-shi,
JP) |
Correspondence
Address: |
Finnegan, Henderson, Farabow
Garrett & Dunner, L.L.P.
1300 I Street, N.W.
Washington
DC
20005-3315
US
|
Family ID: |
33509134 |
Appl. No.: |
10/693083 |
Filed: |
October 27, 2003 |
Current U.S.
Class: |
438/614 ;
257/778; 257/779; 257/E21.503; 257/E21.508; 257/E21.511;
257/E23.021; 257/E23.068; 438/108 |
Current CPC
Class: |
H01L 2224/05022
20130101; H01L 2924/01032 20130101; H01L 2924/01046 20130101; H01L
2924/01049 20130101; H01L 24/12 20130101; H01L 2924/01022 20130101;
H01L 2224/16225 20130101; H01L 2224/29111 20130101; H01L 2224/2919
20130101; H01L 2924/01322 20130101; H01L 2224/1147 20130101; H01L
2924/0133 20130101; H01L 2224/32225 20130101; H01L 2224/81801
20130101; H01L 2924/01067 20130101; H01L 24/29 20130101; H01L
2924/14 20130101; H01L 2224/13099 20130101; H01L 2224/83192
20130101; H01L 2924/01019 20130101; H01L 2924/01082 20130101; H01L
24/81 20130101; H01L 24/16 20130101; H01L 2224/05027 20130101; H01L
2924/01051 20130101; H01L 2924/01078 20130101; H01L 2924/01079
20130101; H01L 2224/05001 20130101; H01L 2224/05026 20130101; H01L
2924/01047 20130101; H01L 2924/01074 20130101; H01L 2924/01042
20130101; H01L 2924/0105 20130101; H01L 2924/01056 20130101; H01L
24/05 20130101; H01L 2924/15311 20130101; H01L 2924/351 20130101;
H01L 23/3128 20130101; H01L 2924/09701 20130101; H01L 2924/1579
20130101; H01L 2924/01013 20130101; H01L 23/49811 20130101; H01L
2224/29109 20130101; H01L 2224/73204 20130101; H01L 2924/01033
20130101; H01L 2924/30105 20130101; H01L 2924/01006 20130101; H01L
2924/01004 20130101; H01L 21/563 20130101; H01L 2224/05572
20130101; H01L 2924/15787 20130101; H01L 2224/13111 20130101; H01L
2224/0508 20130101; H01L 2224/73203 20130101; H01L 2924/19043
20130101; H01L 2924/01023 20130101; H01L 2924/0132 20130101; H01L
2924/01029 20130101; H01L 2924/014 20130101; H01L 24/11 20130101;
H01L 24/83 20130101; H01L 2924/0103 20130101; H01L 2924/01005
20130101; H01L 2924/0132 20130101; H01L 2924/01013 20130101; H01L
2924/01014 20130101; H01L 2924/0133 20130101; H01L 2924/01013
20130101; H01L 2924/01014 20130101; H01L 2924/01029 20130101; H01L
2924/0133 20130101; H01L 2924/01029 20130101; H01L 2924/01047
20130101; H01L 2924/0105 20130101; H01L 2924/0132 20130101; H01L
2924/0103 20130101; H01L 2924/0105 20130101; H01L 2924/0133
20130101; H01L 2924/0103 20130101; H01L 2924/0105 20130101; H01L
2924/01083 20130101; H01L 2924/0132 20130101; H01L 2924/01046
20130101; H01L 2924/01083 20130101; H01L 2924/0132 20130101; H01L
2924/01047 20130101; H01L 2924/01049 20130101; H01L 2924/0132
20130101; H01L 2924/01047 20130101; H01L 2924/0105 20130101; H01L
2924/0133 20130101; H01L 2924/01047 20130101; H01L 2924/0105
20130101; H01L 2924/01083 20130101; H01L 2924/0132 20130101; H01L
2924/01049 20130101; H01L 2924/0105 20130101; H01L 2924/0132
20130101; H01L 2924/01049 20130101; H01L 2924/01083 20130101; H01L
2924/0133 20130101; H01L 2924/01049 20130101; H01L 2924/0105
20130101; H01L 2924/01083 20130101; H01L 2924/0132 20130101; H01L
2924/0105 20130101; H01L 2924/01082 20130101; H01L 2924/0132
20130101; H01L 2924/0105 20130101; H01L 2924/01083 20130101; H01L
2224/16225 20130101; H01L 2224/13111 20130101; H01L 2924/00
20130101; H01L 2224/83192 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101; H01L 2224/13111 20130101; H01L 2924/01083
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/13111 20130101; H01L 2924/01047 20130101; H01L 2924/01083
20130101; H01L 2924/00014 20130101; H01L 2224/13111 20130101; H01L
2924/0103 20130101; H01L 2924/00014 20130101; H01L 2224/13111
20130101; H01L 2924/0103 20130101; H01L 2924/01083 20130101; H01L
2924/00014 20130101; H01L 2224/13109 20130101; H01L 2924/0105
20130101; H01L 2924/00014 20130101; H01L 2924/00014 20130101; H01L
2224/13111 20130101; H01L 2924/01082 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2224/13111 20130101; H01L
2924/01047 20130101; H01L 2924/00014 20130101; H01L 2224/13111
20130101; H01L 2924/01029 20130101; H01L 2924/01047 20130101; H01L
2924/00014 20130101; H01L 2224/13109 20130101; H01L 2924/0105
20130101; H01L 2924/01083 20130101; H01L 2924/00014 20130101; H01L
2924/3512 20130101; H01L 2924/00 20130101; H01L 2924/00 20130101;
H01L 2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00012 20130101; H01L 2924/00 20130101; H01L
2924/15311 20130101; H01L 2224/73204 20130101; H01L 2224/16225
20130101; H01L 2224/32225 20130101; H01L 2924/00 20130101; H01L
2224/2919 20130101; H01L 2924/00014 20130101; H01L 2224/83192
20130101; H01L 2224/73204 20130101; H01L 2224/16225 20130101; H01L
2224/32225 20130101; H01L 2924/00 20130101; H01L 2924/351 20130101;
H01L 2924/00 20130101; H01L 2924/15787 20130101; H01L 2924/00
20130101; H01L 2224/05664 20130101; H01L 2924/00014 20130101; H01L
2224/05155 20130101; H01L 2924/00014 20130101; H01L 2224/05166
20130101; H01L 2924/00014 20130101 |
Class at
Publication: |
438/614 ;
257/779; 257/778; 438/108 |
International
Class: |
H01L 021/44; H01L
023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 16, 2003 |
JP |
P2003 - 170905 |
Claims
What is claimed is:
1. A packaging assembly comprising: a substrate defined by a first
surface and a second surface opposing to the first surface; a
plurality of chip-site lands disposed on the first surface; a
plurality of first solder balls connected to the chip-site lands; a
plurality of second solder balls connected to the first solder
balls including solder materials having higher melting temperatures
than the first solder balls; a semiconductor chip having a
plurality of bonding pads connected to the second solder balls on a
surface of the semiconductor chip; and an underfill resin disposed
around the first and second solder balls.
2. The packaging assembly of claim 1, wherein the first solder
balls include at least one material selected from the group
consisting of Sn--Bi, Sn--Bi--Ag, Sn--Zn, Sn--Zn--Bi, Sn--Bi--In,
Bi--In, Sn--In, Bi--Pd, In--Ag, and Sn--Pb.
3. The packaging assembly of claim l,wherein the second solder
balls include at least one material selected from the group
consisting of Sn--Ag, An--Ag--Cu, Sn--Pb, and Sn--Zn.
4. The packaging assembly of claim 1, wherein a protective film
containing an organic synthetic resin is disposed on the surface of
the semiconductor chip.
5. The packaging assembly of claim 1, wherein a low dielectric
constant film is stacked on the surface of the semiconductor
chip.
6. The packaging assembly of claim 5, wherein an effective
dielectric constant of the low dielectric constant film is equal to
or less than 3.5.
7. The packaging assembly of claim 1, further comprising: a circuit
element merged in the semiconductor chip; and a
multilevel-interconnectio- n disposed on the surface of the
semiconductor chip having: a plurality of insulating films; and a
plurality of metallic interconnections alternatively stacked with
the insulating film, wherein the coherence strength of the stacked
structure to the semiconductor chip is equal to or less than 15
J/m.sup.2.
8. The packaging assembly of claim 7, wherein the insulating films
are made from low dielectric constant films.
9. The packaging assembly of claim 1, further comprising: a
plurality of second chip-site lands disposed on the first surface;
a plurality of third solder balls connected to the second chip-site
lands; a plurality of fourth solder balls connected to the third
solder balls including solder materials having higher melting
temperatures than the third solder balls; a second semiconductor
chip having a plurality of a second bonding pads connected to the
fourth solder balls on a surface of the second semiconductor chip;
and an underfill resin disposed around the third and fourth solder
balls.
10. The packaging assembly of claim 9, wherein the third solder
balls include at least one material selected from a group
consisting of Sn--Bi, Sn--Bi--Ag, Sn--Zn, Sn--Zn--Bi, Sn--Bi--In,
Bi--In, Sn--In, Bi--Pd, In--Ag, and Sn--Pb.
11. The packaging assembly of claim 9,wherein the fourth solder
balls include at least one material selected from a group
consisting of Sn--Ag, An--Ag--Cu, Sn--Pb, and Sn--Zn.
12. The packaging assembly of claim 9, wherein a low dielectric
constant film is stacked on the surface of the second semiconductor
chip.
13. The packaging assembly of claim 12, wherein an effective
dielectric constant of the low dielectric constant film is equal to
or less than 3.5.
14. The packaging assembly of claim 9, further comprising: a second
circuit element merged in the second semiconductor chip; and a
second multilevel-interconnection disposed on the second
semiconductor chip having: a plurality of insulating films; and a
plurality of metallic interconnections alternatively stacked with
the insulating film, wherein the coherence strength of the second
multilevel-interconnection to the second semiconductor chip is
equal to or less than 15 J/m.sup.2.
15. The packaging assembly of claim 14, wherein the insulating
films are made from low dielectric constant films.
16. A method of assembling a packaging assembly comprising:
preparing a substrate having a plurality of chip-site lands
disposed on the first surface of a substrate; disposing a plurality
of first solder balls on the chip-site lands; applying an under
fill resin around the chip-site lands and the first solder balls;
disposing a plurality of second solder balls on corresponding
bonding pads disposed on a semiconductor chip; aligning the first
solder balls with corresponding second solder balls; connecting the
first and second solder balls by melting the first solder balls;
and hardening the underfill resin.
17. The method of claim 16, wherein the connecting the first and
second solder balls includes disposing the substrate on an
assembling stage before melting the first solder balls.
18. The method of claim 16, wherein the preparing the substrate
prepares the substrate having the chip-site lands and a plurality
of second chip-site lands, the method further comprising: disposing
a plurality of third solder balls on the second chip-site lands;
applying a second underfill resin around the second chip-site lands
ant the third solder balls; disposing a plurality of fourth solder
balls on corresponding bonding pads disposed on a second
semiconductor chip; aligning the third solder balls with
corresponding fourth solder balls; and hardening the second
underfill resin.
19. The method of claim 16, further comprising: disposing a
plurality of external solder balls on corresponding external lands
disposed on the second surface of the substrate after hardening the
underfill resin; and forming a plurality of internal solder joints
from first and second solder balls by melting.
20. The method of claim 19, wherein the internal solder joints are
formed at least one material selected from the group consisting of
Sn--Bi, Sn--Bi--Ag, Sn--Zn, Sn--Zn--Bi, Sn--Bi--In, Bi--In, Sn--In,
Bi--Pd, In--Ag, Sn--Ag, Sn--Ag--Cu, Sn--Pb, and Sn--Zn.
21. The method of claim 16, further comprising stacking a low
dielectric constant film on the surface of the semiconductor chip,
before disposing the second solder balls.
22. The method of claim 21, further comprising applying a
protective film containing an organic synthetic resin on the
surface of the semiconductor chip, after stacking the low
dielectric constant film and before disposing the second solder
balls.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Applications No.
P2003-170905, filed on Jun. 16, 2003; the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to semiconductor device
technology, more specifically to a packaging assembly and a method
of assembling a packaging assembly using soldering technology.
[0004] 2. Description of the Related Art
[0005] Semiconductor integrated circuits such as LSI have achieved
higher levels of integration in recent years. Semiconductor devices
themselves are shrinking in geometrical size, increasing in the
degree of on-chip integration, and number of pin-counts are
increasing. As for the surface-mount package (SMP), flip chip
bonding technology which connects a semiconductor chip and a
circuit board with bumps has been employed widely. As for the flip
chip bonding technology, an encapsulating resin is applied on a
surface of a circuit board having bumps on the surface. Next, bumps
formed on an element side of a semiconductor chip and the bumps
formed on the circuit board are mated and contacted to each other.
Furthermore, the circuit board and the semiconductor chip are
heated around 150.degree. C. during a reflow process, and oxide
films and alien substances contained in the bumps are removed by
the resin which serves as a flux. Then, bumps of the circuit board
and the semiconductor chip are melted and connected during heating
process at 200.degree. C. After that, bumps and the resin are
hardened completely in the curing process.
[0006] In the SMP assembling process, solder bumps made of solder
paste are often used as bump electrodes. However, recently, it has
been pointed out that the outflow of lead from electronic products
dumped onto reclaimed land pollutes underground water. Thus,
throughout the world, manufacturers are changing the Sn--Pb
eutectic, used for mounting semiconductor chips or printed circuit
boards, to lead-free solder alloys.
[0007] Material examples of lead-free solder alloys, responding to
an environmental problem, are tin-silver (Sn-Ag) solder and
tin-zinc (Sn--Zn) solder. However, for lead-free solder alloys such
as Sn-Ag solder, the melting temperature is generally higher than
that of the conventional eutectic alloy. Therefore, lead-free
solder alloys having higher melting temperatures have to be
reflowed at a relatively high temperature of approximately
200.degree. C. However, when reflow is performed at high
temperature conditions, strong thermal stresses are applied to
semiconductor chips and mounting bases, and an aggravation of
coplanarity and a fall in reliability occurs. Moreover, when
organic materials are employed as a circuit board, a gas is
generated from the circuit board and that invades into an underfill
resin by reflowing at a high temperature of more than 200.degree.
C. On the other hand, while a curing reaction advances for the
underfill resin, the viscosity of the underfill resin rises. As a
result, the gas in the underfill resin remains as a void without
being ejected outside of the underfill resin. Furthermore, since
the heat shrinkage rate of underfill resin also increases by
reflowing, thermal stresses occur to the electrodes on the
semiconductor element side, and cracks in the electrodes arise.
[0008] Meanwhile, since recent microprocessors process huge
quantities of information at high speed, there have been problems
with the resistance of wires interconnecting transistors, and the
capacitances of insulators between interconnect wires. For example,
wire materials are changing from aluminum (Al) to copper (Cu)
having a high electrical conductivity, and insulators are changing
from silicon oxide films to materials having low dielectric
constants. However, such materials used in recent electronic
devices are generally weak in mechanical strength. In particular,
low dielectric constant films (hereinafter called low-k films) used
as insulators on semiconductor chips are significantly weak in
mechanical strength and in adhesion intensity because of their
porous structures necessary to ensure low dielectric constants.
Therefore, when reflowing to electrodes is performed using a
lead-free solder at a high melting temperature, strong thermal
stresses also occur in the low-k films within the semiconductor
chip. Furthermore, the low-k films disposed just under the solder
electrodes may be damaged by the heat and the adhesive strength
between the semiconductor chip and the mounting base is also
decreased.
SUMMARY OF THE INVENTION
[0009] An aspect of the present invention inheres in a packaging
assembly embracing a substrate defined by a first surface and a
second surface opposing to the first surface; a plurality of
chip-site lands disposed on the first surface; a plurality of first
solder balls connected to the chip-site lands; a plurality of
second solder balls connected to the first solder balls including
solder materials having higher melting temperatures than the first
solder balls; a semiconductor chip having a plurality of bonding
pads connected to the second solder balls on a surface of the
semiconductor chip; and an underfill resin disposed around the
first and second solder balls.
[0010] Another aspect of the present invention inheres in a method
of assembling a packaging assembly embracing preparing a substrate
having a plurality of chip-site lands disposed on the first surface
of a substrate; disposing a plurality of first solder balls on the
chip-site lands; applying an underfill resin around the chip-site
lands and the first solder balls; disposing a plurality of second
solder balls on corresponding bonding pads disposed on a
semiconductor chip; aligning the first solder balls with
corresponding second solder balls; connecting the first and second
solder balls by melting the first solder balls; and hardening the
underfill resin.
BRIEF DESCRIPTION OF DRAWINGS
[0011] FIG. 1 is a sectional view showing an example of packaging
assembly according to a first embodiment of the present
invention.
[0012] FIG. 1A is an enlarged view showing an example of a third
surface of a semiconductor chip shown in FIG. 1.
[0013] FIGS. 2 to 10 are sectional views showing a first example of
assembling the packaging assembly according to the first embodiment
of the present invention.
[0014] FIGS. 11 and 12 are sectional views showing a second example
of assembling the packaging assembly according to the first
embodiment of the present invention.
[0015] FIG. 13 is a sectional view showing a modification of the
first level assembly according to a first embodiment of the present
invention.
[0016] FIGS. 14 and 15 are sectional views showing an example of
assembling the modification of the packaging assembly shown in FIG.
13 according to the first embodiment of the present invention.
[0017] FIG. 16 is a sectional view showing an example of packaging
assembly according to a second embodiment of the present
invention.
[0018] FIGS. 17 and 18 are sectional views showing an example of
assembling the packaging assembly according to the second
embodiment of the present invention.
[0019] FIGS. 19 and 20 are sectional views showing a modification
of packaging assembly according to the second embodiment of the
present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0020] With reference to the accompanying drawings, first and
second embodiments of the present inventions are described. Various
embodiments of the present invention will be described with
reference to the accompanying drawings. It is to be noted that the
same or similar reference numerals are applied to the same or
similar parts and elements throughout the drawings, and the
description of the same or similar parts and elements will be
omitted or simplified. Generally, and as is conventional in the
representation of semiconductor packaging assemblies, it will be
appreciated that the various drawings are not drawn to scale from
one figure to another nor inside a given figure, and in particular
that the layer thicknesses are arbitrarily drawn for facilitating
the reading of the drawings. In the following descriptions,
numerous details are set forth such as specific signal values, etc.
to provide a thorough understanding of the present invention.
However, it will be obvious to those skilled in the art that the
present invention may be practiced without such specific
details.
[0021] (FIRST EMBODIMENT)
[0022] The packaging assembly 100 according to a first embodiment
of the present invention encompasses, as shown in FIG. 1, a
substrate 1 defined by a first surface and a second surface
opposing to the first surface, a plurality of chip-site lands 2a,
2b, 2c, and 2d disposed on the first surface, a plurality of a
first solder balls 3a, 3b, 3c, and 3d connected to the chip-site
lands 2a, 2b, 2c, and 2d, a plurality of a second solder balls 4a,
4b, 4c, and 4d connected to the first solder balls 3a, 3b, 3c, and
3d, a semiconductor chip 6 connected to the second solder balls 4a,
4b, 4c, and 4d on a third surface, and an underfill resin 7
disposed around the first solder balls 3a, 3b, 3c, and 3d and
second solder balls 4a, 4b, 4c, and 4d. The underfill resin 7 also
serves as a flux.
[0023] The substrate 1 is a kind of printed circuit board made from
a material including epoxy resin. The substrate 1 has: a wiring
layer 15 on a second surface, a plurality of chip-site lands 2a,
2b, 2c, and 2d on a first surface, and a protective film
(passivation layer) 18 which is made from SiO.sub.2 film, PSG film
and the like. The protective film 18 is stacked on the chip-site
lands 2a, 2b, 2c, and 2d. As the material of the substrate 1,
various organic synthetic resins and inorganic materials including
ceramic and glass can be used. Among organic synthetic resins,
phenolic resin, polyester resin, epoxy resin, polyimide resin,
fluoroplastic, and the like can be used. Meanwhile, paper, woven
glass fabric, a glass backing material, or the like is used as a
backing material that becomes a core informing a slab-shaped
structure. As a general in organic base material, ceramic can be
used. Alternatively, a metal substrate is used in order to improve
the heat-radiating characteristics. In the case where a transparent
substrate is needed, glass is used. As a ceramic substrate, alumina
(Al.sub.2O.sub.3), mullite (3Al.sub.2O.sub.3. 2SiO.sub.2), beryllia
(BeO), aluminum nitride (AlN), silicon nitride (SiN), and the like
can be used. Furthermore, it is possible to use a metal insulator
substrate in which a polyimide resin plate having high thermal
resistance is laminated onto metal, such as iron or copper, to form
a multi-layered structure. The thickness of the substrate 1 is not
limited. As for the chip-site lands 2a, 2b, 2c, and 2d, and the
wiring layer 15, electrically conductive material such as alminium
(Al,) alminium alloy (Al--Si, Al--Cu--Si), gold, copper, or the
like can be used. Alternatively, other electrodes can be provided
through a plurality of signal lines such as gate wires connected to
a plurality of gate electrodes. As gate electrodes, it is possible
to use polysilicon, refractory metal such as tungsten (W), titanium
(Ti), and molybdenum (Mo), silicides thereof (WSi.sub.2, TiSi.sub.2
and MoSi.sub.2), polycide using these silicides, or the like.
Alternatively, inside of the substrate 1, a plurality of vias can
be formed and a plurality of inner buried wires connected to the
vias can be disposed.
[0024] The chip-site lands 2a, 2b, 2c, and 2d are aligned at equal
intervals on the first surface of the substrate 1. The positions,
material, number, and the like of the chip-site lands 2a, 2b, 2c,
and 2d are not limited. The first solder balls 3a, 3b, 3c, and 3d
are connected on the chip-site lands 2a, 2b, 2c, and 2d. For the
first solder balls 3a, 3b, 3c, and 3d, solder materials having
lower melting temperature can be used. As for the first solder
balls 3a, 3b, 3c and 3d, materials selected from a tin-bismuth
(Sn--Bi) alloy, tin-bismuth-silver (Sn--Bi--Ag) alloy, tin-zinc
(Sn--Zn) alloy, tin-zinc-bismuth (Sn--Zn-Bi) alloy,
tin-bismuth-indium (Sn--Bi--In) alloy, bismuth-indium (Bi--In)
alloy, bismuth-palladium (Bi--Pd) alloy, indium-silver (In--Ag)
alloy, tin-lead (Sn=5 w %, Pb=95 w %) can be used. Melting
temperatures of a these alloys are as follows: Sn--Pb alloy and a
Sn--Bi-Ag alloy are from 138.degree. C. to 150.degree. C., Sn--Zn
alloy is from 198.degree. C. to 210.degree. C, Sn--Bi--In alloy is
from 190.degree. C. to 200.degree. C., Bi--In alloy is from
72.degree. C. to 120.degree. C., Sn-In alloy is from 116.degree. C.
to 130.degree. C., In--Ag alloy is from 141.degree. C. to
160.degree. C., Sn--Pb (Sn=5 w %, Pb=95 w %) alloy is from
320.degree. C. to 330.degree. C. In case where the outflow of lead
to the environment is taken into consideration, lead-free solders
having lower melting temperatures may be used for the first solder
balls 3a, 3b, 3c, and 3d. For example, when a material such as an
organic synthetic resin is used for the substrate 1, solder
materials having lower melting temperature such as Sn--Bi alloy and
Sn--Bi--Ag alloy can be used to prevent gas generation from the
substrate. The top surface of the first solder balls 3a, 3b, 3c and
3d are taking a shape of concave on the chip-site lands 2a, 2b, 2c
and 2d. The second solder balls 4a, 4b, 4c and 4d taking spherical
shapes are adhered on the top surface of the concave-shaped balls
(first solder balls) 3a, 3b, 3c, and 3d.
[0025] As shown in FIG. 1, the second solder balls 4a, 4b, 4c and
4d are connected to the bonding pads 5a, 5b, 5c and 5d disposed on
the third surface of the semiconductor chip 6. As for the second
solder balls 4a, 4b, 4c, and 4d, solder materials having higher
melting temperature than the first solder balls 3a, 3b, 3c, and 3d.
As for the second solder balls 4a, 4b, 4c, and 4d, materials
selected from a tin-silver (Sn--Ag) alloy, tin-silver-cupper
(Sn--Ag--Cu) alloy, tin-lead (Sn=63 w % Pb=35 w %) alloy, tin-zinc
(Sn--Zn) alloy can be used. Melting temperatures of these alloys
are as follows: a Sn--Ag alloy is from 220.degree. C. to
225.degree. C., Sn--Ag--Cu alloy is from 215.degree. C. to
230.degree. C., Sn--Pb (Sn=63 w % Pb=35 w %) alloy is from
180.degree. C. to 185.degree. C., Sn--Zn alloy is from 195.degree.
C. to 215.degree. C. Materials of the second solderballs 4a, 4b,
4c, and 4d may be changed depending on the melting temperature of
the material used for the first solder balls 3a, 3b, 3c, and 3d.
For example, when materials containing lead are used as solder
balls, Sn--Pb alloys composed of 5 w % tin and 95 w % lead can be
used as the first solder balls 3a, 3b, 3c and 3d and Sn--Pb alloys
composed of 63 w % tin and 37 w % of lead can be used as the second
solder balls 4a, 4b, 4c, and 4d. On the other hand, if the outflow
the lead to the environment is taken into consideration, lead-free
solders having lower melting temperature may be useful for the
second solder balls 4a, 4b, 4c, and 4d. For example, Sn--Bi alloys
may be used as the first solder balls 3a, 3b, 3c, and 3d, and
Sn--Ag alloys may be used as the second solder balls 4a, 4b, 4c,
and 4d.
[0026] As shown in FIG. 1A, a plurality of semiconductor elements
(circuit elements) 10s.sub.1, 10s.sub.2, 10d.sub.1, and 10d.sub.2,
which are heavily-doped impurity regions doped with donors or
acceptors of approximately 1.times.10.sup.18 cm.sup.31 3 to
1.times.10.sup.21 cm.sup.3 (such as source regions 10s.sub.1 and
10s.sub.2 and drain regions 10d.sub.1 and 10d.sub.2 or emitter
regions/collector regions) or the like are merged on the third
surface of the semiconductor chip 6. Insulating films 50, 51, 52,
53, and 54, made from low-k films are stacked into a multi-level
structure using low-k films on the semiconductor elements
10s.sub.1, 10s.sub.2, 10d.sub.1, and 10d.sub.2. Metallic
interconnections 50a, 50b, 50c, 50d, 51a, 51b, 51c, 51d, 51e, 53a,
53b, 54a, 54b, and 54c made of aluminum (Al) aluminum alloy (Al--Si
or Al--Cu--Si) or the like are alternatively stacked into the
insulating films 50, 51, 52, 53, and 54 so as to connect the
semiconductor elements 10s.sub.1, 10s.sub.2, 10d.sub.1, and
10d.sub.2. On the uppermost layer of the insulating films 54, low-k
films 12 as shown in FIG. 1 can be stacked into multi-level
structure. As shown in FIG. 1, bonding pads 5a, 5b, 5c and 5d are
formed just under the low-k film 12. Note that, prepositions, such
as "on" and "under" are defined with respect to a planar surface of
the substrate, regardless of the orientation the substrate is
actually held. As shown in FIG. 1, a protective film 13 made from a
silicon oxide film (SiO.sub.2), a PSG film, a BPSG film, a silicon
nitride film (Si.sub.3N.sub.4), a polyimide film or the like is
formed on the low-k film 12 and bonding pads 5a, 5b, 5c and 5d and
covers the third surface of the semiconductor chip 6. In the
protective film 13, a plurality of openings (not shown in FIG. 1)
are selectively provided so as to expose partially the top surface
of the respective bonding pads 5a, 5b, 5c and 5d. The barrier
metals 14a, 14b, 14c, and 14d, which are connected to the second
solder balls 4a, 4b, 4c, and 4d, are formed on the respective
bonding pads Sa, 5b, 5c and 5d. Note that, as for the low-k film
12, a material having an effective dielectric constant of the low-k
film is equal to or less than 3.5 is desirable to accomplish lower
effective dielectric constant between wirings. As for the low-k
films, for example, an inorganic insulator such as fluorine doped
silicon mono oxide (SiOF), carbon doped silicon mono oxide (SiOC),
organic silica, porous HSQ, benzocycrobutene (BCB) and porous films
made from above mentioned materials can be used. Moreover, to
prevent exfoliation, it can be agreeable that the coherence
strength of the insulating films 50, 51, 52, 53 and 54, and low-k
film 12 to the circuit elements 10s.sub.1, 10s.sub.2, 10d.sub.1,
and 10d.sub.2, metallic interconnections 50a, 50b, 50c, 50d, 51a,
51b, 51c, 51d, 51e, 53a, 53b, 54a, 54b, and 54c, and the
semiconductor chip 6 is equal to or less than 15 J/m.sup.2.
[0027] As the underfill resin 7, materials such as a resin
containing flux, a stiffening material having capability of flux, a
resin containing filler, and materials containing acid anhydrides
can be used. As for the resin, epoxy resin, acrylic resin, silicon
resin, polyimide resin and the like may be useful.
[0028] In the packaging assembly 100 according to the first
embodiment of the present invention, the first solder balls 3a, 3b,
3c, and 3d are disposed on the substrate 1. These first solder
balls 3a, 3b, 3c, and 3d are melted when heated at a lower
temperature of approximately 150.degree. C. Therefore, when an
organic synthetic resin is used for a material of 10 the substrate
1, because gas is not released from the substrate 1, voids are not
generated in the underfill resin 7. Moreover, since the substrate 1
and the semiconductor chip 6 are connected at a low temperature of
150.degree. C., the heat contraction of the substrate 1,
semiconductor chip 6, and resin 7 can be minimized. At the same
time, coplanarity and reliability of the substrate 1 may be
improved. Furthermore, since strong thermal stress is not added to
the second solder balls 4a, 4b, 4c, and 4d, the low-k film 12
disposed on the bonding pads 5a, 5b, 5c and 5d does not break. The
protective film 13 containing organic resins is disposed on the
surface of the low-k film 12. Therefore, the low-k film 12 will not
exfoliated.
[0029] Furthermore, when lead-free solder materials are used for
the first and second solder balls 4a, 4b, 4c,and 4d, 5a, 5b, 5c and
5d respectively, the packaging assembly 100 corresponding to the
environmental problem may be accomplished.
[0030] (FIRST ASSEMBLING METHOD OF THE FIRST EMBODIMENT)
[0031] Next, as shown in FIGS. 2 to 10, a first assembling method
of the packaging assembly 100 according to the first embodiment of
the present invention is described. Here, it is obvious that the
assembling method of the packaging assembly 100 described below is
one example, and the packaging assembly 100 is feasible by other
various assembly methods including modifications of the present
embodiment.
[0032] (a) First, the semiconductor chip having circuit elements,
insulating films, and metallic interconnections on the third
surface (omitted in FIG.2) are prepared. Then, as shown in FIG. 2,
a multi-level structure of low-k films 12A and 12B as interlayer
dielectrics are stacked and metal wires 11a, 11b, 11c, 11d, and 11e
made from Al, Al--Si, Al--Cu--Si, or the like are formed into the
low-k films 12A and 12B are formed. In the uppermost conductive
layer, the bonding pad 5a is formed. Next, a protective film 13
made from a Sio.sub.2 film, a PSG film, a BPSG film, a
Si.sub.3N.sub.4 film, a polyimide film, or the like is formed
around the bonding pads 5a. Subsequently, the protection film 13 is
partially provided with an opening 13A such that the bonding pad 5
is exposed.
[0033] (b) Next, as shown in FIG. 3 the titanium (Ti) film 4A,
nickel (Ni) film 14B on the Ti film 14A, and the Pd film 14C on the
Ni film 14B are formed gradually by use of a sputtering equipment
or an electron beam evaporation apparatus, a barrier metal film 14
is formed. Then, a photo resist film (not shown in FIG. 3) is
applied onto the barrier metal 14, and a gap is formed between the
photo resist films 16a and 16b. Next, as shown in FIG. 4, a
conductive material 17 is selectively buried in the groove between
the photo resist films 16a and 16b.
[0034] (c) Next, as shown in FIG. 5, the photo resist films 16a and
16b are stripped by solvents such as acetone, photo resist stripper
and the like. Part of the Pd film 14C, Ni film 14B, and Ti film 14A
are removed by use of the conductive material 14 as an etching
mask. As for the removal of the Pd film 14C and Ni film 14B, an
etching solution of aqua regia may be used. As for the removal of
the Ti film 14A, an etching solution of ethylene diamine
tetra-acetic acid may be used. Next, flux is applied around the
conductive material 17, and the conductive material 17 is heated
around 200.degree. C..about.220.degree. C. for 30 minutes during a
reflowing process. Then, as shown in FIG. 6, the second solder ball
4a is formed. After that, some electric testing may be performed to
the semiconductor chip 6.
[0035] (d) Next, as shown in FIG. 7, the substrate 1 which is made
from epoxy resin with a thickness of 30 .mu.m.about.60 .mu.m is
prepared. As for the substrate 1, phenolic resin, polyester resin,
epoxy resin, polyimide resin, fluoroplastic, and the like may be
used instead of epoxy resin. A wiring layer 15 made from copper or
the like is formed on the second surface of the substrate 1. On the
first surface, the chip-site land 2a is formed and the protective
film 18 made from SiO.sub.2 film, PSG film or the like is laminated
on the chip-site land 2a. Then, the protection film 18 is partially
provided with an opening 18A such that the chip-site land 2a is
exposed, thus forming the first solder ball 3a.
[0036] (e) Next, as shown in FIG. 8, underfill resin 7 having
property of flux is applied on the second surface of the substrate
1 so as to surround the chip-site lands 2a, 2b, 2c, and 2d, and the
first solder balls 3a, 3b, 3c, and 3d. Note that, a resin
containing filler can be used as the underfill resin 7 to decrease
the thermal expansion coefficient and to improve reliability. Then,
as shown in FIG. 9, the second solderballs 4a, 4b, 4c, and 4d are
aligned on the first solder balls 3a, 3b, 3c, and 3d so as to be
mated each other. After that, the substrate 1 and the semiconductor
chip 7 are introduced to a furnace or the like and reflow is
performed for 1.about.15 seconds at about 150.degree. C.,
pressurizing toward a substrate from upside of the semiconductor
chip 6. As a result, since the underfill resin 7 is activated,
oxides and impurities of the first solder balls 3a, 3b, 3c, and 3d
are removed by the flux capability of the underfill resin 7. Next,
the first solder balls 3a, 3b, 3c, and 3d are melted and adhered
around the second solder balls 4a, 4b, 4c, and 4d, as shown in FIG.
10. Moreover, in order to harden the underfill resin 7, the
substrate 1 and the semiconductor chip 6 are introduced to the oven
and dried.
[0037] As described above, the packaging assembly 100 as shown in
FIG. 1 can be assembled. According to the packaging assembly 100 of
the first embodiment of the present invention, the first solder
balls 3a, 3b, 3c and 3d disposed on the chip-site lands 2a, 2b, 2c,
and 2d melt at a temperature of about 150.degree. C. and connect
temporarily to the second solder balls 4a, 4b, 4c, and 4d.
Therefore, when an organic synthetic resin is used for a material
of the substrate 1, gas will not be released from the substrate 1,
and voids are not generated in the underfill resin 7. Moreover,
since the substrate 1 and the semiconductor chip 6 are connected at
a low temperature, the heat contraction of the substrate 1,
semiconductor chip 6, and resin 7 can be minimized. At the same
time, coplanarity and reliability of the substrate 1 may be
improved. Furthermore, since strong thermal stress is not incurred
to the second solder balls 4a, 4b, 4c, and 4d, the low-k film 12
disposed on the bonding pads 5a, 5b, 5c and 5d will not break. The
protective film 13 containing organic resin is disposed on the
surface of the low-k film 12. Therefore, the low-k film 12 is not
exfoliated.
[0038] (SECOND ASEMBLING METHOD OF THE FIRST EMBODIMENT)
[0039] Next, as shown in FIGS. 11 and 12, a second assembling
method of the packaging assembly 100 according to the first
embodiment of the present invention is described. Here, since a
sequence of the procedure of the second assembling method before
forming the second solder balls 4a, 4b, 4c, and 4d on the
semiconductor chip 6 or first solder balls 3a, 3b, 3c, and 3d on
the substrate 1 is substantially the same shown in FIGS. 2.about.8,
detailed explanation is omitted.
[0040] First, an assembling stage 20A and an assembling tool 20B
are heated to around 150.degree. C. Then, the second surface of the
substrate 1 having first solder balls 2a, 2b, 2c, and 2d on the
first surface is disposed on the assembling stage 20A by use of a
vacuum wand and the like. A fourth surface of the semiconductor
chip 6 having second solder balls 3a, 3b, 3c, and 3d on the third
surface is fixed on the assembling tool 20B by use of the vacuum
wand and the like. Next, as shown in FIG. 11, the second solder
balls 4a, 4b, 4c, and 4d are aligned with the first solder balls
3a, 3b, 3c, and 3d so as to be mated each other. Then, the
assembling stage 20A is pressurized by the assembling tool 20B. The
first solder balls 3a, 3b, 3c, and 3d are melted and their shapes
transformed, and are adhered to the second solder ball 4a, 4b, 4c,
and 4d. Moreover, the assembling stage 20A and the assembling tool
20B are cooled, the underfill resin 7 is cooled and hardened.
[0041] (MODIFICATION OF THE FIRST EMBODIMENT)
[0042] As shown in FIG. 13, a packaging assembly 101 according to a
modification of the first embodiment of the resent invention
differs from the packaging assembly 100 shown in FIG. 1 in that the
packaging assembly 101 further includes a plurality of second
chip-site lands 22a, 22b, 22c, and 22d, a plurality of third solder
balls 23a, 23b, 23c, and 23d connected to the second chip-site
lands 22a, 22b, 22c, and 22d, a plurality of fourth solder balls
24a, 24b, 24c, and 24d connected to the third solder balls 23a,
23b, 23c, and 23d, and a second semiconductor chip 26 connected to
the fourth solder balls 24a, 24b, 24c, and 24d. On the third
surface of the semiconductor chip 26, a second low-k film 32 is
disposed. A plurality of second bonding pads 25a, 25b, 2c, and 25d
are aligned under the second low-k film 32. A second protective
film 33 containing organic resin is formed on the surface of the
second low-k film 32. Although, it is omitted in FIG. 13, a second
circuit element are merged in the third surface or the second
semiconductor chip 26, and second multilevel-interconnection having
insulating films and metallic interconnections are disposed on the
third surface of the semiconductor chip 26 as shown in FIG. 1A.
[0043] Detailed explanation is omitted regarding the second
chip-site lands 22a, 22b, 22c, and 22d, the third solder balls 23a,
23b, 23c, and 23d, the fourth solder balls 24a, 24b, 2c, 25d, the
second low-k film 32, the second chip-side internal connection pad
25a, 25b, 2c, and 25d, and the second protective film 33, which
have the same organization as the chip-site lands 2a, 2b, 2c, and
2d, first solder balls 3a, 3b, 3c, and 3d, the second solder balls
4a, 4b, 4c, and 4d, the low-k film 12, the chip-side internal
connection pad 5a, 5b, 5c and 5d, and the protective film 33,
respectively.
[0044] (ASSEMBLING METHOD OF THE MODIFICATION)
[0045] Next, as shown in FIGS. 13 to 15, an assembling method of
the packaging assembly 101 according to the modification of first
embodiment of the present invention is described.
[0046] (a) First, the substrate 1 which is made from epoxy resin
with a thickness of 30 .mu.m.about.60 .mu.m is prepared. A wiring
layer 15 made from copper is formed on the second surface of the
substrate 1. On the first surface, the chip-site lands 2a, 2b, 2c,
and 2d, and the second chip-site lands 22a, 22b, 22c, and 22d are
formed. Then, the protective film 18 made from SiO.sub.2 film, PSG
film or the like is laminated on the chip-site lands 2a, 2b, 2c,
and 2d, and the second chip-site lands 22a, 22b, 22c, and 22d. The
protection film 18 is partially removed such that the chip-site
lands 2a, 2b, 2c, and 2d, and the second chip-site lands 22a, 22b,
22c, and 22d are exposed. Thus, the first solderballs 3a, 3b, 3c,
and 3d are formed on the chip-site lands 2a, 2b, 2d, and 2d. The
third solder balls 23a, 23b, 23c, and 23d are formed on the second
chip-site lands 22a, 22b, 22c, and 22d. Next, as shown in FIG. 14,
the substrate 1 is disposed on the assembling stage 20A which is
heated around 150.degree. C.
[0047] (b) Next, underfill resin 7A serves as flux is applied on
the second surface of the substrate 1 so as to surround the
chip-site lands 2a, 2b, 2c, and 2d, and the first solder balls 3a,
3b, 3c, and 3d. Underfill resin (second underfill resin) 7B serves
as flux is applied so as to surround the second chip-site lands
22a, 22b, 22c, and 22d, and the third solder balls 23a, 23b, 23c,
and 23d. Then, underfill resins 7A and 7B are heated and activated
by the heat of assembling stage 20A. As a result, oxides and
impurities included on the surface of first solder balls 3a, 3b,
3c, and 3d and third solder balls 23a, 23b, 23c, 23d are removed by
the underfill resins 7A and 7B serving as flux. After that, the
surfaces of the first solder balls 3a, 3b, 3c, and 3d are exposed
on the surface of the underfill resin 7A. The surface of the third
solder balls 23a, 23b, 23c, and 24d are also exposed on the surface
or the underfill resin 7B.
[0048] (c) Next, as shown in FIG. 14, the second solder balls 4a,
4b, 4c, and 4d are aligned on the first solder balls 3a, 3b, 3c,
and 3d so as to be mated to each other, and pressurized by being
pushed from the fourth surface of the semiconductor chip 6 toward
the substrate 1. Then, the first solder balls 3a, 3b, 3c, and 3d
are melted with heat from the assembling stage 20A and adhered to
the around of second solder balls 4a, 4b, 4c, and 4d. Next, as
shown in FIG. 15, the fourth solder balls 24a, 24b, 24c, and 24d
connected with the second semiconductor chip 25 are aligned on the
third solder balls 23a, 23b, 23c, and 23d so as to be mated each
other, and pressurized by being pushed from fourth surface of the
second semiconductor chip 26 toward the substrate 1. Then, the
third solder balls 23a, 23b, 23c, and 23d are melted with heat from
the assembling stage 20A and adhered to the around of fourth solder
balls 24a, 24b, 24c, and 24d. Moreover, the assembling stage 20A
and the assembling tool 20B are cooled, and the underfill resin 7
is cooled and hardened.
[0049] As described above, the packaging assembly 101 as shown in
FIG. 13 can be manufactured. According to the packaging assembly
101 of the first embodiment of the present invention, the first
solder balls 3a, 3b, 3c and 3d disposed on the chip-site lands 2a,
2b, 2c, and 2d melt with the heat from assembling stage 20A of
about 150.degree. C. to be connected temporarily to the second
solder balls 4a, 4b, 4c, and 4d. Therefore, when second
semiconductor chip 26 is mounted next to semiconductor chip 6, it
can prevent the position of semiconductor chips 6 and 26 from
shifting due to the flow of underfill resins 7A and 7B. Moreover,
two or more semiconductor chips can be mounted adjacently. Since
the packaging assembly 101 shown in FIG. 13 can be mounted at a low
temperature of 150.degree. C., gas is not released from the
substrate 1, and voids are not generated in the underfill resin 7
even if an organic synthetic resin is used for a material of the
substrate 1. Furthermore, since heat expansion of the substrate 1
and semiconductor chips 6 and 26, and heat contraction of the
underfill resin 7 can be suppressed at lower level, strong thermal
stresses are not be incurred to bonding pads 5a, 5b, 5c and 5d, and
second bonding pads 25a, 25b, 2c, and 25d. Therefore, thermal
stresses applied to the low-k film 12 and second low-k film 32
which are disposed close to the bonding pads 5a, 5b, 5c and 5d, and
second bonding pads 25a, 25b, 2c, and 25d, can be minimized and
breakage of the films can be prevented.
[0050] (SECOND EMBODIMENT)
[0051] The packaging assembly 102 according to a first embodiment
of the present invention encompasses, as shown in FIG. 16, a
plurality of internal solder joints 8a, 8b, 8c, and 8d disposed
between chip-site lands 2a, 2b, 2c, and 2d, and bonding pads 5a,
5b, 5c and 5d. On the second surface of the substrate 1, a
plurality of external lands 15a, 15b, 15c, and 15d are disposed. A
plurality of external solder balls 21a, 21b, 21c, and 21d are
connected on the external lands 15a, 15b, 15c, and 15d,
respectively. Others are the same as a packaging assembly 100 shown
in FIG. 1, detailed explanations are omitted.
[0052] The internal solder joints 8a, 8b, 8c, and 8d are electrodes
mixed with first solder balls 3a, 3b, 3c, and 3d and second solder
balls 4a, 4b, 4c, and 4d as shown in FIG. l. The internal solder
joints 8a, 8b, 8c, and 8d have higher melting temperature than
first solder balls 3a, 3b, 3c, and 3d, and have lower melting
temperature than second solder balls 4a, 4b, 4c, and 4d. As for the
internal solder joints 8a, 8b, 8c, and 8d, at least two kinds of
solder materials having higher and lower melting temperatures can
be included. For solder materials having lower melting temperature,
Sn--Bi alloys, Sn--Bi--Ag alloys, Sn--Zn alloys, Sn--Zn--Bi alloys,
An--Bi--In alloys, Bi--In alloy, Sn--In alloys, In--Ag alloys,
Sn--Pb (Sn=5 w %, Pb=95 w %) can be used. For the materials having
higher melting temperature, for example, Sn--Ag alloys, Sn--Ag--Cu
alloys, Sn--Pb (Sn-=63 w %, Pb=37 w %) alloys, and Sn--Zn alloys
can be used.
[0053] As for the external lands 15a, 15b, 15c, and 15d, conductive
material such as alminium (Al,) alminium alloy (Al--Si,
Al--Cu--Si), gold, copper, or the like can be used.
[0054] Alternatively, other electrodes can be provided through a
plurality of signal lines such as gate wires connected to a
plurality of polysilicon gate electrodes. Instead of gate
electrodes made from polysilicon, it is possible to use gate
electrodes made from a metal having a higher melting temperature
including W, Ti, and Mo, silicides thereof (WSi.sub.2, TiSi.sub.2
and MoSi.sub.2), polycide using these silicides, or the like.
Furthermore, it is also possible to mount a motherboard or the like
on the external lands 15a, 15b, 15c, and 15d.
[0055] As for the external solder balls 21a, 21b, 21c, and 21d,
solder materials having higher melting temperature than the first
solder balls 3a, 3b, 3c, and 3d can be used. As for the external
solder balls 21a, 21b, 21c, and 21d, materials selected from a
Sn--Ag alloy, Sn--Ag--Cu alloy, Sn--Pb (Sn=63 w % Pb=35 w %) alloy,
Sn--Zn alloy can be used. Mixtures or compounds made from materials
such as Au, Ag, Cu, Ni, Fe, Pd, Sn, Pb, Ag, Bi, Zn, In, Sb, Cu, Ge
can be also used.
[0056] (ASSEMBLING METHOD OF THE SECOND EMBODIMENT)
[0057] Next, as shown in FIGS. 17 and 18, an assembling method of
the packaging assembly 102 according to the second embodiment of
the present invention is described. Here, since the second
assembling method before forming second solder balls 4a, 4b, 4c,
and 4d on the semiconductor chip 6 or first solder balls 3a, 3b,
3c, and 3d on the substrate 1 is substantially the same shown in
FIGS. 2.about.8, detailed explanation is omitted.
[0058] A photo resist film (not shown) is coated on the wiring
layer 15 (shown in FIG. 1) delineated on the second surface by use
of photolithography technology. The wiring layer 15 is partially
delineated with the photo resist film as an etching mask, and
external lands 15a, 15b, 15c, and . . . 15d are formed. A
protective film (not shown) which is made from SiO.sub.2, SiN and
the like can be delineated so as to be surround the external lands
15a, 15b, 15c, and 15d. Then, as shown in FIG. 17, the external
solder balls 21a, 21b, 21c, and 21d containing such as Sn--Ag
alloys are formed on the external lands 15a, 15b, 15c, and 15d, and
heated around 200.degree. C., reflow is performed. Heat from
performing reflow is conveyed to first solder balls 3a, 3b, 3c, and
3d, and second solder balls 4a, 4b, 4c, and 4d. As a result, first
solder balls 3a, 3b, 3c, and 3d, and second solder balls 4a, 4b,
4c, and 4d are melted to be formed internal solder joints 8a, 8b,
8c, and 8d. Since the internal solder joints 8a, 8b, 8c, and 8d are
formed from a mixture of first solder balls 3a, 3b, 3c, and 3d, and
second solder balls 4a, 4b, 4c, and 4d, the internal solder joints
8a, 8b, 8c, and 8d have higher melting temperature than first
solder balls 3a, 3b, 3c, and 3d, and have lower melting temperature
than second solder balls 4a, 4b, 4c, and 4d.
[0059] As described above, the packaging assembly 102 shown n FIG.
16 can be manufactured. According to the packaging assembly 102 of
the second embodiment of the present invention, the first solder
balls 3a, 3b, 3c and 3d melt at a heat of about 150.degree. C.and
connect temporarily to the second solder balls 4a, 4b, 4c, and 4d.
Therefore, when an organic synthetic resin is used for a material
of the substrate 1, gas is not released from the substrate 1, and
voids are not generated in the underfill resin 7. Moreover, since
the substrate 1 and the semiconductor chip 6 are connected at a low
temperature, thermal stresses applied to the low-k film 12 disposed
on the bonding pads 5a, 5b, 5c, and 5d can be minimized.
Furthermore, since complete connection is accomplished by forming
internal solder joints 8a, 8b, 8c, and 8d to be heated by reflowing
process, the reliability of the first level assembly 102 can be
improved. Accordingly, internal solder joints 8a, 8b, 8c, and 8d do
not melt even if in a test of a continuous at high temperature of
150.degree. C, or a heat cycle test which repeatedly varies an
atmosphere from 120.degree. C. to -55.degree. C.
[0060] (MODIFICATION OF THE SECOND EMBODIMENT)
[0061] The packaging assembly 103 according to a second embodiment
of the present invention encompasses, as shown in FIG. 19, a
plurality of second internal solder joints 28a, 28b, 28c, and 28d
are disposed between second chip-site lands 22a, 22b, 22c, and 22d,
and second bonding pads 25a, 25b, 2c, and 25d. A plurality of
external lands 15a, 15b, 15c, . . . , 15j are disposed on the first
surface opposite to the second chip-site lands 22a, 22b, 22c, and
22d. A plurality of external solder ball 21a, 21b, 21c, . . . , 21j
are connected on the external lands 15a, 15b, 15c, . . . , 15j,
respectively. Others are the same as a packaging assembly 101 shown
in FIG. 13, explanations are omitted.
[0062] The second internal solder joints 28a, 28b, 28c, and 28d are
electrodes mixed with third solder balls 23a, 23b, 23c, and 23d,
and fourth solder balls 24a, 24b, 24c, and 24d as shown in FIG. 20.
The second internal solder joints 28a, 28b, 28c, and 28d have
higher melting temperature than third solder balls 23a, 23b, 23c,
and 23d, and have lower melting temperature than fourth solder
balls 24a, 24b, 24c, and 24d. As for the second internal solder
joints 28a, 28b, 28c, and 28d, at least two kinds of solder
materials having higher melting temperature and lower melting
temperature can be used. For solder materials of lower melting
temperature, Sn--Bi alloys, Sn--Bi--Ag alloys, Sn--Zn alloys,
Sn--Zn--Bi alloys, An--Bi--In alloys, Bi--In alloy, Sn--In alloys,
In--Ag alloys, Sn--Pb (Sn=5 w %, Pb=95 w %) can be used. Materials
of higher melting temperature, for example, Sn--Ag alloys,
Sn--Ag--Cu alloys, Sn--Pb (Sn-=63 w %, Pb=37 w %) alloys, and
Sn--Zn alloys can be used.
[0063] (ASSEMBLING METHOD)
[0064] Next, as shown in FIGS. 19 and 20, an assembling method of
the packaging assembly 103 according to the modification of the
second embodiment of the present invention is described.
[0065] A photo resist film (not shown) is delineated on the wiring
layer 15 formed on the second surface by use of photolithography
technology. The wiring layer 15 is stripped with the photo resist
film as an etching mask, external lands 15a, 15b, 15c, . . . 15j
are formed. A protective film which is made from SiO.sub.2, SiN and
the like can be formed so as to be surround the external lands 15a,
15b, 15c, and . . . 15j. Then, as shown in FIG. 20, the outer
connection solder balls 21a, 21b, 21c. . . 21j containing such as
Sn--Ag alloys are formed on the external lands 15a, 15b, 15c, . . .
, 15j and heated around 200.degree. C., reflow is performed. Heat
from performing reflow is conveyed to first and third solder balls
3a, 3b, 3c, d 3d, 23a, 23b, 23c, and 23d, and second and fourth
solder balls 4a, 4b, 24c, 24d, and 24a, 24b, 24c, and 24d. As a
result, first and third solder balls 3a, 3b, 3c, 3d, 23a, 23b, 23c,
and 23d, and second and fourth solder balls 4a, 4b, 4c, 4d, 24a,
24b, 24c, and 24d are melted to be formed internal solder joints
8a, 8b, 8c, and 8d and second internal solder joints 28a, 28b, 28c,
and 28d.
[0066] As described above, the packaging assembly 103 as shown in
FIG. 19 can be assembled. According to the packaging assembly 103
of the modification of second embodiment of the present invention,
third solder balls 23a, 23b, 23c, and 23d, and fourth solder balls
24a, 24b, 24c, and 24d are connected temporarily after being
connected with first solder balls 3a, 3b, 3c, and 3d and second
solder balls 4a, 4b, 4c, and 4d. Therefore, when the second
semiconductor chip 26 is mounted next to the first semiconductor
chip 6, shifting of the position of chips 6 and 26 caused by the
flow of underfill resin 7 can be prevented. Moreover, two or more
semiconductor chips can be mounted adjacently. Since the packaging
assembly 103 shown in FIG. 19 can be mounted at a low temperature
of 150.degree. C., gas is not released from the substrate 1, and
not generated in the underfill resin 7 even if an organic synthetic
resin is used for a material of the substrate 1. Furthermore, since
heat expansion of the substrate 1 and semiconductor chips 6 and 26,
and heat contraction of the underfill resin 7 can be suppressed at
lower level, strong thermal stresses are not be incurred to bonding
pads 5a, 5b, 5c and 5d, and second bonding pads 25a, 25b, 2c, and
25d. Therefore, thermal stresses applied to the low-k film 12 and
second low-k film 32 which are disposed close to the bonding pads
5a, 5b, 5c and 5d, and second bonding pads 25a, 25b, 2c, and 25d,
can be minimized and the breakage of the films can be prevented.
Furthermore, since complete connection is accomplished by forming
internal solder joints 8a, 8b, 8c, and 8d, and second internal
solder joints 28a, 28b, 28c, and 28d, to be heated by reflowing
process, the reliability of the first level assembly 102 can be
improved. Accordingly, first and second internal solder joints 8a,
8b, 8c, 8d, 28a, 28b, 28c, and 28d do not melt even if in a test of
a continuous at high temperature of 150.degree. C., or a heat cycle
test which repeatedly varies an atmosphere from 120.degree. C.to
-55.degree. C.
[0067] (OTHER EMBODIMENTS)
[0068] Various modifications will become possible for those skilled
in the art upon receiving the teachings of the present disclosure
without departing from the scope thereof.
[0069] As for the packaging assembly 100, 101, 102, and 103 shown
in FIGS. 1.about.19, materials of the solder balls 3a.about.3d,
4a.about.4d, 23a.about.23d, 24a.about.24d can be partially changed.
When the solder balls 3a.about.3d, 4a.about.4d, 23a.about.23d,
24a.about.24d are heated by performing reflowing, the semiconductor
chips 6 and 26 and substrate 1 are elongated respectively. The
thermal stresses caused by heat expansion (elongation) occurring at
the central parts of the semiconductor chips 6 and 26 or the
substrate 1 are weak. However, thermal stresses occurring at the
edges of the semiconductor chips 6 and 26 and the substrate 1 are
strong. Therefore, lead-free solders having higher melting
temperature can be applied to the second solder joints 4b and 4c.
The lead-free solders having lower melting temperatures can be
applied to the second solder joints 4a and 4d. Accordingly, it is
possible to prevent the breakage of materials that have weak
mechanical strengths formed in the circuit elements of the
semiconductor chip 6, particularly, the breakage of the low-k film
12 disposed directly on the second solder joints 4a, 4b, 4c, and
4d.
* * * * *