U.S. patent application number 10/461367 was filed with the patent office on 2004-12-16 for ferroelectric memory device.
Invention is credited to Hoya, Katsuhiko, Rehm, Nobert, Takashima, Daisaburo.
Application Number | 20040252542 10/461367 |
Document ID | / |
Family ID | 33434922 |
Filed Date | 2004-12-16 |
United States Patent
Application |
20040252542 |
Kind Code |
A1 |
Hoya, Katsuhiko ; et
al. |
December 16, 2004 |
FERROELECTRIC MEMORY DEVICE
Abstract
A ferroelectric memory device includes a memory cell array
having memory cells arranged in a matrix form. Each of the memory
cells includes a cell transistor and a ferroelectric capacitor. It
further includes a first dummy bit line arranged outside a bit line
arranged on an end portion of the memory cell array and separated
from the bit line arranged on the end portion of the memory cell
array with an interval which is the same as a pitch between the bit
lines in the memory cell array and having the same width as the bit
line, and a first dummy memory cell connected to the first dummy
bit line and having the same structure as the memory cell.
Inventors: |
Hoya, Katsuhiko;
(Yokohama-shi, JP) ; Takashima, Daisaburo;
(Yokohama-shi, JP) ; Rehm, Nobert; (Yokohama-shi,
JP) |
Correspondence
Address: |
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, P.C.
1940 DUKE STREET
ALEXANDRIA
VA
22314
US
|
Family ID: |
33434922 |
Appl. No.: |
10/461367 |
Filed: |
June 16, 2003 |
Current U.S.
Class: |
365/145 |
Current CPC
Class: |
G11C 11/22 20130101 |
Class at
Publication: |
365/145 |
International
Class: |
G11C 011/22 |
Claims
1. A ferroelectric memory device comprising: a memory cell array
having a plurality of memory cells arranged in a matrix form, each
of the memory cells including a cell transistor and a ferroelectric
capacitor, one of source and drain regions of the cell transistor
being electrically connected to a corresponding one of a plurality
of bit lines, a gate of the cell transistor being electrically
connected to a corresponding one of a plurality of word lines, the
other one of the source and drain regions of the cell transistor
being electrically connected to one electrode of the ferroelectric
capacitor, the other electrode of the ferroelectric capacitor being
electrically connected to a corresponding one of a plurality of
plate lines; a first dummy bit line arranged outside a bit line
arranged on an end portion of the memory cell array, and separated
from the bit line arranged on the end portion of the memory cell
array with an interval which is the same as a pitch between the bit
lines in the memory cell array, the first dummy bit line having the
same width as the bit line, and not electrically connected to a
data line which transmits data; and a first dummy memory cell
electrically connected to the first dummy bit line and including a
cell transistor and a ferroelectric capacitor.
2. The ferroelectric memory device according to claim 1, further
comprising a second dummy bit line arranged outside the first dummy
bit line and fixed at a predetermined potential.
3. The ferroelectric memory device according to claim 1, further
comprising a second dummy bit line arranged outside the first dummy
bit line, and separated from the first dummy bit line with the
interval, the second dummy bit line having the same width as the
bit line, and not electrically connected to a data line which
transmits data, and a second dummy memory cell to which data
complementary to data of the first dummy memory cell is
transferred, the second dummy memory cell being electrically
connected to the second dummy bit line and including a cell
transistor and a ferroelectric capacitor.
4. The ferroelectric memory device according to claim 3, further
comprising a sense amplifier circuit which is electrically
connected to the first and second dummy bit lines and senses a
signal based on potentials of the first and second dummy bit
lines.
5. The ferroelectric memory device according to claim 4, further
comprising a third dummy bit line arranged outside the second dummy
bit line and fixed at a predetermined potential.
6. A ferroelectric memory device comprising: a first memory cell
array having a plurality of memory cells arranged in a matrix form,
each of the memory cells including a cell transistor and a
ferroelectric capacitor, one of source and drain regions of the
cell transistor being electrically connected to a corresponding one
of a plurality of first bit lines, a gate of the cell transistor
being electrically connected to a corresponding one of a plurality
of first word lines, the other one of the source and drain regions
of the cell transistor being electrically connected to one
electrode of the ferroelectric capacitor, the other electrode of
the ferroelectric capacitor being electrically connected to a
corresponding one of a plurality of first plate lines; a second
memory cell array arranged adjacent to the first memory cell array
and having a plurality of memory cells arranged in a matrix form,
each of the memory cells including a cell transistor and a
ferroelectric capacitor, one of source and drain regions of the
cell transistor being electrically connected to a corresponding one
of a plurality of second bit lines, a gate of the cell transistor
being electrically connected to a corresponding one of a plurality
of second word lines, the other one of the source and drain regions
of the cell transistor being electrically connected to one
electrode of the ferroelectric capacitor, the other electrode of
the ferroelectric capacitor being electrically connected to a
corresponding one of a plurality of second plate lines; a first
dummy bit line arranged outside a first bit line arranged on an end
portion of the first memory cell array; a first dummy memory cell
electrically connected to the first dummy bit line and including a
cell transistor and a ferroelectric capacitor; a second dummy bit
line arranged outside a second bit line arranged on an end portion
of the second memory cell array; and a second dummy memory cell
electrically connected to the second dummy bit line and including a
cell transistor and a ferroelectric capacitor.
7. The ferroelectric memory device according to claim 6, further
comprising a sense amplifier circuit which is electrically
connected to the first and second dummy bit lines and senses a
signal based on potentials of the first and second dummy bit
lines.
8. The ferroelectric memory device according to claim 7, wherein a
pair of dummy bit lines which includes the first and second dummy
bit lines has open bit-line architecture in which the first dummy
memory cell is connected to the first word line and the second
dummy memory cell is connected to the second word line.
9. The ferroelectric memory device according to claim 7, further
comprising a third dummy bit line arranged outside the first and
second dummy bit lines and fixed at a predetermined potential.
10. A ferroelectric memory device comprising: a memory cell array
having memory cells arranged in a matrix form, each memory cell
including a cell transistor and a ferroelectric capacitor, one of
source and drain regions of the cell transistor being electrically
connected to a corresponding one of bit lines, a gate of the cell
transistor being electrically connected to a corresponding one of
word lines, the other one of the source and drain regions of the
cell transistor being electrically connected to one electrode of
the ferroelectric capacitor, the other electrode of the
ferroelectric capacitor being electrically connected to a
corresponding one of plate lines; an auxiliary word line arranged
in parallel to the word line above the memory cell array; a stitch
portion arranged in the memory cell array and electrically
connected to the word line and auxiliary word line; a first dummy
bit line arranged between the stitch portion and one of the two bit
lines disposed on both sides of the stitch portion and separated
from the bit line among the two bit lines with an interval which is
the same as a pitch between the bit lines in the memory cell array
and having the same width as the bit line; a first dummy memory
cell electrically connected to the first dummy bit line and having
the same structure as the memory cell; a second dummy bit line
arranged between the stitch portion and the other one of the two
bit lines disposed on both sides of the stitch portion and
separated from the other bit line among the two bit lines with an
interval which is the same as the pitch between the bit lines in
the memory cell array and having the same width as the bit line;
and a second dummy memory cell electrically connected to the second
dummy bit line and having the same structure as the memory
cell.
11. The ferroelectric memory device according to claim 10, wherein
data, which is data complementary to data transferred to the first
dummy memory cell, is transferred to the second dummy memory cell
and the device further comprises a sense amplifier circuit to sense
a signal based on potentials of the first and second dummy bit
lines.
12. The ferroelectric memory device according to claim 10, further
comprising a third dummy bit line arranged between the stitch
portion and the first dummy bit line and separated from the first
dummy bit line with an interval which is the same as the pitch
between the bit lines in the memory cell array and having the same
width as the bit line, a third dummy memory cell electrically
connected to the third dummy bit line and having the same structure
as the memory cell, a fourth dummy bit line arranged between the
stitch portion and the second dummy bit line and separated from the
second dummy bit line with an interval which is the same as the
pitch between the bit lines in the memory cell array and having the
same width as the bit line, and a fourth dummy memory cell
electrically connected to the fourth dummy bit line and having the
same structure as the memory cell.
13. The ferroelectric memory device according to claim 12, wherein
data, which is data complementary to data transferred to the first
dummy memory cell, is transferred to the third dummy memory cell
and data, which is data complementary to data transferred to the
second dummy memory cell, is transferred to the fourth dummy memory
cell and the device further comprises a first sense amplifier
circuit to sense a signal based on potentials of the first and
third dummy bit lines and a second sense amplifier circuit to sense
a signal based on potentials of the second and fourth dummy bit
lines.
14. A ferroelectric memory device comprising: a memory cell array
having memory cells arranged in a matrix form, each memory cell
including a cell transistor and a ferroelectric capacitor, one of
source and drain regions of the cell transistor being electrically
connected to a corresponding one of bit lines, a gate of the cell
transistor being electrically connected to a corresponding one of
word lines, the other one of the source and drain regions of the
cell transistor being electrically connected to one electrode of
the ferroelectric capacitor, the other electrode of the
ferroelectric capacitor being electrically connected to a
corresponding one of plate lines; a dummy bit line arranged outside
a bit line arranged on an end portion of the memory cell array; a
capacitor having one electrode electrically connected to the dummy
bit line; and a dummy bit line driving circuit having an output
terminal electrically connected to the other electrode of the
capacitor and input terminals electrically connected to the plate
lines, respectively, and detecting drive of the plate lines.
15. A ferroelectric memory device comprising: a memory cell array
having a plurality of memory cells arranged in a matrix form, each
of the memory cells including a cell transistor and a ferroelectric
capacitor, one of source and drain regions of the cell transistor
being electrically connected to a corresponding one of a plurality
of bit lines, a gate of the cell transistor being electrically
connected to a corresponding one of a plurality of word lines, the
other one of the source and drain regions of the cell transistor
being electrically connected to one electrode of the ferroelectric
capacitor, the other electrode of the ferroelectric capacitor being
electrically connected to a corresponding one of a plurality of
plate lines; and a dummy memory cell which includes a cell
transistor and a ferroelectric capacitor and is not electrically
connected to the plurality of bit lines.
16. A ferroelectric memory device comprising: a memory cell array
having memory cell blocks arranged in a matrix form, each memory
cell block being configured by electrically connecting a plurality
of memory cells between first and second terminals in series,
electrically connecting the first terminal to a bit line via a
block selection transistor and electrically connecting the second
terminal to a plate line, and the memory cell being configured by
electrically connecting source and drain regions of a cell
transistor to electrodes of a ferroelectric capacitor; a dummy bit
line arranged outside a bit line arranged on an end portion of the
memory cell array and separated from the bit line arranged on the
end portion of the memory cell array with an interval which is the
same as a pitch between the bit lines in the memory cell array and
having the same width as the bit line; and a dummy memory cell
block electrically connected to the first dummy bit line and having
the same structure as the memory cell block.
17. The ferroelectric memory device according to claim 16, further
comprising a second dummy bit line arranged further outside the
first dummy bit line and fixed at a predetermined potential.
18. The ferroelectric memory device according to claim 16, further
comprising a second dummy bit line arranged further outside-the
first dummy bit line and separated from the first dummy bit line
with an interval which is the same as the pitch between the bit
lines in the memory cell array and having the same width as the bit
line, and a second dummy memory cell block electrically connected
to the second dummy bit line and having the same structure as the
memory cell block to which data complementary to data of the first
dummy memory cell block is transferred.
19. The ferroelectric memory device according to claim 18, further
comprising a sense amplifier circuit which is electrically
connected to the first and second dummy bit lines and senses a
signal based on potentials of the first and second dummy bit
lines.
20. The ferroelectric memory device according to claim 19, further
comprising a third dummy bit line arranged further outside the
second dummy bit line and fixed at a predetermined potential.
21. A ferroelectric memory device comprising: a first memory cell
array having memory cell blocks arranged in a matrix form, each
memory cell block being configured by electrically connecting a
plurality of memory cells between first and second terminals in
series, electrically connecting the first terminal to a bit line
via a block selection transistor and electrically connecting the
second terminal to a plate line, and the memory cell being
configured by electrically connecting source and drain regions of a
cell transistor to electrodes of a ferroelectric capacitor; a
second memory cell array arranged adjacent to the first memory cell
array to commonly use the bit lines electrically connected to the
first memory cell array and having the same structure as the first
memory cell array; a first dummy bit line arranged outside a bit
line arranged on an end portion of the first memory cell array and
separated from the bit line arranged on the end portion of the
first memory cell array with an interval which is the same as a
pitch between the bit lines in the first memory cell array and
having the same width as the bit line; a first dummy memory cell
block electrically connected to the first dummy bit line and having
the same structure as the memory cell block; a second dummy bit
line arranged outside a bit line arranged on an end portion of the
second memory cell array and separated from the bit line arranged
on the end portion of the second memory cell array with an interval
which is the same as a pitch between the bit lines in the second
memory cell array and having the same width as the bit line; and a
second dummy memory cell block electrically connected to the second
dummy bit line and having the same structure as the memory cell
block.
22. The ferroelectric memory device according to claim 21, further
comprising a sense amplifier circuit which is electrically
connected to the first and second dummy bit lines and senses a
signal based on potentials of the first and second dummy bit
lines.
23. The ferroelectric memory device according to claim 22, wherein
the pair of dummy bit lines which includes the first and second
dummy bit lines has open bit-line architecture in which the first
dummy memory cell block is connected to the word line in the first
memory cell array and the second dummy memory cell block is
connected to the word line in the second memory cell array.
24. The ferroelectric memory device according to claim 22, further
comprising a third dummy bit line arranged further outside the
first and second dummy bit lines and fixed at a predetermined
potential.
25. A ferroelectric memory device comprising: a memory cell array
having memory cell blocks arranged in a matrix form, each memory
cell block being configured by electrically connecting a plurality
of memory cells between first and second terminals in series,
electrically connecting the first terminal to a bit line via a
block selection transistor and electrically connecting the second
terminal to a plate line, and the memory cell being configured by
electrically connecting source and drain regions of a cell
transistor to electrodes of a ferroelectric capacitor; an auxiliary
word line arranged in parallel to the word line above the memory
cell array; a stitch portion arranged in the memory cell array and
electrically connected to the word line and auxiliary word line; a
first dummy bit line arranged between the stitch portion and one of
the two bit lines disposed on both sides of the stitch portion and
separated from the bit line among the two bit lines with an
interval which is the same as a pitch between the bit lines in the
memory cell array and having the same width as the bit line; a
first dummy memory cell block electrically connected to the first
dummy bit line and having the same structure as the memory cell
block; a second dummy bit line arranged between the stitch portion
and the other one of the two bit lines disposed on both sides of
the stitch portion and separated from the other bit line among the
two bit lines with an interval which is the same as the pitch
between the bit lines in the memory cell array and having the same
width as the bit line; and a second dummy memory cell block
electrically connected to the second dummy bit line and having the
same structure as the memory cell block.
26. The ferroelectric memory device according to claim 25, wherein
data, which is data complementary to data transferred to the first
dummy memory cell block, is transferred to the second dummy memory
cell block and the device further comprises a sense amplifier
circuit to sense a signal based on potentials of the first and
second dummy bit lines.
27. The ferroelectric memory device according to claim 25, further
comprising a third dummy bit line arranged between the stitch
portion and the first dummy bit line and separated from the first
dummy bit line with an interval which is the same as the pitch
between the bit lines in the memory cell array and having the same
width as the bit line, a third dummy memory cell block electrically
connected to the third dummy bit line and having the same structure
as the memory cell block, a fourth dummy bit line arranged between
the stitch portion and the second dummy bit line and separated from
the second dummy bit line with an interval which is the same as the
pitch between the bit lines in the memory cell array and having the
same width as the bit line, and a fourth dummy memory cell block
electrically connected to the fourth dummy bit line and having the
same structure as the memory cell block.
28. The ferroelectric memory device according to claim 27, wherein
data, which is data complementary to data transferred to the first
dummy memory cell block, is transferred to the third dummy memory
cell block and data, which is data complementary to data
transferred to the second dummy memory cell block, is transferred
to the fourth dummy memory cell block and the device further
comprises a first sense amplifier circuit to sense a signal based
on potentials of the first and third dummy bit lines and a second
sense amplifier circuit to sense a signal based on potentials of
the second and fourth dummy bit lines.
29. A ferroelectric memory device comprising: a memory cell array
having memory cell blocks arranged in a matrix form, each memory
cell block being configured by electrically connecting a plurality
of memory cells between first and second terminals in series,
electrically connecting the first terminal to a bit line via a
block selection transistor and electrically connecting the second
terminal to a plate line, and the memory cell being configured by
electrically connecting source and drain regions of a cell
transistor to electrodes of a ferroelectric capacitor; a dummy bit
line arranged outside a bit line arranged on an end portion of the
memory cell array; a capacitor having one electrode electrically
connected to the dummy bit line; and a dummy bit line driving
circuit having an output terminal electrically connected to the
other electrode of the capacitor and input terminals electrically
connected to the plate lines, respectively, and detecting drive of
the plate lines.
30. A ferroelectric memory device comprising: a memory cell array
having memory cell blocks arranged in a matrix form, each memory
cell block being configured by electrically connecting a plurality
of memory cells between first and second terminals in series,
electrically connecting the first terminal to a bit line via a
block selection transistor and electrically connecting the second
terminal to a plate line, and the memory cell being configured by
electrically connecting source and drain regions of a cell
transistor to electrodes of a ferroelectric capacitor; and a dummy
memory cell block which has the same structure as the memory cell
block and is not electrically connected to the bit line.
31. The ferroelectric memory device according to claim 1, wherein
the first dummy bit line compensates for imbalance of noise caused
by parasitic capacitance, with respect to the bit line arranged on
the end portion of the memory cell array.
32. The ferroelectric memory device according to claim 6, wherein
the first dummy bit line is separated from the first bit line
arranged on the end portion of the first memory cell array with a
first interval which is the same as a pitch between the first bit
lines, and the second dummy bit line is separated from the second
bit line arranged on the end portion of the second memory cell
array with a second interval which is the same as a pitch between
the second bit lines.
33. The ferroelectric memory device according to claim 6, wherein
the first dummy bit line has the same width as the first bit line,
and the second dummy bit line has the same width as the second bit
line.
34. The ferroelectric memory device according to claim 6, further
comprising a plurality of sense amplifier circuits shared by the
first memory cell array and the second memory cell array.
35. The ferroelectric memory device according to claim 34, wherein
the plurality of first bit lines are formed of a plurality of pairs
of first bit lines, the plurality of second bit lines are formed of
a plurality of pairs of second bit lines, and each of the sense
amplifier circuits detects a signal from a corresponding one of the
pairs of first bit lines, and detects a signal from a corresponding
one of the pairs of second bit lines.
36. The ferroelectric memory device according to claim 7, wherein
data complementary to data of the first dummy memory cell is
transferred to the second dummy memory cell.
37. The ferroelectric memory device according to claim 6, wherein
the first and second dummy bit lines are not connected to data
lines which transmit data, respectively.
38. The ferroelectric memory device according to claim 6, wherein
the first dummy bit line compensates for imbalance of noise caused
by parasitic capacitance, with respect to the first bit line
arranged on the end portion of the first memory cell array, and the
second dummy bit line compensates for imbalance of noise caused by
parasitic capacitance, with respect to the second bit line arranged
on the end portion of the second memory cell array.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to a ferroelectric memory device
which stores data in a nonvolatile fashion by use of a
ferroelectric capacitor.
[0003] 2. Description of the Related Art
[0004] A ferroelectric memory device stores binary data in a
nonvolatile fashion according to the intensity of residual
dielectric polarization of a ferroelectric capacitor. A memory cell
of a conventional ferro-electric memory device is configured by
connecting the ferroelectric capacitor and a transistor in series
as in the case of a DRAM, for example. However, unlike the DRAM,
since data is held depending on the intensity of residual
dielectric polarization in the ferro-electric memory device, it is
necessary to drive a plate line in order to read out signal charges
onto a bit line. Therefore, in the conventional ferroelectric
memory device, a plate line driving circuit is required to have a
large area.
[0005] In order to cope with the above problem, a cell array system
of the ferroelectric memory device which can reduce the area of the
plate line driving circuit has been proposed by Takashima et al.
(D. Takashima et al., "High-density chain ferroelectric random
memory (CFRAM)" in Proc. VSLI Symp., June 1997, pp. 83-84). In the
above cell array system, a memory cell is configured by
respectively connecting two ends of the ferroelectric capacitor to
the source and drain of a cell transistor, and a plurality of
memory cells with the same configuration as described above are
serially connected to configure a memory cell block. In the series
connected TC unit type ferroelectric RAM, since the plate line
driving circuit can be commonly used by eight memory cells, for
example, the memory cell array can be integrated with a high
integration density.
[0006] In the series connected TC unit type ferroelectric RAM with
the above configuration, it is a common practice to arrange a dummy
bit line outside the memory cell array and use the dummy bit line
as a shield line by fixing the dummy bit line at ground potential,
for example, so as to prevent occurrence of noise from the exterior
of the memory cell array.
[0007] Further, a ferroelectric memory device in which a dummy bit
line is arranged on the exterior of the memory cell array to
compensate for capacitive coupling of the bit line on the end
portion of the memory cell array has been proposed (Jpn. Pat.
Appln. KOKAI Publication 10-200061).
[0008] It is known that the influence of noise (hereinafter
referred to as coupling noise) caused by parasitic capacitance
between wirings occurs when data which is read out onto the bit
line arranged in the memory cell array is sensed. When two bit
lines are arranged on both sides of a bit line with the same pitch
and if the amount of coupling noise given to the bit line from one
of the two bit lines is .delta., the amount of coupling noise
2.delta. occurs by taking the coupling noise .delta. given from the
other bit line into consideration.
[0009] However, in the case of the bit line arranged on the end
portion of the memory cell array, no coupling noise is given to the
bit line from the dummy bit line fixed at the ground potential.
Therefore, only the coupling noise .delta. from one bit line is
given to the bit line arranged on the end portion of the memory
cell array. For example, when data is sensed in a two
transistor-two capacitor (2T2C) system and if "1" is read out onto
the bit line arranged on the end portion of the memory cell array
and "0" is read out onto the adjacent bit line, the difference
between the readout potentials is reduced by .delta. and, as a
result, the sense margin is reduced by .delta..
[0010] Thus, there occurs a problem that the sense margin is
reduced due to an imbalance of coupling noise between the bit lines
arranged on the end portion of the memory cell array, the retention
characteristic is degraded and the yield rate is lowered.
BRIEF SUMMARY OF THE INVENTION
[0011] A ferroelectric memory device according to an aspect of the
present invention includes a memory cell array having memory cells
arranged in a matrix form. Each of the memory cells includes a cell
transistor and a ferroelectric capacitor, one of source and drain
regions of the cell transistor being electrically connected to a
corresponding one of bit lines, a gate of the cell transistor being
electrically connected to a corresponding one of word lines, the
other one of the source and drain regions of the cell transistor
being electrically connected to one electrode of the ferroelectric
capacitor, the other electrode of the ferroelectric capacitor being
electrically connected to a corresponding one of plate lines. It
further includes a first dummy bit line arranged outside a bit line
arranged on an end portion of the memory cell array and separated
from the bit line arranged on the end portion of the memory cell
array with an interval which is the same as a pitch between the bit
lines in the memory cell array and having the same width as the bit
line, and a first dummy memory cell electrically connected to the
first dummy bit line and having the same structure as the memory
cell.
[0012] A ferroelectric memory device according to another aspect of
the present invention includes a first memory cell array having
memory cells arranged in a matrix form. Each of memory cells
includes a cell transistor and a ferroelectric capacitor, one of
source and drain regions of the cell transistor being electrically
connected to a corresponding one of bit lines, a gate of the cell
transistor being electrically connected to a corresponding one of
word lines, the other one of the source and drain regions of the
cell transistor being electrically connected to one electrode of
the ferroelectric capacitor, the other electrode of the
ferroelectric capacitor being electrically connected to a
corresponding one of plate lines. It includes a second memory cell
array arranged adjacent to the first memory cell array to commonly
use the bit lines electrically connected to the first memory cell
array and having the same structure as the first memory cell array.
Further, it includes a first dummy bit line arranged outside a bit
line arranged on an end portion of the first memory cell array and
separated from the bit line arranged on the end portion of the
first memory cell array with an interval which is the same as the
pitch between the bit lines in the first memory cell array and
having the same width as the bit line, a first dummy memory cell
electrically connected to the first dummy bit line and having the
same structure as the memory cell. It includes a second dummy bit
line arranged outside a bit line arranged on an end portion of the
second memory cell array and separated from the bit line arranged
on the end portion of the second memory cell array with an interval
which is the same as the pitch between the bit lines in the second
memory cell array and having the same width as the bit line, and a
second dummy memory cell electrically connected to the second dummy
bit line and having the same structure as the memory cell.
[0013] A ferroelectric memory device according to still another
aspect of the present invention includes a memory cell array having
memory cells arranged in a matrix form. Each of the memory cells
includes a cell transistor and a ferroelectric capacitor, one of
source and drain regions of the cell transistor being electrically
connected to a corresponding one of bit lines, a gate of the cell
transistor being electrically connected to a corresponding one of
word lines, the other one of the source and drain regions of the
cell transistor being electrically connected to one electrode of
the ferroelectric capacitor, the other electrode of the
ferroelectric capacitor being electrically connected to a
corresponding one of plate lines. Further, it includes a dummy bit
line arranged outside a bit line arranged on an end portion of the
memory cell array, a capacitor having one electrode electrically
connected to the dummy bit line, and a dummy bit line driving
circuit having an output terminal electrically connected to the
other electrode of the capacitor and input terminals electrically
connected to the plate lines, respectively, and detecting drive of
the plate lines.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0014] FIG. 1 is a circuit diagram showing a memory cell block MCB
which configure a series connected TC unit type ferroelectric RAM
according to a first embodiment of this invention;
[0015] FIG. 2 is an operation timing diagram in the 2T2C system of
the memory cell block MCB shown in FIG. 1;
[0016] FIG. 3 is an operation timing diagram in the 1T1C system of
the memory cell block MCB shown in FIG. 1;
[0017] FIG. 4 is a schematic circuit diagram showing the
configuration of the main portion of the series connected TC unit
type ferroelectric RAM according to the first embodiment of this
invention;
[0018] FIG. 5 is a diagram showing one example of parasitic
capacitances Cbb between the respective bit lines in the 2T2C
system of the series connected TC unit type ferroelectric RAM shown
in FIG. 4 and coupling noise .delta. caused by the parasitic
capacitance Cbb;
[0019] FIG. 6 is a diagram showing one example of parasitic
capacitances Cbb between the respective bit lines in the 1T1C
system of the series connected TC unit type ferroelectric RAM shown
in FIG. 4 and coupling noise .delta. caused by the parasitic
capacitance Cbb;
[0020] FIG. 7 is a diagram showing the other example of parasitic
capacitances Cbb between the respective bit lines in the 1T1C
system of the series connected TC unit type ferroelectric RAM shown
in FIG. 4 and coupling noise .delta. caused by the parasitic
capacitance Cbb;
[0021] FIG. 8 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a second embodiment of this
invention;
[0022] FIG. 9 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a third embodiment of this
invention;
[0023] FIG. 10 is a schematic circuit diagram showing a
modification of the series connected TC unit type ferroelectric RAM
shown in FIG. 9;
[0024] FIG. 11 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a fourth embodiment of this
invention;
[0025] FIG. 12 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a fifth embodiment of this
invention;
[0026] FIG. 13 is a plan view showing the main portion of a series
connected TC unit type ferroelectric RAM according to a sixth
embodiment of this invention;
[0027] FIG. 14 is a cross sectional view taken along the 14-14'
line of FIG. 13;
[0028] FIG. 15 is a schematic circuit diagram showing the
configuration of the main portion of the series connected TC unit
type ferroelectric RAM shown in FIG. 13;
[0029] FIG. 16 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a seventh embodiment of this
invention; and
[0030] FIG. 17 is a diagram showing the main portion of another
example of a ferroelectric memory device.
DETAILED DESCRIPTION OF THE INVENTION
[0031] There will now be described embodiments of this invention
with reference to the accompanying drawings. In the following
explanation, constituents having the same function and
configuration are denoted by the same reference symbols and the
repetitive explanation is made only when necessary.
[0032] (First Embodiment)
[0033] FIG. 1 is a circuit diagram showing memory cell blocks MCB
which configure a series connected TC unit type ferroelectric RAM
according to a first embodiment of this invention.
[0034] A memory cell MC is configured by connecting a ferroelectric
capacitor C and a cell transistor T in parallel. The memory cell
block MCB is configured by electrically connecting, for example,
eight memory cells with the same structure as the memory cell MC in
series. In FIG. 1, two memory blocks MCB0, MCB1 which are
electrically connected to a pair of bit lines BL, /BL,
respectively, are shown. The phrase "electrically connected to" is
replaced hereinafter by "connected to".
[0035] One-side ends of the memory blocks MCB0, MCB1 are
respectively connected to the bit lines BL, /BL via block selection
transistors BST0, BST1. The other ends of the memory blocks MCB0,
MCB1 are respectively connected to plate lines PL, /PL. The gate of
the cell transistor T of each memory cell block MCB is connected to
a corresponding one of word lines WL0 to WL7. The gates of the
block selection transistors BST0, BST1 are respectively connected
to block selection signal lines BSL0, BSL1.
[0036] Two systems, that is, a 2T2C system of holding one-bit data
by use of two cell transistors and two ferroelectric capacitors and
a 1T1C system of holding one-bit data by use of one cell transistor
and one ferroelectric capacitor are provided as a data holding
system of the ferroelectric memory device. The series connected TC
unit type ferroelectric RAM shown in FIG. 1 has a configuration to
which both of the 2T2C system and 1T1C system can be commonly
applied.
[0037] In the 1T1C system, a reference voltage generating circuit
RVG which generates reference voltage includes dummy word
transistors DWT1, DWT2 and a reference capacitor RC. One of the
electrodes of the reference capacitor RC is connected to a dummy
plate line DPL. The other electrode of the reference capacitor RC
is connected to sources/drains of the dummy word transistors DWT1,
DWT2. The drain/source of the dummy word transistor DWT1 is
connected to the bit line /BL. The drain/source of the dummy word
transistor DWT2 is connected to the bit line BL. The gate of the
dummy word transistor DWT1 is connected to a dummy word line DWL1.
The gate of the dummy word transistor DWT2 is connected to a dummy
word line DWL2.
[0038] The bit lines BL, /BL are connected to a sense amplifier
circuit SA which senses and amplifies readout data.
[0039] FIG. 2 is an operation timing diagram in the 2T2C system of
the memory cell block MCB with the above configuration. It is
assumed that the memory cell MC stores a state in which the
residual dielectric polarization of the ferroelectric capacitor C
is positive as data "1" and stores a state in which the residual
dielectric polarization thereof is negative as data "0". At the
standby time, all of the word lines WL are kept at "H", the block
selection signal lines BSL0, BSL1 are kept at "L" and the bit lines
BL, /BL and plate lines PL, /PL are kept at VSS (ground potential).
At this time, two terminals of the ferroelectric capacitor C are
short-circuited by the cell transistor which is set in the ON state
so as to stably hold data.
[0040] At the active time, for example, when the memory cell MC on
the bit line BL side is selected by use of the word line WL2, the
bit line BL is set into an electrically floating state, the word
line WL2 is set to "L", then the block selection signal line BSL0
is set to "H" and the plate line PL is raised from VSS (ground
potential) to VAA (positive potential). As a result, voltage is
applied to the ferroelectric capacitor C of the selected memory
cell MC and signal voltage is read out onto the bit line BL
according to the data "0", "1". In this case, data which is
complementary to data stored in the memory cell MC on the bit line
BL side is stored in the memory cell MC on the bit line /BL side
selected by the word line WL2. Therefore, signal voltage is read
out onto the bit line /BL according to the data "0", "1" in the
same manner as described above by setting the block selection
signal line BSL1 to "H".
[0041] The signal voltages read out onto the bit lines BL, /BL are
compared with each other and the compared data is amplified by the
sense amplifier circuit SA which is activated and the data "0", "1"
is sensed. After this, the sense amplifier circuit SA is
deactivated and the readout data is rewritten.
[0042] In the readout and rewriting operations, the destructive
readout operation is performed in the case of "1" data and the
nondestructive readout operation is performed in the case of "0"
data. That is, in the case of "1" data, the amount of residual
dielectric polarization of the ferroelectric capacitor is greatly
reduced by application of positive voltage from the plate line and
inversion of polarization occurs. Then, if the plate line voltage
is lowered after the readout operation, a voltage opposite to that
at the readout time is applied to the ferroelectric capacitor to
rewrite the data since the bit line is set at high potential by the
readout data. In the case of "0" data, inversion of polarization
due to the plate line voltage does not occur, the opposite voltage
is not applied after the readout operation and data of the original
negative residual dielectric polarization state is rewritten.
[0043] FIG. 3 is an operation timing diagram in the 1T1C system of
the memory cell block MCB shown in FIG. 1.
[0044] At the active time, for example, when the memory cell MC on
the bit line BL side is selected by use of the word line WL2, the
bit line BL is set into an electrically floating state, the word
line WL2 is set to "L", then the block selection signal line BSL0
is set to "H" and the plate line PL is raised from VSS (ground
potential) to VAA (positive potential). Further, the dummy word
line DWL1 is set to "H" and reference voltage is applied to the bit
line /BL.
[0045] The signal voltage read out onto the bit line BL is compared
with the reference voltage and the compared data is amplified by
the sense amplifier circuit SA which is activated and data "0", "1"
is sensed.
[0046] FIG. 4 is a schematic circuit diagram showing the
configuration of the main portion of the series connected TC unit
type ferroelectric RAM according to the first embodiment of this
invention.
[0047] A plurality of memory cell blocks which have the same
configuration as the memory cell blocks MCB0, MCB1 shown in FIG. 1
are arranged to configure a memory cell array MCA.
[0048] Bit lines BL0, /BL0 are connected to data lines DQ0, /DQ0
via data selection transistors DST0, DST1. The gates of the data
selection transistors DST0, DST1 are connected to a column decoder
CD (not shown) and a column selection signal is applied thereto via
a column selection signal line CSL0 to output data via the data
lines DQ0, /DQ0.
[0049] Dummy bit lines DummyBL and Dummy/BL are respec-tively
arranged outside the memory cell array MCA and separated from the
bit line BL0 which is arranged on the end portion of the memory
cell array MCA with an interval which is the same as the pitch
between the paired bit lines in the memory cell array MCA. The
Dummy bit lines DummyBL and Dummy/BL respectively have the same
width as the bit line in the memory cell array MCA. Memory cell
blocks MCB are connected to the respective dummy bit lines DummyBL,
Dummy/BL and a reference voltage generating circuit RVG and sense
amplifier circuit SA are connected. Further, data lines and a
column gate are not connected to the dummy bit lines DummyBL,
Dummy/BL.
[0050] The operation of the 2T2C system of the series connected TC
unit type ferroelectric RAM with the above configuration is
explained below. FIG. 5 is a diagram showing parasitic capacitances
Cbb between the respective bit lines and coupling noise .delta.
caused by the parasitic capacitance Cbb.
[0051] In order to read out data stored in the memory cell MC
connected to the word line WLn, potential VAA (positive potential)
is applied to the plate lines PL, /PL. For example, it is assumed
that data "1" is read out onto the dummy bit line DummyBL and bit
lines BL0, BL1. In the case of the 2T2C system, data "0" is read
out onto the dummy bit line Dummy/BL and bit lines /BL0, /BL1.
[0052] If VAA (positive potential) is applied to the plate lines
PL, /PL and data is read out onto the respective bit lines,
coupling noises .delta. are instantaneously caused on the
respective bit lines by the presence of the parasitic capacitances
Cbb between the respective bit lines. The bit line /BL0 receives
the coupling noise of 2.delta. from the adjacent bit lines BL0 and
BL1. Further, since the dummy bit lines DummyBL, Dummy/BL are
provided, the bit line BL0 disposed on the end portion of the
memory cell array MCA also receives the coupling noise of 2.delta.
from the adjacent dummy bit line Dummy/BL and bit line /BL0.
[0053] As a result, when data read out from the paired bit lines
BL0, /BL0 is sensed by the sense amplifier circuit SA, readout
potentials of "1" data of the bit line BL0 and "0" data of the bit
line /BL0 are both increased by 2.delta.. Therefore, as in the case
of the bit lines in the memory cell array MCA, an imbalance in the
coupling noise will not occur on the bit line BL0.
[0054] FIG. 6 is a diagram showing one example of parasitic
capacitances Cbb between the respective bit lines in the 1T1C
system and coupling noise .delta. caused by the parasitic
capacitance Cbb.
[0055] For example, assume that data "1" is read out onto the dummy
bit line DummyBL and bit lines BL0, BL1. In the case of the 1T1C
system, the reference voltage RV is applied to the dummy bit line
Dummy/BL and bit lines /BL0, /BL1. If VAA (positive potential) is
applied to the plate lines PL, /PL, coupling noises 5 are
instantaneously caused on the respective bit lines by the presence
of the parasitic capacitances Cbb between the respective bit lines.
Therefore, as in the case of the 2T2C system, the bit line BL0
disposed on the end portion of the memory cell array MCA receives
the coupling noise of 2.delta. from the adjacent dummy bit line
Dummy/BL and bit line /BL0.
[0056] Next, in the 1T1C system, for example, assume that data "0"
is read out onto the dummy bit line Dummy/BL and bit lines /BL0,
/BL1. FIG. 7 is a diagram showing parasitic capacitances Cbb
between the respective bit lines in the above case and coupling
noise .delta. caused by the parasitic capacitance Cbb.
[0057] In the case of the 1T1C system, if "0" data is read out onto
the dummy bit line Dummy/BL and bit lines /BL0, /BL1, the reference
voltage RV is applied to the dummy bit line DummyBL and bit lines
BL0, BL1. If VAA (positive potential) is applied to the plate lines
PL, /PL, coupling noises .delta. are instantaneously caused on the
respective bit lines by the presence of the parasitic capacitances
Cbb between the respective bit lines. Therefore, as in the case of
the 2T2C system, the bit line BL0 disposed on the end portion of
the memory cell array MCA receives the coupling noise of 2.delta.
from the adjacent dummy bit line Dummy/BL and bit line /BL0.
[0058] As described above, in the present embodiment, the dummy bit
lines DummyBL and Dummy/BL are arranged outside and apart from the
bit line BL0 disposed on the end portion of the memory cell array
MCA with an interval which is the same as the pitch between the
paired bit lines in the memory cell array MCA. The Dummy bit lines
DummyBL and Dummy/BL respectively have the same width as the bit
line in the memory cell array MCA. Further, the sense amplifier
circuit SA is connected to the dummy bit lines DummyBL, Dummy/BL
and data lines are not connected to the dummy bit lines.
[0059] Therefore, according to the present embodiment, an imbalance
in the coupling noise occurring on the bit line disposed on the end
portion of the memory cell array MCA can be suppressed. As a
result, a reduction in the sense margin of the sense amplifier
circuit SA can be prevented and data can be correctly sensed.
[0060] Further, since the sense amplifier circuit SA is connected
to the dummy bit lines DummyBL, Dummy/BL, the same operation as
that of the bit lines in the memory cell array MCA can be attained.
Therefore, the same coupling noise as that occurring on the other
bit line in the memory cell array MCA can be caused on the bit line
BL0.
[0061] Further, since the data lines DQ are not connected to the
dummy bit lines DummyBL, Dummy/BL, an extra circuit can be omitted
and the circuit space can be reduced.
[0062] (Second Embodiment)
[0063] In a second embodiment of this invention, paired dummy bit
lines are arranged outside the memory cell array MCA and a dummy
bit line connected to VSS (ground potential) is further arranged
outside the paired dummy bit lines.
[0064] FIG. 8 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to the second embodiment of this
invention. The configuration of the memory cell array MCA and
paired dummy bit lines DummyBL1, Dummy/BL1 is the same as that in
the first embodiment.
[0065] A dummy bit line Dummy/BL0 is disposed outside the dummy bit
line DummyBL1 and separated from the dummy bit line DummyBL1 with
an interval which is the same as the pitch between the paired bit
lines in the memory cell array MCA. The potential of the dummy bit
line Dummy/BL0 is fixed at VSS (ground potential).
[0066] As in the first embodiment, in the series connected TC unit
type ferroelectric RAM with the above configuration, an imbalance
in the coupling noise occurring on the bit line BL0 can be
eliminated. Further, in order to prevent noise from the exterior
from being applied to the memory cell array MCA and paired dummy
bit lines DummyBL1, Dummy/BL1, the dummy bit line Dummy/BL0 fixed
at VSS (ground potential) is provided.
[0067] Therefore, according to the present embodiment, an imbalance
in the coupling noise occurring on the bit line disposed on the end
portion of the memory cell array MCA can be eliminated. As a
result, a reduction in the sense margin of the sense amplifier
circuit SA can be prevented and data can be correctly sensed.
[0068] Further, the dummy bit line Dummy/BL0 functions as a shield
line and can prevent occurrence of noise from the exterior of the
memory cell array MCA.
[0069] Even if the interval between the dummy bit lines DummyBL1
and Dummy/BL0 is not the same as the pitch between the paired bit
lines in the memory cell array MCA, no particular problem
occurs.
[0070] (Third Embodiment)
[0071] FIG. 9 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to a third embodiment of this
invention. The configuration of a memory cell block MCB is the same
as that of the first embodiment.
[0072] A plurality of memory cell blocks MCB are arranged to
configure memory cell arrays MCA1, MCA2. The memory cell blocks MCB
in the memory cell arrays MCA1 and MCA2 are connected together by
use of a common bit line. A sense amplifier circuit SA is connected
between the respective common paired bit lines lying between the
memory cell arrays MCA1 and MCA2. A column decoder CD is connected
to each sense amplifier circuit SA.
[0073] A cell array selection transistor AST1 is inserted into that
portion of the bit line BL0 which lies between the memory cell
array MCA1 and the sense amplifier circuit SA. Further, a cell
array selection transistor AST2 is inserted into that portion of
the bit line BL0 which lies between the memory cell array MCA2 and
the sense amplifier circuit SA. The gate of the cell array
selection transistor AST1 is connected to a memory cell array
selection line ASL1. The gate of the cell array selection
transistor AST2 is connected to a memory cell array selection line
ASL2. Likewise, cell array selection transistors AST1, AST2 are
connected to the other bit lines. The memory cell arrays MCA1, MCA2
can be selected by use of memory cell array selection lines ASL1,
ASL2 and each sense amplifier circuit SA and each column decoder CD
can be commonly used.
[0074] A dummy bit line Dummy/BL is arranged outside the memory
cell array MCA1 and separated from the bit line BL0 disposed on the
end portion of the memory cell array MCA1 with an interval
corresponding to the pitch between the paired bit lines in the
memory cell array MCA1. The Dummy bit line Dummy/BL has the same
width as the bit line in the memory cell array MCA1. A memory cell
block MCB and a reference voltage generating circuit RVG1 are
connected to the dummy bit line Dummy/BL. The reference voltage
generating circuit RVG1 is configured by a dummy word transistor
DWTn and reference capacitor RCn. One of the electrodes of the
reference capacitor RCn is connected to a dummy plate line DPLn.
The other electrode of the reference capacitor RCn is connected to
the source/drain of the dummy word transistor DWTn. The
drain/source of the dummy word transistor DWTn is connected to the
dummy bit line Dummy/BL.
[0075] A dummy bit line DummyBL is arranged outside the memory cell
array MCA2 and separated from the bit line BL0 disposed on the end
portion of the memory cell array MCA2 with an interval
corresponding to the pitch between the paired bit lines in the
memory cell array MCA2. The Dummy bit line DummyBL has the same
width as the bit line in the memory cell array MCA2. A memory cell
block MCB and a reference voltage generating circuit RVG2 are
connected to the dummy bit line DummyBL. The reference voltage
generating circuit RVG2 is configured by a dummy word transistor
DWTm+1 and reference capacitor RCm. One of the electrodes of the
reference capacitor RCm is connected to a dummy plate line DPLm.
The other electrode of the reference capacitor RCm is connected to
the source/drain of the dummy word transistor DWTm+1. The
drain/source of the dummy word transistor DWTm+1 is connected to
the dummy bit line DummyBL.
[0076] The dummy bit lines DummyBL and Dummy/BL are connected to a
sense amplifier circuit SA. The memory cell block MCB which is
connected to the dummy bit line Dummy/BL is connected to the word
lines which are arranged for the memory cell array MCAl. The memory
cell block MCB which is connected to the dummy bit line DummyBL is
connected to the word lines which are arranged for the memory cell
array MCA2. Thus, architecture that the pair of dummy bit lines
DummyBL and Dummy/BL is connected to different word lines,
respectively, is referred to as open bit-line architecture.
[0077] In the series connected TC unit type ferroelectric RAM with
the above configuration, the bit line BL0 on the memory cell array
MCAl side receives coupling noise of 26 from the adjacent bit line
/BL0 and dummy bit line Dummy/BL.
[0078] Further, the bit line BL0 on the memory cell array MCA2 side
receives coupling noise of 26 from the adjacent bit line /BL0 and
dummy bit line DummyBL.
[0079] As described above, in the present embodiment, in the series
connected TC unit type ferroelectric RAM in which the bit lines and
sense amplifier circuits SA are commonly used, one of the two
memory cell arrays MCA1, MCA2 is selected and data is sensed, one
of the paired dummy bit lines DummyBL and Dummy/BL is arranged
outside the memory cell array MCA1 with an interval which is the
same as the pitch between the paired bit lines in the memory cell
array MCA1. The other dummy bit line is arranged outside the memory
cell array MCA2 with an interval which is the same as the pitch
between the paired bit lines in the memory cell array MCA2.
Further, the Dummy bit lines DummyBL and Dummy/BL respectively have
the same width as the bit line.
[0080] Therefore, according to the present embodiment, an imbalance
in the coupling noise occurring on the bit line disposed on the end
portion of each memory cell array MCA can be eliminated. As a
result, a reduction in the sense margin of the sense amplifier
circuit SA can be prevented and data can be correctly sensed.
[0081] Further, since the paired bit lines are formed of an open
form and arranged for each memory cell array MCA, an increase in
the chip area can be suppressed in comparison with the case wherein
the paired dummy bit lines are arranged for the respective memory
cell arrays MCA.
[0082] Further, a dummy bit line DummyBL0 whose potential is fixed
at VSS (ground potential) can be arranged outside the paired dummy
bit lines DummyBL, Dummy/BL. FIG. 10 is a schematic circuit diagram
showing the configuration of the main portion of the series
connected TC unit type ferroelectric RAM with the above
configuration.
[0083] The dummy bit line Dummy/BL0 is arranged outside the paired
dummy bit lines DummyBL, Dummy/BL with the same pitch as that
between the paired bit lines in the memory cell array MCA.
[0084] With the above configuration, noise from the exterior to the
memory cell array MCA and paired dummy bit lines DummyBL, Dummy/BL
can be prevented.
[0085] Even if the interval at which the dummy bit line Dummy/BL0
is arranged is not the same as the pitch between paired bit lines
in the memory cell array MCA, no particular problem occurs.
[0086] (Fourth Embodiment)
[0087] In a fourth embodiment of this invention, a dummy bit line
is arranged outside the memory cell array MCA and reference voltage
is applied to the dummy bit line.
[0088] FIG. 11 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to the fourth embodiment of this
invention. The configuration of the memory cell array MCA is the
same as that in the first embodiment.
[0089] A dummy bit line Dummy/BL is arranged outside the memory
cell array MCA and separated from a bit line BL0 disposed on the
end portion of the memory cell array MCA with an interval
corresponding to the pitch between the paired bit lines in the
memory cell array MCA. A memory cell block MCB is arranged with
respect to the dummy bit line Dummy/BL, but it is not connected to
the dummy bit line Dummy/BL and plate line PL.
[0090] One of the electrodes of a reference capacitor C1 is
connected to the dummy bit line Dummy/BL. The other electrode of
the reference capacitor C1 is connected to plate lines PL, /PL via
an OR circuit. For example, the capacitance of the capacitor C1 is
set so that an intermediate value of readout potentials of "1" data
and "0" data will be applied to the dummy bit line Dummy/BL.
[0091] In the series connected TC unit type ferroelectric RAM with
the above configuration, reference voltage is applied to the dummy
bit line Dummy/BL at the active time. Therefore, coupling noise
.delta. from the bit line /BL0 and coupling noise .delta. from the
dummy bit line Dummy/BL based on the reference voltage occur in the
bit line BL0.
[0092] Thus, according to the present embodiment, an imbalance in
the coupling noise occurring in the bit line arranged on the end
portion of the memory cell array MCA can be suppressed.
[0093] Further, since only one dummy bit line is used, the chip
area can be reduced in comparison with the case wherein the paired
dummy bit lines are arranged.
[0094] In the present embodiment, the OR circuit is used as an
example of a circuit which detects drive of the plate lines PL,
/PL. But this is not limitative. Any circuit will do as long as it
can detect drive of the plate lines PL, /PL.
[0095] (Fifth Embodiment)
[0096] In a fifth embodiment of this invention, a dummy memory cell
block DMCB is arranged outside a memory cell array MCA.
[0097] FIG. 12 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to the fifth embodiment of this
invention. The configuration of the memory cell array MCA is the
same as that of the first embodiment.
[0098] The dummy memory cell block DMCB is arranged out-side the
memory cell array MCA. A dummy bit line which is generally arranged
outside the memory cell array MCA and whose potential is fixed at
VSS is eliminated.
[0099] In the series connected TC unit type ferroelectric RAM with
the above configuration, the influence caused by the wiring
capacitance from the dummy bit line which is fixed at VSS and given
to the bit line BL0 is eliminated. As a result, the capacitance
associated with the bit line BL0 is made smaller in comparison with
capacitances associated with bit lines in the memory cell array
MCA.
[0100] Thus, according to the present embodiment, coupling noise
with respect to the bit line BL0 from the other bit lines in the
memory cell array MCA becomes larger. Therefore, an imbalance in
the coupling noise of the bit line BL0 can be suppressed.
[0101] (Sixth Embodiment)
[0102] FIG. 13 is a plan view showing the main portion of a series
connected TC unit type ferroelectric RAM according to a sixth
embodiment of this invention. FIG. 14 is a cross sectional view
taken along the 14-14' line of FIG. 13.
[0103] A stitch area is formed in an internal portion of a memory
cell array MCA (which is a portion between bit lines /BLn+1 and
BLn+2 in this embodiment). The stitch area is provided to suppress
the delay of signals of word lines WL and block selection line BSL.
Metal wirings (three-layered metal wirings M1, M2, M3 in this
embodiment) are arranged parallel to the word lines WL and block
selection line BSL. Further, the stitch area is provided to connect
the gate wirings GC to the metal wirings every predetermined memory
cell blocks MCB.
[0104] The configuration of the stitch area is explained by taking
a word line WL1 as an example. A gate wiring WL1(GC) is connected
to a first-layered metal wiring WL1(Ml) 2 via a plug 1. The metal
wiring WL1(M1) 2 is connected to a second-layered metal wiring
WL1(M2) 4 via a plug 3. The metal wiring WL1(M2) 4 is connected to
a third-layered metal wiring WL1(M3) via a plug 5.
[0105] FIG. 15 is a schematic circuit diagram showing the
configuration of the main portion of the series connected TC unit
type ferroelectric RAM shown in FIG. 13.
[0106] Dummy bit lines DummyBL, Dummy/BL are arranged on both sides
of the stitch area. The dummy bit lines DummyBL, Dummy/BL are
respectively separated from adjacent bit lines /BLn+1, BLn+2 with
an interval corresponding to the pitch between paired bit lines in
the memory cell array MCA. The Dummy bit lines DummyBL and Dummy/BL
respectively have the same width as the bit line in the memory cell
array MCA. Memory cell blocks MCB are respectively connected to the
dummy bit lines DummyBL, Dummy/BL and a reference voltage
generating circuit RVG and sense amplifier circuit SA are connected
therebetween. In this case, data lines and a column gate are not
connected to the dummy bit lines DummyBL, Dummy/BL.
[0107] In the series connected TC unit type ferroelectric RAM with
the above configuration, the pitch between the bit lines /BLn+1 and
BLn+1 is equal to the pitch between the bit line /BLn+1 and the
dummy bit line DummyBL. Therefore, the bit line /BLn+1 receives the
same coupling noise .delta. from the bit lines lying on both sides
thereof. This applies to the bit line BLn+2.
[0108] As described above, in the present embodiment, in order to
eliminate an imbalance in the coupling noise between the bit lines
caused by forming the stitch area in the memory cell array MCA, the
dummy bit lines DummyBL, Dummy/BL are arranged on both sides of the
stitch area. Further, the Dummy bit lines DummyBL and Dummy/BL
respectively have the same width as the bit line in the memory cell
array MCA.
[0109] Therefore, according to the present embodiment, the pitches
between each of the bit lines /BLn+1, BLn+2 and the bit lines
arranged on both sides of each of the bit lines /BLn+1, BLn+2 can
be made equal to each other and an imbalance in the coupling noise
occurring on the bit lines /BLn+1, BLn+2 can be suppressed. As a
result, a reduction in the sense margin of the sense amplifier
circuit SA can be prevented and data can be correctly sensed.
[0110] Further, since the sense amplifier circuit SA is connected
to the dummy bit lines DummyBL, Dummy/BL, the same operation as
that of the bit lines in the memory cell array MCA can be attained.
Therefore, the same coupling noise as that of the other bit lines
can be caused with respect to the bit line BL0.
[0111] Further, since the data lines DQ are not connected to the
dummy bit lines DummyBL, Dummy/BL, an extra circuit can be omitted
and the space of the circuit can be reduced.
[0112] (Seventh Embodiment)
[0113] In a seventh embodiment of this invention, dummy bit line
pairs are arranged on both sides of a stitch area formed in a
memory cell array MCA. Therefore, an imbalance in the coupling
noise occurring on a bit line according to provide the stitch area
is suppressed.
[0114] FIG. 16 is a schematic circuit diagram showing the
configuration of the main portion of a series connected TC unit
type ferroelectric RAM according to the seventh embodiment of this
invention. The configuration of the stitch area is the same as that
of the sixth embodiment.
[0115] The dummy bit line pairs are arranged on both sides of the
stitch area. The paired dummy bit lines DummyBLn, Dummy/BLn are
arranged between the stitch area and a bit line /BLn and intervals
between the bit line /BLn and the dummy bit line DummyBLn and
between the dummy bit lines DummyBLn and Dummy/BLn are set equal to
an interval which is the same as the pitch between the paired bit
lines in the memory cell array MCA. The Dummy bit lines DummyBLn
and Dummy/BLn respectively have the same width as the bit line in
the memory cell array MCA. Memory cell blocks MCB are respectively
connected to the dummy bit lines DummyBLn, Dummy/BLn and a
reference voltage generating circuit RVG and sense amplifier
circuit SA are connected therebetween. In this case, data lines and
a column gate are not connected to the dummy bit lines DummyBL,
Dummy/BL.
[0116] The dummy bit lines DummyBLn+1, Dummy/BLn+1 are arranged
between the stitch area and the bit line BLn+1. The other
configuration is the same as that of the dummy bit lines DummyBLn,
Dummy/BLn.
[0117] In the series connected TC unit type ferroelectric RAM with
the above configuration, the interval between the bit line /BLn and
the dummy bit line DummyBLn and the interval between the dummy bit
lines DummyBLn and Dummy/BLn are equal to the pitch between the
paired bit lines in the memory cell array MCA. Therefore, since the
wiring parasitic capacitance between the bit line /BLn and the
dummy bit line DummyBLn becomes equal to the wiring parasitic
capacitance between the paired dummy bit lines DummyBLn and
Dummy/BLn. AS a result, coupling noise with respect to the bit line
/BLn from the dummy bit line Dummy/BLn other bit lines is the same
as coupling noise between the paired dummy bit lines in the memory
cell array MCA.
[0118] Thus, according to the present embodiment, in addition to
the effect obtained in the seventh embodiment, an imbalance in the
coupling noise caused by the wiring parasitic capacitance between
the paired dummy bit lines DummyBLn and Dummy/BLn can be suppressed
with respect to the bit line /BLn. This applies to the bit line
BLn+1.
[0119] The series connected parallel-TC unit type ferroelectric
memories of the above embodiments are explained to have the common
configuration for the 2T2C system and 1T1C system, but it can be
formed with a configuration which can be applied only to one of the
2T2C system and 1T1C system.
[0120] Further, in the above embodiments, a case wherein the series
connected TC unit type ferroelectric RAM is used as an example of
the ferroelectric memory device is explained, but this is not
limitative. FIG. 17 is a diagram showing the main portion of
another example of the ferroelectric memory device.
[0121] The gate of a transistor T is connected to a word line WL.
The source or drain region of the transistor T is connected to a
bit line BL. The drain or source region of the transistor T is
connected to one of the electrodes of a ferroelectric capacitor C.
The other electrode of the ferroelectric capacitor C is connected
to a plate line to form a memory cell MC'. That is, the transistor
T and ferroelectric capacitor C are connected in series. A
plurality of memory cells having the same configuration as that of
the above memory cell are arranged to configure a memory cell
array. When applying a ferroelectric memory device with the above
configuration to the above embodiments, the same effect can be
attained.
[0122] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
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