U.S. patent application number 10/870216 was filed with the patent office on 2004-12-09 for low k film application for interlevel dielectric and method of cleaning etched features.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Chen, Gary, Yin, Zhiping.
Application Number | 20040245644 10/870216 |
Document ID | / |
Family ID | 25545512 |
Filed Date | 2004-12-09 |
United States Patent
Application |
20040245644 |
Kind Code |
A1 |
Yin, Zhiping ; et
al. |
December 9, 2004 |
Low K film application for interlevel dielectric and method of
cleaning etched features
Abstract
Methods of selectively removing post-etch polymer material and
dielectric antireflective coatings (DARC) without substantially
etching an underlying carbon-doped low k dielectric layer, and
compositions for the selective removal of a DARC layer and
post-etch polymer material are provided. A composition comprising
trimethylammonium fluoride is used to selectively etch a dielectric
antireflective coating layer overlying a low k dielectric layer at
an etch rate of the antireflective coating layer to the low k
dielectric layer that is greater than the etch rate of the
antireflective coating to a TEOS layer. The method and composition
are useful, for example, in the formation of high aspect ratio
openings in low k (carbon doped) silicon oxide dielectric layers
and maintaining the integrity of the dimensions of the formed
openings during a cleaning step to remove a post-etch polymer and
antireflective coating.
Inventors: |
Yin, Zhiping; (Boise,
ID) ; Chen, Gary; (Boise, ID) |
Correspondence
Address: |
WHYTE HIRSCHBOECK DUDEK S.C.
555 EAST WELLS STREET
SUITE 1900
MILWAUKEE
WI
53202
US
|
Assignee: |
Micron Technology, Inc.
Boise
ID
|
Family ID: |
25545512 |
Appl. No.: |
10/870216 |
Filed: |
June 17, 2004 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10870216 |
Jun 17, 2004 |
|
|
|
10423210 |
Apr 25, 2003 |
|
|
|
10423210 |
Apr 25, 2003 |
|
|
|
09998729 |
Nov 30, 2001 |
|
|
|
6573175 |
|
|
|
|
Current U.S.
Class: |
257/758 ;
257/759; 257/760; 257/E21.029; 257/E21.251; 257/E21.252;
257/E21.277; 257/E21.579 |
Current CPC
Class: |
H01L 21/0276 20130101;
H01L 21/31633 20130101; H01L 21/31111 20130101; H01L 21/76814
20130101; H01L 21/31116 20130101; H01L 21/76802 20130101; H01L
21/76807 20130101; H01L 21/02063 20130101 |
Class at
Publication: |
257/758 ;
257/759; 257/760 |
International
Class: |
H01L 023/48; H01L
023/52; H01L 029/40 |
Claims
1-112. (canceled)
113. A semiconductor device, comprising: a contact opening in an
insulative layer, wherein the contact opening has been cleaned with
a solution comprising trimethylammonium fluoride to selectively
remove dielectric antireflective coating material from the contact
opening and the insulative layer adjacent the contact opening.
114. The semiconductor device of claim 113, wherein the contact
opening comprises a via and a trench.
115. A semiconductor device, comprising: a contact opening in an
insulative layer, wherein the contact opening has been cleaned with
a solution comprising trimethylammonium fluoride to selectively
remove dielectric antireflective coating material from the contact
opening and the insulative layer adjacent the contact opening; and
a conductive material within the contact opening.
116. A semiconductor device, comprising: a substrate comprising an
active area; a contact opening in an insulative layer over the
substrate to the active area, wherein the contact opening has been
cleaned with a solution comprising trimethylammonium fluoride to
selectively remove dielectric antireflective coating material from
the contact opening and the insulative layer adjacent the contact
opening; and a conductive plug within the contact opening in
contact with the active area.
117. A semiconductor device, comprising: a via plug in a contact
opening in an insulative layer, wherein the contact opening has
been cleaned with a solution comprising trimethylammonium fluoride
to selectively remove dielectric antireflective coating material
from the contact opening.
118. A semiconductor device, comprising: a trench in an insulative
layer, wherein the trench has been cleaned with a solution
comprising trimethylammonium fluoride to selectively remove
dielectric antireflective coating material from the trench.
119. A semiconductor device, comprising: an interconnect within a
contact opening in an insulative layer, wherein the contact opening
has been cleaned with a solution comprising trimethylammonium
fluoride to selectively remove dielectric antireflective coating
material from the contact opening.
120. A semiconductor device, comprising: a contact opening
comprising a via and a trench in an insulative layer, wherein the
contact opening has been cleaned with a solution comprising
trimethylammonium fluoride to selectively remove dielectric
antireflective coating material from the contact opening.
121. A semiconductor device, comprising: a via plug and an
interconnect in a contact opening in an insulative layer, wherein
the contact opening has been cleaned with a solution comprising
trimethylammonium fluoride to selectively remove dielectric
antireflective coating material from the contact opening.
122. A semiconductor structure, comprising: a contact opening
etched in an insulative layer and cleaned with a solution
comprising trimethylammonium fluoride to selectively remove
dielectric antireflective coating material and polymer material
from the contact opening and the insulative layer adjacent the
contact opening.
123. A semiconductor structure, comprising: a contact opening
etched in an interlevel dielectric layer and cleaned with a
solution comprising trimethylammonium fluoride to selectively
remove dielectric antireflective coating material and polymer
material from the contact opening and the interlevel dielectric
layer adjacent the contact opening.
124. A semiconductor device, comprising: a dual damascene opening
in an insulative layer, wherein the opening has been cleaned with a
solution comprising trimethylammonium fluoride to selectively
remove dielectric antireflective coating material from the
opening.
125. A semiconductor device, comprising: a dual inlaid opening in
an insulative layer, wherein the opening has been cleaned with a
solution comprising trimethylammonium fluoride to selectively
remove dielectric antireflective coating material from the
opening.
126. The device of claim 125, wherein the opening comprises a via
and a trench.
127. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising an organic fluoride cleaning agent comprising
nitrogen to selectively remove a silicon-rich oxide antireflective
coating material relative to the low k dielectric layer.
128. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising an organic fluoride cleaning agent comprising
nitrogen to selectively remove a silicon-rich oxynitride
antireflective coating material relative to the low k dielectric
layer.
129. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising an organic fluoride cleaning agent comprising
nitrogen to selectively remove a dielectric antireflective coating
and organic polymer material relative to the low k dielectric
layer.
130. A semiconductor device, comprising: an opening in a
carbon-based dielectric layer, wherein the opening has been cleaned
with a solution comprising an organic fluoride cleaning agent
comprising nitrogen to selectively remove a dielectric
antireflective coating and organic polymer material relative to the
carbon-based dielectric layer.
131. A semiconductor device, comprising: an opening in a dielectric
layer comprising carbon, wherein the opening has been cleaned with
a solution comprising an organic fluoride cleaning agent comprising
nitrogen to selectively remove a dielectric antireflective coating
and organic polymer material relative to the carbon-comprising
dielectric layer.
132. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising a cleaning agent effective to selectively
remove oxynitride antireflective coating material relative to the
low k dielectric layer.
133. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising a cleaning agent effective to selectively
remove silicon-rich oxide antireflective coating material relative
to the low k dielectric layer.
134. A semiconductor device, comprising: an opening in a low k
dielectric layer, wherein the opening has been cleaned with a
solution comprising a cleaning agent effective to selectively
remove silicon-rich oxynitride antireflective coating material
relative to the low k dielectric layer.
135. A semiconductor device, comprising: an opening in a
carbon-based low k dielectric layer, wherein the opening has been
cleaned with a solution comprising a cleaning agent effective to
selectively remove antireflective coating material relative to the
carbon-based low k dielectric layer.
136. A semiconductor device, comprising: an opening in a
carbon-based low k dielectric layer, wherein the opening has been
cleaned with a solution comprising a cleaning agent effective to
selectively remove oxynitride antireflective coating material
relative to the carbon-based low k dielectric layer.
137. A semiconductor device, comprising: an opening in a
carbon-based low k dielectric layer, wherein the opening has been
cleaned with a solution comprising a cleaning agent effective to
selectively remove silicon-rich oxide antireflective coating
material relative to the carbon-based low k dielectric layer.
138. A semiconductor device, comprising: an opening in a
carbon-based low k dielectric layer, wherein the opening has been
cleaned with a solution comprising a cleaning agent effective to
selectively remove silicon-rich oxynitride antireflective coating
material relative to the carbon-based low k dielectric layer.
139. A semiconductor device, comprising: a high aspect ratio
feature in a low k dielectric layer, wherein the feature has been
cleaned with a solution comprising a cleaning agent effective to
selectively remove antireflective coating material relative to the
low k dielectric layer.
140. The device of claim 139, wherein the high aspect ratio feature
comprises a via, a trench, or a combination thereof.
141. The device of claim 139, wherein the high aspect ratio feature
has an aspect ratio greater than about 0.5.
142. The device of claim 139, wherein the high aspect ratio feature
has a width dimension less than about 0.25 .mu.m.
143. A semiconductor device, comprising: an opening in a low k
dielectric layer, the opening having a critical dimension, wherein
the opening has been cleaned with a solution comprising a cleaning
agent effective to selectively remove antireflective coating
material relative to the low k dielectric layer.
144. The device of claim 143, wherein the opening comprises a via,
a trench, or a combination thereof.
145. The device of claim 143, wherein the opening has an aspect
ratio greater than about 0.5.
146. The device of claim 143, wherein the opening has a width
dimension less than about 0.25 .mu.m.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
device fabrication, and more particularly to methods of removing
post-etch polymer and dielectric antireflective coatings without
substantially etching the underlying dielectric layer, and
solutions used in such methods.
BACKGROUND OF THE INVENTION
[0002] The continuing trend in the semiconductor industry toward
densification of circuit devices has significantly improved
performance of electronic devices that use integrated circuits. In
a typical integrated circuit, individual circuit elements are
electrically connected together by a metallization process in which
layers of metal are deposited and patterned to form metal lines
that complete the circuit as designed. Multiple metal layers are
often employed. Metal lines within patterned metal layers are
insulated by interlevel dielectric layers from undesired electrical
contact both with other metal lines, whether in the same or another
metal layer, and with other circuit elements.
[0003] In the construction of integrated circuit structures,
dielectric materials such as silicon oxide (SiO.sub.2) have been
conventionally used to electrically separate conductive elements of
the integrated circuit structure. The increasing density of
integrated circuits has resulted in unneeded capacitance between
metal lines in an integrated circuit which slows circuit speed and
can cause cross-coupling between adjacent conductive elements.
[0004] The use of insulation materials having lower dielectric
constants (k values) than conventional silicon oxide (SiO.sub.2)
have been described. One such class of material is a carbon doped
silicon oxide material wherein at least a portion of the oxygen
atoms bonded to the silicon atoms are replaced by one or more
organic groups, for example, an alkyl group such as a methyl
(CH.sub.3) group. Such low k carbon doped silicon oxide dielectric
materials have dielectric constants varying from about 2.5 to about
3.5, and lowers the capacitance between conductive elements
separated by such dielectric materials.
[0005] In connecting overlying layers of metal lines separated by a
carbon-doped SiO.sub.2 interlayer dielectric (ILD) layer, a
photolithographic technique is used that typically employs a
dielectric antireflective coating (DARC) layer and an overlying
photoresist layer. High aspect ratio features such as vias/trenches
that are etched through the ILD layer to an underlying metal line
are subsequently cleaned to remove post-etch polymer and the DARC
layer before depositing the metal fill. Current cleaning
compositions etch a portion of the ILD layer during the cleaning
step, which can have a negative impact on and significantly alter
the critical dimensions of the etched feature.
[0006] Therefore, a need exists for a cleaning composition and
process that overcomes such problems.
SUMMARY OF THE INVENTION
[0007] The present invention provides methods of selectively
removing dielectric antireflective coatings (DARC) without
substantially etching the underlying dielectric layer, for example,
in the formation of conductive contacts in a semiconductor
structure. The invention further provides compositions for the
selective removal of post-etch polymer and a DARC layer. The method
and composition help prevent degradation of the exposed surfaces of
a low k carbon doped silicon oxide dielectric material during
removal of post-etch polymer and antireflective coating after
formation of vias or contact openings in the dielectric
material.
[0008] In one aspect, the invention provides a method of cleaning a
wafer surface. In one embodiment, the method comprises contacting a
wafer substrate having overlying layers of a carbon-doped low k
dielectric layer, a dielectric antireflective coating layer, and
post-etch polymer material, with a cleaning solution to selectively
remove the antireflective coating layer and the post-etch polymer,
with substantially no etching of the low k dielectric layer.
Preferably, the etch rate ratio of the DARC layer to the low k
dielectric layer is greater than 5:1, preferably greater than 10:1.
In one embodiment, the cleaning composition comprises an effective
amount of trimethylammonium fluoride (TMAF) to selective etch the
DARC layer and post-etch polymer material. In another embodiment,
the composition comprises effective amounts of TMAF and hydrogen
fluoride (HF). In a further embodiment, effective amounts of TMAF
and trimethylammonium hydroxide (TMAH) are combined to form the
cleaning composition.
[0009] In another aspect, the invention provides a method of
forming a conductive plug (via plug) and/or interconnect or
contact. In one embodiment, the method includes providing a wafer
comprising a substrate with an active area such as a metal line and
overlying layers of low k dielectric layer, a dielectric
antireflective coating (DARC) layer, and a photoresist layer;
forming a opening through the low k dielectric layer to the active
area on the substrate; and contacting the wafer with a cleaning
solution to selectively remove the dielectric antireflective
coating layer and post-etch polymer material with substantially no
etching of the low k dielectric layer. A conductive metal can then
be deposited to fill the opening (and/or trench) to form a
conductive plug and a metal line (interconnect, contact). The
method can be used to form single or dual damascene interconnects
and via plugs in the manufacture of integrated circuits.
[0010] In yet another aspect, the invention provides a cleaning
composition comprising one or more cleaning agents in amounts
effective to selectively remove a dielectric antireflective coating
(DARC) layer overlying a carbon-doped low k dielectric layer at an
etch rate of the DARC layer to the low k dielectric layer that is
greater than the etch rate ratio of the DARC material to TEOS. In
one embodiment, the cleaning composition is formulated such that
contact of the cleaning composition with a carbon-doped low k
dielectric blanket layer for a time period of up to about 15
minutes results in no measurable removal of a carbon-doped low k
dielectric layer. In other embodiments, the cleaning composition
comprises about 10 to about 40 wt % TMAF and, optionally, about 0
to about 10 wt % HF, or about 0 to about 25 wt % TMAH. The cleaning
composition can have a pH over a range of about 0.3.5 to about
14.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings, which are
for illustrative purposes only. Throughout the following views, the
reference numerals will be used in the drawings, and the same
reference numerals will be used throughout the several views and in
the description to indicate same or like parts.
[0012] FIG. 1 is a diagrammatic cross-sectional view of a
semiconductor wafer fragment at a preliminary step of a processing
sequence.
[0013] FIGS. 2-6 are views of the wafer fragment of FIG. 1 at
subsequent and sequential processing steps, showing fabrication of
a via plug and metal line according to an embodiment of the method
of the invention.
[0014] FIGS. 7-10 depict another embodiment of the method of the
invention in the formation of a via plug, showing steps in the
subsequent and sequential processing of the wafer fragment of FIGS.
1-2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] The invention will be described generally with reference to
the drawings for the purpose of illustrating the present preferred
embodiments only and not for purposes of limiting the same. The
figures illustrate processing steps for use in the fabrication of
semiconductor devices in accordance with the present invention. It
should be readily apparent that the processing steps are only a
portion of the entire fabrication process.
[0016] In the current application, the terms "semiconductive wafer
fragment" or "wafer fragment" or "wafer" will be understood to mean
any construction comprising semiconductor material, including but
not limited to bulk semiconductive materials such as a
semiconductor wafer (either alone or in assemblies comprising other
materials thereon), and semiconductive material layers (either
alone or in assemblies comprising other materials). The term
"substrate" refers to any supporting structure including, but not
limited to, the semiconductive wafer fragments or wafers described
above.
[0017] An embodiment of a method of the present invention is
described with reference to FIGS. 1-6. As shown, a dual damascene
process is used to form a via and interconnect associated with an
active area of a semiconductor circuit. It is understood that the
method of the invention can be used in a single damascene process
or other process to form a via plug or metal line.
[0018] The via plug/metal line is illustrated and will be described
as being coupled to a conductive area 16, but can be used wherever
required within the structure of a semiconductor circuit.
[0019] Referring to FIG. 1, a wafer fragment 10 is shown at a
preliminary processing step. The wafer fragment 10 in progress can
comprise a semiconductor wafer substrate or the wafer along with
various process layers formed thereon, including one or more
semiconductor layers or other formations, and active or operable
portions of semiconductor devices.
[0020] The wafer fragment 10 is shown as comprising a substrate 12,
a conductive (active) area 14, an overlying interlayer dielectric
(ILD) layer 16, and an overlying dielectric antireflective coating
(DARC) layer 18. An exemplary substrate 12 is monocrystalline
silicon. The conductive area 14 can comprise a conductor or
semiconductor material, for example, a doped silicon region such as
a source/drain region, or an underlying conductive runner or wiring
layer, as shown in the illustrated example. The wiring layer can
comprise, for example copper or aluminum, or other conductive metal
depending upon the function and desired conductivity of the circuit
element.
[0021] The interlayer dielectric (ILD) layer 16 comprises a low k
oxide material formed over the conductive area 14, typically to a
thickness of about 2,000 to about 10,000 angstroms. The ILD layer
16 comprises a modified silicon oxide (SiO.sub.2) insulation layer
that can be formed using a carbon-substituted silane precursor such
as trimethylsilane (TMS). The ILD layer 16 preferably has a
dielectric constant of about 2.5 to about 3.5.
[0022] An exemplary process for forming a carbon doped low k
silicon oxide ILD layer 16 comprises flowing into a chemical vapor
deposition (CVD) chamber, about 60 to about 1000 sccm TMS, with an
oxygen source such N.sub.2O at about 200 to about 1000 sccm, or
O.sub.2 at about 50 to about 500 sccm, combined with helium (He) to
dilute the gases at a flow rate of about 200 to about 1,000 sccm or
higher, preferably with plasma enhancement. In an example and
preferred process, about 60 to about 150 sccm TMS, about 300 to
about 500 sccm N.sub.2O, and about 300 to 500 sccm He are flowed
into the deposition chamber. In another example and preferred
process, about 500 to about 700 sccm TMS with about 80 to about 150
sccm O.sub.2 are flowed into the reaction chamber. A standard CVD
chamber can be used, such as a DxZ chamber (Applied Materials).
Preferred processing conditions include a temperature of about
300.degree. C. to about 450.degree. C., a pressure of about 3 Torr
to about 7 Torr, and an rf power of about 200 W to about 800 W.
[0023] The dielectric antireflective coating (DARC) layer 18 is
deposited over the low k carbon doped ILD layer 16 to a thickness
to provide anti-reflective properties, typically about 150 to about
650 angstroms or more. In a photolithography process, the DARC
layer 18 aids in preventing undesirable light reflection during a
step of "setting" a photoresist layer, and also prevents profile
distortion. Preferably, the DARC layer 18 reduces reflected
radiation reaching an overlying layer of photoresist to less than
about 10% or as low as less than 1%, depending on the process
sensitivity of incident radiation at the DARC layer 18.
[0024] A variety of DARC materials can be used that absorb various
wavelengths of radiation. Preferably, the DARC layer comprises a
silicon-rich oxide or a silicon-rich oxynitride. The DARC layer 18
preferably comprises amounts of silicon, oxygen, and nitrogen,
optionally with an amount of hydrogen, to form a silicon-rich
oxynitride film of Si.sub.xO.sub.yN.sub.2:H, preferably where
x=0.30 to 0.65, y=0.02 to 0.56, and z is 0.05 to 0.33, or a
silicon-rich oxide Si.sub.xO.sub.y:H, preferably where x=0.30 to
0.65, and y=0.25 to 0.60. The relative values of x, y and z and the
hydrogen content can be adjusted to alter absorbence
characteristics of the deposited layer. Exemplary DARC films
include silicon, oxygen and nitrogen DARC materials disclosed, for
example, in U.S. Pat. No. 6,225,671 (Yin), U.S. Pat. No. 6,268,282
(Sandhu et al.), and U.S. Pat. No. 5,698,352 (Ogawa et al.).
[0025] The DARC layer 18 can be deposited by known processes, such
as CVD or preferably by plasma-enhanced CVD (PECVD) including, for
example, electron cyclotron resonance (ECR) PECVD, and bias ECR
PECVD processes. Exemplary conditions for depositing the DARC layer
18 include flowing a silicon-containing precursor such as silane
(SiH.sub.4) at a rate of about 40 to about 300 sccm, preferably
about 60 to about 225 sccm, preferably about 80 sccm; an oxygen
source gas such as nitrous oxide (N.sub.2O) or oxygen (O.sub.2) at
a rate of about 80 to about 600 sccm, preferably about 95 to about
550 sccm, preferably about 80 sccm; with argon, helium or other
inert gas at a rate of about 1300 to about 2500 sccm, preferably
about 2200 sccm, depending on the photo requirements of the DARC
film.
[0026] The gases can be flowed into a plasma-enhanced CVD chamber
at a temperature of about 400.degree. C., under a pressure of about
4 Torr to about 6.5 Torr, and an rf power to the chamber of about
50 to about 200 watts, preferably about 100 watts.
[0027] As shown in FIG. 2, a photoresist layer 20 is formed over
the DARC layer 18 by known techniques, for example, a spin-on
process. The photoresist layer 20 can comprise either a positive or
negative photoresist. Exemplary photoresists comprise an organic
polymeric material, and include those comprising a novolac resin, a
diazonaphthaquinone, and a solvent (e.g., n-butyl alcohol or
xylene), and negative photoresist materials such as those
comprising a cyclized synthetic rubber resin, bis-arylazide, and an
aromatic solvent.
[0028] As shown in FIG. 3, the ILD layer 16 and the DARC layer 18
can then be patterned and etched using a known two-tier etch
process, typical when forming damascene contacts, to form dual
inlaid openings that include a contact opening or via 22 and an
interconnect channel or trench 24. Etching of the ILD and DARC
layers can be performed using known techniques, for example, a
plasma etch using one or more of Cl.sub.2, HBr, CF.sub.4,
CH.sub.2F.sub.2, and helium and NF.sub.3. Typically, a trench or
groove 24 is etched into the ILD layer 16, and then the contact
opening 22 is etched to extend to the underlying conductive
(active) region 14 in the substrate. The trench 24 forms a channel
from the contact opening 22 to other circuit elements (not shown).
Typically, the contact opening 22 has a width less than about 0.25
.mu.m, more preferably less than about 0.20 .mu.m, resulting in an
aspect ratio greater than about 0.5, preferably greater than about
8. The photoresist is removed through an oxygen plasma ashing step,
a wet piranha (H.sub.2SO.sub.4/H.sub.2O.sub.2 mixture) step, or a
combination of both.
[0029] Referring to FIG. 4, once the etch step and photoresist
strip step are completed, a post-etch cleaning (arrows 26) is
performed using a single step wet etch to selectively remove the
DARC layer 1-8 and any remaining post-etch polymer 26. Post-etch
polymer 26 generally comprises the polymer residue by-products
remaining after the etch and photoresist strip.
[0030] According to the invention, the wet etch cleaning
composition comprises relative amounts of one or more cleaning
agents to selectively etch the DARC layer 18 at a desired rate
without substantially etching the ILD layer 16. The wet etch
composition can have a pH over a range of about 3.5 to about 14,
and is preferably about pH 6.5. The cleaning composition preferably
comprises tetramethylammonium fluoride (TMAF), a mixture of TMAF
and hydrogen fluoride (HF), or a mixture of TMAF and
trimethylammonium hydroxide (TMAH).
[0031] In one embodiment, the cleaning composition comprises an
effective amount of tetramethylammonium fluoride (TMAF) to
selectively remove the DARC layer 18 and post-etch polymer 26
relative to the low k dielectric layer 16. Preferably, the cleaning
composition comprises about 10 to about 40 wt % TMAF. The TMAF
solution can be prepared by known methods in the art. For example,
a TMAF cleaning composition can be prepared by combining a standard
aqueous (49 wt %) HF solution with a standard aqueous (25 wt %)
TMAH solution in an effective volume ratio concentration such that
the resultant composition preferably comprises about 10 to about 40
wt % TMAF.
[0032] In another embodiment, the cleaning composition can comprise
an effective amount of TMAF combined with an amount of hydrogen
fluoride (HF), to selectively remove the DARC layer 18 and
post-etch polymer material 26. Preferably, the cleaning composition
comprises about 10 to about 40 wt % TMAF and up to about 10 wt %
HF. The TMAF/HF cleaning composition can be prepared, for example,
by combining an aqueous TMAF solution with about up to about 10 wt
% of a standard aqueous (49 wt %) HF solution. In another example,
the cleaning composition can also be prepared by combining TMAH (25
wt % solution) with an excess amount of HF (49 wt % solution) to
form a TMAF and HF cleaning composition. An example and preferred
composition comprises a volume ratio concentration of TMAH (25 wt
%): HF (49 wt %) of about 4:1 to about 11:1, preferably about a 9:1
volume ratio.
[0033] In yet another embodiment, the cleaning composition is
formulated with effective amounts of TMAF and TMAH cleaning agents
to selectively remove the DARC layer 18 and post-etch polymer
material 26. Preferably, the cleaning composition comprises about
10 to about 40 wt % TMAF and up to about 25 wt % TMAH. The
TMAF/TMAH cleaning composition can be prepared by combining a
standard aqueous (25 wt %) TMAH solution with an aqueous TMAF
solution.
[0034] To avoid undesirable modification of the critical dimensions
(CD) of the etched features, the cleaning composition comprises
amounts of the cleaning agents to provide an etch selectivity ratio
of the DARC layer to the low k ILD layer (DARC: low k ILD) that is
greater than the DARC:TEOS etch rate ratio of the particular DARC
material that is utilized, to limit etching of the low k ILD layer,
preferably to about zero (0) to less than 50 angstroms. The etch
rates of various DARC materials are shown in Table 1 of the
Example. Preferably, the etch rate ratio of the DARC: low k ILD
layer is greater than 2:1, preferably greater than 5:1, preferably
about 9:1 to about 1:1 or greater, and more preferably about 100:1
to about 1,000:1 or greater. The cleaning composition provides
effective and easy removal of the DARC layer 18 and post-etch
polymer 26 while controlling the etch rate of other wafer regions
such that essentially no etching of the ILD layer 16 occurs during
the cleaning step.
[0035] The cleaning composition can be applied to the wafer in
various ways. For example, the cleaning composition can be sprayed
onto the wafer, or the wafer can be dipped or immersed-into a bath
of the cleaning composition, among others. The cleaning composition
can be used at a temperature of about 5 to about 65.degree. C.,
preferably about 20 to about 50.degree. C. The length of the
contact of the cleaning composition with the wafer surface
generally depends on the thickness and the character of the DARC
layer. For example, a 6-minute dip using a 9:1 volume ratio of TMAH
(25 wt %): HF (49 wt %) can be used to remove about 600 angstroms
of a DARC film, with the wet etch rate for the low k ILD layer
being about zero (0). By comparison, in six (6) minutes, the
foregoing composition typically removes about 200 angstroms of a
TEOS deposited layer, which causes CD loss of features etched in a
TEOS ILD layer. The contact time of the composition generally
ranges from about 1 to about 15 minutes.
[0036] After the cleaning step, a conductive metal layer 30 can
then be deposited to fill the trench 24 and the contact opening 22,
as shown in FIG. 5. Examples of conductive metals include aluminum,
copper, and tungsten. The conductive metal 30 can be deposited by
conventional methods, such as physical vapor deposition (PVD)
(sputtering) or CVD. The metal layer 36 can be subsequently
planarized by chemical mechanical planarization (CMP) or etched
back so that the metal remains isolated in paths within the trench
24 and opening 22, resulting in the metal line (interconnect or
contact) 32, conducting plug 34, and metal layer 36, as depicted in
FIG. 6.
[0037] In another embodiment of the method of the invention, a
single opening or via can be etched through the ILD layer, cleaned
with the cleaning composition, and filled with a conductive metal
to form a via plug, as depicted in FIGS. 7-10.
[0038] For example, the wafer fragment shown in FIG. 2, having a
low k dielectric (ILD) layer 16', DARC layer 18', and overlying
photoresist layer 20', can be patterned and etched to form a single
opening or via 22', as illustrated in FIG. 7. Referring to FIG. 8,
after the etch step and a photoresist strip step, a post-etch
cleaning (arrows 26') can then be performed using the cleaning
composition of the invention to selectively etch the DARC layer 18'
and any post-etch polymer 26', with little or no etching of the low
k ILD layer 16', preferably removing less than 50 angstroms of the
ILD layer.
[0039] Thereafter, a conductive metal layer 30' can be deposited to
fill the opening 22', as shown in FIG. 9. The metal layer 36' can
be subsequently planarized by CMP or etched back so that the metal
remains isolated in the contact opening 22', resulting in the
conducting plug 34', as shown in FIG. 10.
EXAMPLE
[0040] Wafers were provided with various oxide film layers and DARC
film layers, as shown in Table 1 below. The wafers were immersed
for 6 minutes in a bath containing a 9:1 volume ratio TMAH:HF
solution (25 wt % TMAH solution; 49 wt % HF solution). The pH of
the solution was 6.5, and the bath temperature was 21.5.degree.
C.
1 TABLE 1 Thickness .DELTA..sup.1 Film type (angstroms) Thermal
oxide 33 Rich BPSG, annealed 74 TEOS, as deposited 223 320 DARC 330
I-line DARC 454 DUV DARC 740 HER DARC >1006 Fuse DARC 547 Low k
film 0 .sup.1"Thickness .DELTA." is the change in thickness of the
films by the wet etch step.
[0041] All DARC films were stripped and piranhaed before being
tested. The low k film was not etched at all during a 15 minute
dip.
[0042] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
* * * * *