U.S. patent application number 10/855562 was filed with the patent office on 2004-12-02 for semiconductor device with interconnection structure for reducing stress migration.
This patent application is currently assigned to NEC ELECTRONICS CORPORATION. Invention is credited to Ito, Takamasa, Kawano, Masaya, Yamamoto, Yoshiaki.
Application Number | 20040238964 10/855562 |
Document ID | / |
Family ID | 33447862 |
Filed Date | 2004-12-02 |
United States Patent
Application |
20040238964 |
Kind Code |
A1 |
Kawano, Masaya ; et
al. |
December 2, 2004 |
Semiconductor device with interconnection structure for reducing
stress migration
Abstract
The semiconductor device of the present invention includes a
first interconnection, a via-plug that is connected to the first
interconnection, and a second interconnection that is formed as a
single unit with the via-plug. The cross-sectional shape of the
via-plug is such that the plug sidewall angle, which indicates the
angle of the via-plug sidewall with respect to the surface of the
first interconnection, is a positive angle; and moreover, at least
two points exist between the base and the top of the via-plug on at
least one sidewall of the two sidewalls of the cross-sectional
shape of the via-plug at which the plug sidewall angle attains a
maximum value. Since shapes that would give rise to the occurrence
of concentrations of stress are not formed in the via-plug
sidewalls, metal is more effectively embedded in the via-hole, and
the incidence of voids is prevented.
Inventors: |
Kawano, Masaya; (Kawasaki,
JP) ; Yamamoto, Yoshiaki; (Kawasaki, JP) ;
Ito, Takamasa; (Kawasaki, JP) |
Correspondence
Address: |
SUGHRUE MION, PLLC
2100 PENNSYLVANIA AVENUE, N.W.
SUITE 800
WASHINGTON
DC
20037
US
|
Assignee: |
NEC ELECTRONICS CORPORATION
|
Family ID: |
33447862 |
Appl. No.: |
10/855562 |
Filed: |
May 28, 2004 |
Current U.S.
Class: |
257/758 ;
257/E21.578; 257/E21.579; 257/E21.585; 257/E23.145;
257/E23.167 |
Current CPC
Class: |
H01L 21/76804 20130101;
H01L 2924/0002 20130101; H01L 21/76808 20130101; H01L 23/53295
20130101; H01L 2924/0002 20130101; H01L 23/5329 20130101; H01L
21/76877 20130101; H01L 23/5226 20130101; H01L 23/53238 20130101;
H01L 2924/00 20130101 |
Class at
Publication: |
257/758 |
International
Class: |
H01L 021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
May 30, 2003 |
JP |
2003-154728 |
Claims
What is claimed is:
1. A semiconductor device having a first interconnection, a
via-plug that is connected to said first interconnection, and a
second interconnection that is formed as a single unit with said
via-plug; wherein: regarding a plug sidewall angle in a
cross-sectional shape of said via-plug, said plug sidewall angle
being an angle formed between: a line that joins an arbitrary point
of a sidewall of said via-plug and a point of intersection between
a line that passes through said arbitrary point and that is
parallel to a surface of said first interconnection and a central
axis of said via-plug, and a line that joins said arbitrary point
and a point of intersection between a tangent line at said
arbitrary point and said central axis, an angle of depression from
a line that is parallel to the surface of said first
interconnection is a positive angle, and an angle of elevation from
a line that is parallel to the surface of said first
interconnection is a negative angle; and in the cross-sectional
shape of said via-plug, said plug sidewall angle is a positive
angle; and there are at least two points between a base and a top
of said via-plug on at least one of two sidewalls of said via-plug
cross-sectional shape at which said plug sidewall angle attains a
maximum value.
2. The semiconductor device according to claim 1, wherein said plug
sidewall angle at arbitrary points of the sidewalls of said
via-plug is a positive angle.
3. The semiconductor device according to claim 1, wherein said plug
sidewall angle is equal to or less than 900.
4. The semiconductor device according to claim 1, wherein said plug
sidewall angle is a continuous value between said two points of
maximum value.
5. The semiconductor device according to claim 1, wherein said plug
sidewall angle at an arbitrary point, said arbitrary point being
between a point on the sidewall of said via-plug at which said plug
sidewall angle becomes a minimum value between said two maximum
values and the base of said via-plug, is less than 90.degree..
6. The semiconductor device according to claim 1, comprising a
metal diffusion prevention film that is formed on said first
interconnection; wherein said plug sidewall angle at arbitrary
points of the sidewall of said via-plug at a portion of said metal
diffusion prevention film is an angle less than 90.degree..
7. A fabrication method of a semiconductor device, said
semiconductor device having a first interconnection, a via-plug
that is connected to said first interconnection, and a second
interconnection that is connected to said via-plug; said
fabrication method comprising the steps of: successively forming on
said first interconnection: a first metal diffusion prevention
film, an interlayer dielectric film, an etching stopper film, and
an intralayer dielectric film; using a lithographic process and an
etching process to form a first opening in a prescribed opening
pattern in said interlayer dielectric film, said etching stopper
film, and said intralayer dielectric film; applying an
antireflective coating for preventing a reflection of light by said
first interconnection, and forming a second opening in said first
opening in which said antireflective coating is buried such that a
position of an upper surface of said antireflective coating is
lower than a lower surface of said etching stopper film; forming a
resist film having a prescribed pattern of trench openings in said
intralayer dielectric film; performing etching with said resist
film as a mask to form a trench opening in said intralayer
dielectric film, and forming sidewalls of said interlayer
dielectric film of said second opening such that a diameter of said
second opening is progressively larger from a bottom toward a top
of said second opening; removing said resist film and said
antireflective coating; etching from the trench opening that has
been formed in said intralayer dielectric film to remove said
etching stopper film and said first metal diffusion prevention film
that have been exposed on upper surfaces and forming a via-hole
that includes said second opening and the trench opening of said
second interconnection; and embedding a metal in said via-hole and
the trench opening of said second interconnection to form said
via-plug and said second interconnection, and then forming a second
metal diffusion prevention film.
8. The fabrication method of a semiconductor device according to
claim 7, wherein: regarding a plug sidewall angle in a
cross-sectional shape of said via-hole following formation of said
via-hole, said plug sidewall angle being an angle formed between: a
line that joins an arbitrary point of a sidewall of said via-hole
and a point of intersection of a line that passes through said
arbitrary point and that is parallel to a surface of said first
interconnection and a central axis of said via-hole, and a line
that joins said arbitrary point and a point of intersection between
a tangent line at said arbitrary point and said central axis, an
angle of depression from a line that is parallel to the surface of
said first interconnection is a positive angle, and an angle of
elevation from a line that is parallel to the surface of said first
interconnection is a negative angle; and in the cross-sectional
shape of said via-hole, said plug sidewall angle is a positive
angle; and at least two points exist between a base and a top of
said via-hole on at least one of two sidewalls of said via-hole
cross-sectional shape at which said plug sidewall angle attains a
maximum value.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device
having interconnections and a via-plug for connecting the
interconnections together, and to a fabrication method for such a
semiconductor device.
[0003] 2. Description of the Related Art
[0004] Among semiconductor devices such as memory and logic devices
are those that conventionally include an interconnection structure
in which interconnections are connected together by via-plugs. FIG.
1 is a sectional view showing an example of the configuration of a
semiconductor device of the prior art. As shown in FIG. 1, the
semiconductor device is a configuration that includes:
interconnection 120 on lower dielectric film 110 that is formed on
a semiconductor substrate (not shown); via-plug 230 that is
connected to interconnection 120; and interconnection 140 that is
connected to via-plug 230. Via-plug 230 and interconnection 140 are
formed as a single unit.
[0005] The effect of the shape of via-plugs upon stress migration
in such an interconnection structure has previously been documented
(T. Oshima et al., "Suppression of stress-induced voiding in copper
interconnects," IEDM (2002)).
[0006] However, although the effect of the shape of via-plugs upon
stress migration has been touched upon in the above-described
literature, nothing has been disclosed regarding methods of solving
this problem, and it is unclear how stress migration can be
reduced.
SUMMARY OF THE INVENTION
[0007] It is an object of the present invention to provide a
semiconductor device having an interconnection structure for
reducing stress migration and a method of fabricating such a
semiconductor device.
[0008] The semiconductor device of the present invention includes:
a first interconnection; a via-plug that connects to the first
interconnection; and a second interconnection that is formed as a
unit with the via-plug; wherein a cross-sectional shape of the
via-plug is a configuration in which a plug sidewall angle, which
indicates an angle of the via-plug sidewall with respect to the
surface of the first interconnection, is a positive angle; and
moreover, that has at least two points between a base and a top of
the via-plug on at least one of the two sidewalls of the
cross-sectional shape of the via-plug at which the plug sidewall
angle attains a maximum value.
[0009] More specifically, the plug sidewall angle is an angle
formed between: a line that joins an arbitrary point of a sidewall
of the via-plug and a point of intersection of a line that passes
through that arbitrary point and that is parallel to the first
interconnection and a central axis of the via-plug; and a line that
joins that arbitrary point and a point of intersection between a
tangent line at that arbitrary point and the central axis. In
addition, regarding the plug sidewall angle, an angle of depression
from a line that is parallel to the surface of the first
interconnection is a positive angle, and an angle of elevation from
a line that is parallel to the first interconnection is a negative
angle.
[0010] In the present invention, the plug sidewall angle in the
cross-sectional shape of the via-plug does not become a negative
angle, and as a result, shape that would cause stress to
concentrate are not formed in the via-plug sidewalls of the
via-plug cross-sectional shape. In addition, because a minimum
value exists between the two maximum values for the plug sidewall
angle, an inclination of the sidewall changes such that a via-hole
diameter increases midway from the via-plug base to the top, and
the essential aspect ratio of the via-hole is therefore smaller
than for a simple tapered shape.
[0011] In addition, if the plug sidewall angle is a positive angle
at any point of the via-plug sidewall, a sidewall shape will be
formed in which the plug sidewall angles are positive angles for
all of the via-plug sidewalls. As a result, a shape that would
cause stress to concentrate is not formed on any of the via-plug
sidewalls.
[0012] In addition, when the plug sidewall angle is less than or
equal to 90.degree., the via-hole sidewalls will have a shape that
is amenable to burying metal in the via-hole interior.
[0013] Still further, if the plug sidewall angle is a continuous
value between the maximum values, the via-hole sidewalls will have
a gentle shape between the points on the sidewalls at which the
plug sidewall angles attain maximum values even if the plug
sidewall angle has a maximum value that approaches 90.degree.. As a
result, a shape that would give rise to concentrations of stress
will not be formed even when an angle of 90.degree. is approached
or between differing inclinations.
[0014] In addition, the amenability of the via-hole interiors to
filling with metal is further improved when the plug sidewall angle
is less than 90.degree. between the via-plug base and the points on
via-plug sidewalls at which the plug sidewall angle becomes a
minimum value between maximum values.
[0015] Moreover, the amenability of the via-hole interiors to
filling with metal is further improved if a metal diffusion barrier
film is included on the first interconnection, and if the plug
sidewall angle at the position of the side surface of the metal
diffusion barrier film is less than 90.degree..
[0016] Accordingly, shapes that would bring about a concentration
of stress are not formed on the via-plug sidewalls in the
semiconductor device of the present invention, and as a result, the
via-hole interior is more amenable to filling with metal, and the
occurrence of voids can be prevented. Moreover, stress migration is
reduced and the reliability of the interconnections is
improved.
[0017] The above and other objects, features, and advantages of the
present invention will become apparent from the following
description with reference to the accompanying drawings, which
illustrate examples of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 is a sectional view showing an example of the
configuration of a semiconductor device of the prior art;
[0019] FIG. 2A is a sectional view showing an example of the
configuration of a semiconductor device of the present
invention;
[0020] FIG. 2B is a plan view showing an example of the
configuration of the semiconductor device of the present
invention;
[0021] FIG. 3 is a schematic view showing the sectional shape of a
via-plug;
[0022] FIG. 4 is a graph showing the via-plug sidewall shape in the
semiconductor device shown in FIG. 2A;
[0023] FIG. 5 is a graph showing the via-plug sidewall shape of the
semiconductor device shown in FIG. 1;
[0024] FIG. 6 is a graph showing the dependency of stress migration
failure rate upon the interconnection width of the upper metal;
[0025] FIGS. 7A to 7N are sectional views showing the method of
fabricating the semiconductor device of the present invention;
[0026] FIG. 8A is a sectional view showing the configuration of the
semiconductor device of the second working example; and
[0027] FIG. 8B is a plan view showing the configuration of the
semiconductor device of the second working example.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIRST WORKING EXAMPLE
[0028] As shown in FIG. 2A, the semiconductor device is a
configuration that includes: interconnection 120 on lower
dielectric film 110 that is formed on a semiconductor substrate
(not shown); via-plug 130 that is connected to interconnection 120;
and interconnection 140 that is connected to via-plug 130. Via-plug
130 and interconnection 140 are formed as a single unit.
Interconnection 120, via-plug 130, and interconnection 140 each
include the conductive material copper (Cu) and a barrier metal
film for preventing diffusion of the copper.
[0029] Intralayer dielectric film 112 for insulating
interconnection 120 from interconnections that are formed on the
same level is formed on lower dielectric film 110. The upper
surface of interconnection 120 is covered by Cap-SiCN film 152,
which forms a metal diffusion prevention film for preventing the
diffusion of copper at points other than the points of connection
with via-plug 130. Interconnection 140 is formed in intralayer
dielectric film 116, and interlayer dielectric film 114 is formed
between interconnection 120 and interconnection 140. Cap-SiCN film
156 is formed as a metal diffusion prevention film on
interconnection 140.
[0030] Stopper-SiC film 150 is formed to act as an etching stopper
film between lower dielectric film 110 and intralayer dielectric
film 112. Stopper-SiC film 154 is formed as an etching stopper film
between interlayer dielectric film 114 and intralayer dielectric
film 116.
[0031] Interlayer dielectric film 114 is a silicon oxide film.
Intralayer dielectric film 112 and intralayer dielectric film 116
are ladder oxide films having a ladder-type hydrogenated siloxane
structure. In the following explanation, ladder oxide films are
referred to as "L-Ox (a registered trademark of NEC Electronics
Corporation) films".
[0032] Semiconductor elements such as transistors, resistors,
capacitors are formed on the semiconductor substrate, but the
structure of the semiconductor elements is similar to that of
semiconductor elements of the prior art, and detailed explanation
of this structure is therefore here omitted.
[0033] The following explanation regards the angles of the
sidewalls of the via-plug in the sectional shape of the
semiconductor device that is shown in FIG. 2A.
[0034] FIG. 3 is a schematic view showing the sectional shape of a
via-plug. In FIG. 3, via-plug 130 is connected to interconnection
120. Lt is a line that is tangent to an arbitrary point 330 of the
via-plug sidewall, and Lp is a line at point 330 that is parallel
to the surface of interconnection 120. Further, Lc is the central
axis of the via-plug. Point 340 is the point of intersection
between line Lp at point 330 and central axis Lc, and point 350 is
the point of intersection between tangent line Lt at point 330 and
central axis Lc. Plug sidewall angle .theta. is the angle formed
between the line formed by joining point 340 and point 330 and the
line formed by joining point 330 and point 350. In addition, the
angle of depression from line Lp for this plug sidewall angle is a
positive angle, and the angle of elevation from line Lp is a
negative angle.
[0035] In the semiconductor device that is shown in FIG. 2A, the
above-described plug sidewall angle is a positive angle greater
than 0.degree. and less than or equal to 90.degree. from the top of
the via-plug at the base of interconnection 140 to the base of the
via-plug. This point is explained hereinbelow using a graph that
shows the shape of the via-plug sidewall.
[0036] FIG. 4 is a graph showing the shape of the via-plug sidewall
of the semiconductor device shown in FIG. 2A. The vertical axis
shows the value of the plug sidewall angle, and the horizontal axis
shows the distance from the top of the via-plug when tracing the
sidewall of the via-plug shown in FIG. 2A. Point 300 on the
horizontal axis shows the top of the via-plug, and point 320 shows
the base of the via-plug. Point 310 shows an intermediate point
between point 300 and point 320.
[0037] As shown in FIG. 4, the plug sidewall angle increases
gradually from the angle at point 300, and decreases gradually upon
exceeding a maximum value. After attaining a minimum value at point
310, the angle again gradually increases to reach a maximum value,
whereupon the angle decreases up to point 320. The plug sidewall
angle is never a negative angle, and sidewall of the via-plug is
therefore formed in a smooth shape. In addition, as shown in the
graph, the plug sidewall angle has two maximum values, is a
continuous value between the two maximum values, and has no
discontinuous points. The plug sidewall angle varies gradually
before and after point 310 and does not change radically even at
point 310 where the plug sidewall angle reaches a minimum value.
Although the sidewall angle does not attain 90.degree. in this
graph, points with a 90.degree. are permissible.
[0038] As with the above-described plug sidewall shape, the plug
sidewall angle does not become a negative angle, and there are
consequently no areas that would give rise to a concentration of
stress. As a result, stress migration in the via-plug is reduced.
In the shape of the via-plug sidewall, moreover, the plug sidewall
angle has at least two maximum values, and further, has a minimum
value between these maximum values. At the point of this minimum
value, the inclination of the sidewalls changes such that the
diameter of the via-hole (hereinbelow referred to as "via-hole
diameter") increases midway from the base of the via-plug to the
top of the via-plug, and the essential aspect ratio of the via-hole
therefore is smaller than that of a simple tapered shape. As a
result, the via-hole is more amenable to filling when the via-hole
is filled with copper. As a result of these factors, stress
migration inside the via-plug is reduced and an interconnection
having high reliability is obtained.
[0039] FIG. 2B is a plan view showing the pattern of
interconnection 140 and via-plug 130. Point 300 of FIG. 2B shows
the top of the via-plug, and point 320 shows the base of the
via-plug. As shown in FIG. 2B, the shape of the sidewall from
via-plug base 320 to via-plug top 300 that is shown in FIG. 2A is
formed on all of the via-plug sidewalls.
[0040] The following explanation regards the shape of the
above-described via-plug sidewalls for a case in the prior art. The
film configuration of the semiconductor device of the prior art is
similar to that of the semiconductor device of the present
invention shown in FIG. 2A, and a detailed explanation of this
configuration is therefore omitted.
[0041] As shown in FIG. 1, a protuberance is formed at the position
shown by point 410 on the sidewalls of via-plug 230. This shape is
next explained using a graph that shows the plug sidewall
angle.
[0042] FIG. 5 is a graph showing the shape of the via-plug sidewall
of the semiconductor device shown in FIG. 1. The vertical axis
shows the value of the plug sidewall angle, and the horizontal axis
shows the distance from the top of the via-plug when tracing the
via-plug sidewall that is shown in FIG. 1. Point 400 on the
horizontal axis shows the via-plug top, and point 420 shows the
via-plug base. Point 410 shows an intermediate point between point
400 and point 420.
[0043] As shown in FIG. 5, the plug sidewall angle first increases
from point 400 that indicates the via-plug top, but after attaining
a maximum value, decreases and then becomes a negative angle at
point 410. From point 410, the plug sidewall angle again increases,
and after continuing as a substantially fixed value, drops
precipitously to point 420 (O). A protuberance is thus formed at
the position at which the plug sidewall angle becomes a negative
angle. Stress is consequently focused at the protuberance in the
via-hole, and stress migration tends to occur in the via-plug. In
addition, the via-hole is not amenable to filling with copper, and
voids tend to occur in the via-plug. The formation of voids
decreases the product yield, and further, leads to the breakdown of
connections between interconnection 120 and interconnection 140 as
voids grow in the course of extended use of the semiconductor
device.
[0044] The following explanation regards an appraisal of stress
migration for the interconnection structures of the semiconductor
device shown in FIG. 2A and the semiconductor device shown in FIG.
1. In this explanation, Sample A is a sample produced according to
the interconnection structure of the semiconductor device shown in
FIG. 2A, and Sample B is a sample produced according to the
interconnection structure of the semiconductor device shown in FIG.
1. In addition, interconnection 120 is referred to as
"lower-metal," and interconnection 140 is referred to as
"upper-metal."
[0045] In this appraisal, a via-chain TEG (Test Element Group) was
used in which the connections of the lower-metal, via-plug and
upper-metal were formed by repeating a prescribed number of times.
In addition, several conditions were set regarding the
interconnection width of the upper-metal based on a range of 0.2-10
.mu.m, where the interconnection width is the direction that is
perpendicular to the longitudinal direction of the interconnections
in the planar pattern of the interconnections. The interconnection
width of the lower-metal was fixed.
[0046] Experimentation was carried out as follows: Samples A and
Samples B were each fabricated, a plurality of via-chain TEGs being
formed according to the above-described conditions. Samples A and
Samples B were next kept at a temperature of 150.degree. C. for 168
hours, following which the via-chain TEGs were subjected to the
application of voltage and then checked to determine whether
current flowed. Via-chain TEGs in which current did not flow at
this time were determined to be defective due to stress
migration.
[0047] The above-described conditions on the interconnection width
of the upper-metal in this appraisal were established because
stress migration failures tend to occur with increase in the
interconnection width of the upper-metal.
[0048] Regarding the reasons for this phenomenon, heat treatment in
the process of fabricating a semiconductor device causes residual
tensile stress in interconnections. Stress migration is the
phenomenon by which metal atoms move through the interconnections
or via-plugs to relieve this tensile stress. Voids are generated in
a via-plug to relieve the stress of the upper-metal. When the
interconnection width of the upper-metal is small, the stress is
relieved even though the volume of the voids is small. In contrast,
when the interconnection width is great, the alleviation of stress
is inadequate when the volume of the voids is small, and voids of
greater volume are therefore necessary for relieving stress.
However, the occurrence of voids having large volume in the
via-plug leads to the connection failure of the via-plug.
[0049] Regarding the results of the appraisal of stress migration,
FIG. 6 is a graph showing the dependence of the stress migration
failure rate upon the interconnection width of the upper-metal. The
horizontal axis shows the interconnection width of the upper-metal,
and the vertical axis shows the stress migration failure rate
(hereinbelow referred to as simply the "failure rate"). The value
of the failure rate for Sample A is plotted by blank triangles,
while the failure rate for Sample B is plotted using solid
dots.
[0050] As shown in FIG. 6, the failure rate was 0 for Sample A
despite increase of the interconnection width of the upper-metal
from 0.2 .mu.m to 10 .mu.m. In contrast, failures occurred in
Sample B when the interconnection width of the upper-metal became
greater than 1 .mu.m, and the failure rate continued to increase as
the interconnection width increased. Based on the reasons described
hereinabove, it is believed that when the interconnection width of
the upper-metal exceeded 1 .mu.m in Sample B, voids occurred that
promoted breaks in the connections of the via-plug.
[0051] Based on the results shown in FIG. 6, it can be seen that
the stress migration characteristic of Sample A is far superior to
that of Sample B. As the reason for this difference, points that
would cause concentrations of stress do not occur in Sample A
because the plug sidewall angle never becomes a negative angle,
while protuberances are formed in Sample B at points in which the
plug sidewall angle becomes a negative angle.
[0052] The following explanation regards a method of fabricating
the semiconductor device that is shown in FIG. 2A. The explanation
here regards a dual damascene method in which via-plug 130 and
interconnection 140 are formed as a single unit.
[0053] FIGS. 7A to 7N are sectional views showing the fabrication
method of the semiconductor device of the present invention.
Semiconductor elements such as transistors and resistors are formed
on a semiconductor substrate that is not shown in the figure, but
because the configuration of the semiconductor elements is similar
to that of the prior art, explanation of the method of forming
these elements is here omitted.
[0054] As shown in FIG. 7A, after forming the above-described
semiconductor elements, a silicon oxide film is formed as lower
dielectric film 110 having a film thickness of 400-700 nm by a
plasma CVD (Chemical Vapor Deposition) method.
[0055] Next, Stopper-SiC film 150 having a thickness of 50-70 nm is
formed, an L-Ox film having a thickness of 400-700 nm is formed as
intralayer dielectric film 112, and a resist film is then applied
over these films. Trench openings are next formed in the resist
film by means of a known lithographic process. The resist film is
used as a mask to remove Stopper-SiC film 150 and intralayer
dielectric film 112, following which the resist film is
removed.
[0056] After forming a barrier metal film 122 (FIG. 7B), a copper
seed layer is formed, following which copper 124 is formed on the
copper seed layer by means of an electroplating method (FIG.
7C).
[0057] As shown in FIG. 7D, copper 124 is next polished by means of
a CMP (Chemical and Mechanical Polishing) method until the upper
surface of intralayer dielectric film 112 is exposed, whereby
interconnection 120 is formed.
[0058] Next, as shown in FIG. 7E, Cap-SiCN film 152 is formed to a
thickness of 50-70 nm, and a silicon oxide film is formed to a
thickness of 400-700 nm as interlayer dielectric film 114.
Stopper-SiC film 154 is then formed to a film thickness of 50-70
nm, and an L-Ox film is formed to a film thickness of 400-700 nm as
intralayer dielectric film 116.
[0059] Interlayer dielectric film 114, Stopper-SiC film 154, and
intralayer dielectric film 116 are next removed by a known
lithographic process and etching process until prescribed positions
of the upper surface of Cap-SiCN film 152 are exposed as shown in
FIG. 7F, whereby opening 134 for forming the via-hole is
formed.
[0060] Next, anti-reflective coating (hereinbelow abbreviated as
"ARC") 160 is applied in order that the resist film will not be
exposed to light reflected by interconnection 120 in the subsequent
lithography process (FIG. 7G). At this time, ARC 160 is applied
such that the position of the upper surface of ARC 160 inside
opening 134 that was shown in FIG. 7F is below the lower surface of
Stopper-SiC film 154. In the following explanation, the opening in
which ARC 160 is buried in opening 134 is referred to as opening
135. ARC 160 is an organic film in which polyvinyl phenol or
polymethyl methacrylate is added to a base resin of polyimide or
novolac.
[0061] As shown in FIG. 7H, after applying resist film 162 by means
of a known lithographic process, trench opening 148 for forming
interconnection 140 is formed in resist film 162 (FIG. 71).
[0062] Using resist film 162 as a mask, plasma etching is carried
out from trench opening 148 using a mixed gas of CF.sub.4 and Ar in
which the gas mixture ratio of CF.sub.4: Ar equals 1:5 and the
pressure is 13.3-53.2 Pa (100-400 mTorr).
[0063] By means of this plasma etching, not only is intralayer
dielectric film 116 of trench opening 148 eliminated until the
upper surface of Stopper-SiC film 154 is exposed, but the sidewalls
of interlayer dielectric film 114 of opening 135 are also removed
such that the diameter of the opening is greater at the top than at
the base of the opening (FIG. 7J). At this time, interlayer
dielectric film 114 is not etched as far as a position lower than
the upper surface of ARC 160. ARC 160 below opening 135 serves as a
protective film for preventing elimination of the via-hole
sidewalls by etching.
[0064] Next, as shown in FIG. 7K, resist film 162 and ARC 160 are
removed by performing an O.sub.2 plasma ashing process and an
organic stripping agent process. Plasma etching is next carried out
from the trench opening that has been formed in intralayer
dielectric film 116 using a mixed gas of CHF.sub.3, O.sub.2, and
Ar. This plasma etching eliminates Stopper-SiC film 154 and
Cap-SiCN film 152 that have been exposed on upper surfaces and
forms via-hole 137 and a trench opening for interconnection 140
(FIG. 7L). At this time, the plug sidewall angle for the sidewalls
of via-hole 137 at Cap-SiCN film 152 may be less than positive
900.
[0065] Barrier metal film 142 and copper seed layer are next formed
in succession, and copper 144 is embedded by an electroplating
method in via-hole 137 and in the trench opening for
interconnection 140 (FIG. 7M). At this time, the via-hole diameter
is greater toward the via-hole top than at the via-hole base, and
the step coverage of the copper seed layer and barrier metal film
142 that are formed in the via-hole is therefore excellent and the
embedding of copper 144 is improved.
[0066] Copper 144 is next polished by means of a CMP method until
the upper surface of intralayer dielectric film 116 is exposed to
form interconnection 140, following which Cap-SiCN film 156 is
formed to cover the upper surface of interconnection 140 (FIG. 7N).
The semiconductor device shown in FIG. 2A is thus completed. After
forming the structure shown in FIG. 2A, an interlayer dielectric
film may also be additionally formed to form an interconnection on
the upper layer.
[0067] The above-described fabrication method produces a shape in
which the sidewalls of the via-hole drop monotonously from the
via-hole top toward the via-hole base, and as a result, a shape is
not produced in which the sidewall angles upward from a horizontal
direction at midpoints of the sidewalls that drop toward the
via-hole base. Further, the inclination of the sidewalls changes
such that the via-hole diameter increases with progress along the
via-hole sidewall from the via-hole base toward the via-hole
top.
[0068] The smoother via-hole sidewalls, and moreover, smaller
essential aspect ratio of the via-hole in the semiconductor device
of the above-described working example brings about an improvement
in the step coverage when forming the barrier metal film, resulting
in excellent embedding of copper and the production of a via-plug
and interconnection in which voids do not occur. It is further
believed that this type of configuration tends to eliminate
concentrations of stress inside the via-plug and can thus eliminate
the starting points of void nucleation. Interconnections can thus
be obtained that feature reduced stress migration in the via-plugs
and high reliability. In particular, the suppression of
concentrations of stress eliminates the occurrence of stress
migration failures even when stress increases as a result of the
increased width of interconnection 140. Still further, by making
the plug sidewall angle .alpha. positive angle for any points of
the via-plug sidewalls, the sidewall shape from the via-plug base
to the via-plug top is formed for all of the via-plug sidewalls. As
a result, the formation of shapes that would lead to the occurrence
of stress concentration is prevented on all of the via-plug
sidewalls.
[0069] Still further, making the plug sidewall angle at the point
of Cap-SiCN film 152 that is shown in FIG. 2A less than 90.degree.
provides a still greater improvement in the embedding of metal in
the via-hole interior and allows better prevention of the
occurrence of voids.
[0070] Regarding the etching process that was shown in FIG. 7J,
although a case was shown in which a mixed gas of CF.sub.4 and Ar
was used as the etching gas such that the etching rate of ARC 160
was greater than that of interlayer dielectric film 114, a mixed
gas of C.sub.4F.sub.8 and Ar may also be used such that the etching
rate of ARC 160 is less than that of interlayer dielectric film
114. C.sub.2F.sub.6 gas may also be used in place of CF.sub.4.
SECOND WORKING EXAMPLE
[0071] The present working example is a semiconductor device that
is provided with a via-plug in which only a portion of the via-plug
has the sidewall shape of the via-plug in the first working
example.
[0072] The following explanation regards the semiconductor device
of the present working example. Identical reference numerals are
applied to components that are identical to those of the first
working example and detailed explanation of such components is here
omitted. In addition, the fabrication for this working example is
identical to that of the first working example and explanation of
this method is therefore here omitted.
[0073] As shown in FIG. 8A, the semiconductor device of this
working example is a configuration that includes: interconnection
120; via-plug 136 that is connected to interconnection 120; and
interconnection 146 that is formed as a single unit with via-plug
136. Regarding the sectional shape of the via-plug sidewall that is
shown in FIG. 8A, the left side of the figure is the same shape as
in the first working example, but on the right side of the figure,
the plug sidewall angle is uniform from the upper surface of
interconnection 146 to the base of the via-plug. The plug sidewall
angle of the sidewall on the right side of the figure may be within
the range over 0.degree. to a positive 900.
[0074] FIG. 8B is a plan view showing the pattern of
interconnection 146 and via-plug 136. Point 500 in FIG. 8B shows
the via-plug top and point 520 shows the via-plug base. As shown in
FIG. 8B, the pattern of interconnection 146 extends to the left of
the figure from via-plug 136. As a result, the via-plug sidewall
shape such as the shape shown in the first working example is not
formed on the right-side portion of the sidewalls.
[0075] If the same shape as in the first working example is
provided in the via-plug sidewalls at least from the via-plug top
to the via-plug base as in the present working example, the same
effects can be obtained as were obtained in the first working
example.
[0076] Although the metal copper was used as the material of the
above-described interconnections and via-plug in the
above-described first working example and second working example,
the metal may be an alloy that contains copper, or may be another
metal such as aluminum or tungsten.
[0077] Further, although L-Ox film was used in intralayer
dielectric films 112 and 116 as a low-dielectric-constant
dielectric film having a lower dielectric constant than a silicon
oxide film, the present invention is not limited to the use of L-Ox
film. The low-dielectric-constant dielectric film may be an
inorganic dielectric film such as either a SiOF film or a silicon
oxide film containing carbon (SiOC film). Alternatively, the
low-dielectric-constant dielectric film may be an organic
dielectric film such as either a silicon oxide film containing a
methyl group or a high-polymer film. Still further, intralayer
dielectric films 112 and 116 may also be laminated films that
include these low-dielectric-constant dielectric films. Although a
case was shown in which interlayer dielectric film 114 was a
silicon oxide film, interlayer dielectric film 114 may be a film
that contains a low-dielectric-constant dielectric film. The use of
a low-dielectric-constant dielectric film in intralayer dielectric
films 112 and 116 and interlayer dielectric film 114 reduces the
capacitance between interconnections.
[0078] Further, the etching stopper film is not limited to a SiC
film and may be a SiCN film or a silicon nitride film having high
etching selectivity with intralayer dielectric films. Still
further, the metal diffusion prevention film is not limited to a
SiCN film, and may also be a dielectric film such as a SiC film or
a silicon nitride film that serves the purpose of preventing
diffusion of metal.
[0079] While preferred embodiments of the present invention have
been described using specific terms, such description is for
illustrative purposes only, and it is to be understood that changes
and variations may be made without departing from the spirit or
scope of the following claims.
* * * * *