U.S. patent application number 10/452027 was filed with the patent office on 2004-12-02 for array of integrated circuit units with strapping lines to prevent punch through.
Invention is credited to Hu, Yaw Wen, Lee, Dana.
Application Number | 20040238852 10/452027 |
Document ID | / |
Family ID | 33434899 |
Filed Date | 2004-12-02 |
United States Patent
Application |
20040238852 |
Kind Code |
A1 |
Lee, Dana ; et al. |
December 2, 2004 |
ARRAY OF INTEGRATED CIRCUIT UNITS WITH STRAPPING LINES TO PREVENT
PUNCH THROUGH
Abstract
An array of non-volatile memory cells is arranged in a plurality
of rows and columns where each cell has a first region and a second
region spaced apart from one another with a channel region
therebetween for the conduction of charges between the first region
and the second region. A first plurality of row lines electrically
connect the second region of cells in the same row. A plurality of
column lines electrically connect the first region of cells in the
same column. A plurality of strap lines connect certain of the row
lines with each strap line electrically connecting a second
plurality of row lines not immediately adjacent to one another,
wherein row lines connected to a first strap line are interleaved
with row lines connected to a second strap line.
Inventors: |
Lee, Dana; (Santa Clara,
CA) ; Hu, Yaw Wen; (Cupertino, CA) |
Correspondence
Address: |
GRAY CARY WARE & FREIDENRICH LLP
2000 UNIVERSITY AVENUE
E. PALO ALTO
CA
94303-2248
US
|
Family ID: |
33434899 |
Appl. No.: |
10/452027 |
Filed: |
May 30, 2003 |
Current U.S.
Class: |
257/204 ;
257/202; 257/315; 257/E21.209; 257/E21.422; 257/E21.692;
257/E21.693; 257/E27.081; 257/E27.103; 257/E29.306 |
Current CPC
Class: |
H01L 29/40114 20190801;
H01L 27/11556 20130101; H01L 27/11553 20130101; G11C 5/063
20130101; H01L 29/42336 20130101; H01L 29/7885 20130101; H01L
27/105 20130101; H01L 27/115 20130101; H01L 29/66825 20130101; G11C
16/0425 20130101 |
Class at
Publication: |
257/204 ;
257/202; 257/315 |
International
Class: |
H01L 027/10 |
Claims
1. An array of integrated circuit units comprising: a plurality of
integrated circuit units arranged in a plurality of rows and
columns, wherein each unit having a first region and a second
region spaced apart from one another with a channel region
therebetween for the conduction of charges between said first
region and said second region, wherein a select cell has a voltage
supplied to its second region; a first plurality of row lines
electrically connecting the second region of units in the same row;
a plurality of column lines electrically connecting the first
region of units in the same column; and a plurality of strap lines,
each strap line electrically connecting a second plurality of row
lines, not immediately adjacent to one another, wherein row lines
strapped together by a first strap line are interleaved with row
lines strapped together by a second strap line.
2. The array of claim 1 wherein said plurality of soap lines are
arranged in a column direction substantially parallel to said
plurality of column lines.
3. The array of claim 2 wherein said integrated circuit unit is a
non-volatile memory cell.
4. The array of claim 3 wherein each of said non-volatile memory
cell is a stack gate cell.
5. The array of claim 3 wherein each of said non-volatile memory
cell is a split gate cell.
6. The array of claim 5 wherein each of said non-volatile memory
cells comprises: a control gate: a floating gate: said channel
region having a first portion and a second portion with said
floating gate spaced apart and insulated from said first portion,
and said control gate spaced apart and insulated from said second
portion; wherein said cell programs by the mechanism of hot
electron injection, and erases by the mechanism of Fowler-Nordheim
tunneling from said floating gate to said control gate.
7. The array of claim 6 wherein said channel region is
substantially co-planar.
8. The array of claim 6 wherein said channel region has a first
portion which is substantially horizontal and a second portion
which is substantially vertical.
9. The array of claim 3 wherein said plurality of row lines are
grouped in a plurality of sectors, with a sector line for each
sector.
10. The array of claim 9 wherein each sector line is connected to a
strap line.
11. A method of preventing punch through in a plurality of
integrated circuit units arranged in a plurality of rows and
columns wherein each unit has a first region and a second region
spaced apart from one another with a channel region therebetween
for the conduction of charges between said first region and said
second region, wherein units in the same row have a row line
electrically connecting the second region of the units in the same
row, and wherein units in the same column have a column line
electrically connecting the first region of the units in the same
column; said method comprising: electrically connecting a first
plurality of row lines together wherein said row lines are not
immediately adjacent to one another; and electrically connecting
together a second plurality of row lines, different from said first
plurality of row lines, wherein said second plurality of row lines
are not immediately adjacent to one another, and wherein said
second plurality of row lines are interleaved with said first
plurality of row lines.
12. An array of electrically programmable and erasable memory
devices comprising: a substrate of semiconductor material having a
first conductivity type and a surface; spaced apart isolation
regions formed on the substrate which are substantially parallel to
one another and extend in a first direction, with an active region
between each pair of adjacent isolation regions; and each of the
active regions including a plurality of pairs of memory cells,
wherein each of the memory cell pairs comprises: a trench formed
into the surface of the substrate and including a pair of opposing
sidewalls, a first region formed in the substrate underneath the
trench, a pair of second regions formed in the substrate, with a
pair of channel regions each formed in the substrate between the
first region and one of the second regions, wherein the first and
second regions have a second conductivity type, and wherein each of
the channel regions includes a first portion that extends
substantially along one of the opposing trench sidewalls and a
second portion that extends substantially along the substrate
surface, a pair of electrically conductive floating gates each
having at least a lower portion thereof disposed in the trench
adjacent to and insulated from one of the channel region first
portions for controlling a conductivity of the one channel region
first portion, a pair of electrically conductive control gates each
disposed over and insulated from one of the channel region second
portions for controlling a conductivity of the one channel region
second portion, wherein there is at most only a partial vertical
overlap between the control gates and the floating gates; said
cells arranged in a plurality of rows and columns; said first
region of each cell in the same row is connected by a row line in a
second direction substantially perpendicular to said first
direction; a plurality of strap lines, each strap line electrically
connecting a plurality of row lines not immediately adjacent to one
another, wherein row lines strapped together by a first strap line
are interleaved with row lines strapped together by a second strap
line.
13. The array of claim 12, wherein each of the memory cell pairs
further comprises: a block of conductive material having at least a
lower portion thereof disposed in the trench adjacent to and
insulated from the pair of floating gates.
14. The array of claim 13, wherein each of the conductive material
blocks is electrically connected to one of the first regions.
15. The array of claim 13, wherein each of the control gates is
disposed adjacent to one of the floating gates and insulated
therefrom with insulation material having a thickness that permits
Fowler-Nordheim tunneling.
16. The array of claim 13, wherein each of the memory cell pairs
further comprises: a pair of spacers of insulating material each
disposed between the block of conductive material and one of the
control gates, and over one of the floating gates.
17. The array of claim 12, wherein: each of the floating gates
includes an upper portion that extends above the substrate surface;
each of the control gates has a first portion that is disposed
laterally adjacent to and insulated from one of the floating gate
upper portions; and each of the control gates has a second portion
that is disposed over and insulated from one of the floating gate
tipper portions.
18. The array of claim 17, wherein: each of the control gates
includes a notch formed by the first and second portions thereof;
and each of the floating gate upper portions includes an edge that
faces one of the notches.
19. The array of claim 18, wherein each of the control gates is a
spacer of conductive material.
20. The array of claim 12, wherein each of the floating gates is a
spacer of conductive material.
21. The array of claim 12, wherein first and second portions for
each of the channel regions are non-linear with respect to each
other, with each of the channel region second portions extending in
a direction directly toward one of the floating gates to define a
path for programming the one floating gate.
22. The array of claim 12, further comprising: a plurality of
conductive control lines of conductive material each extending
across the active and isolation regions in a second direction
perpendicular to the first direction and each electrically
connecting together one of the control gates from each of the
active regions.
23. The array of claim 14, further comprising: a plurality of
conductive source lines of conductive material each extending
across the active and isolation regions in a second direction
perpendicular to the first direction and each electrically
connecting together one of the conductive blocks from each of the
active regions.
24-36. (Canceled)
Description
TECHNICAL FIELD
[0001] The present invention relates to an array of semiconductor
integrated circuit units, and more particularly floating gate
memory cells, with strapping lines, to strap row lines with a high
voltage applied thereto to reduce the affect of punch through.
BACKGROUND OF THE INVENTION
[0002] Non-volatile semiconductor memory cells using a floating
gate to store charges thereon and memory arrays of such
non-volatile memory cells formed in a semiconductor substrate are
well known in the art. Typically, such floating gate memory cells
have been of the split gate type, or stacked gate type.
[0003] In either floating gate memory cells of the split gate type
or stacked gate type, the memory cell has a first region and a
second region spaced apart from one another with a channel region
therebetween for the conduction of charges. A floating gate stores
the charges thereon to control the conduction of charges in the
channel region. Finally, a control gate controls the conduction
charges in the channel region either directly, in the split gate
type, or indirectly, in the stacked gate type.
[0004] In the prior art, an array of such non-volatile memory cells
are arranged in a plurality of rows and columns with memory cells
in the same row having their second region connected together and
memory cells in the same column having their first region connected
together. In addition, typically, the memory cells in the same row
have their control gate connected together. Row decoders and column
decoders, which are well known in the art, are also provided to
decode addresses and to select a memory cell defined by the
intersection of a selected column line and a selected control gate
line. Typically, however, in the prior art, either all of the
second regions of all the memory cells are connected together, or a
plurality of immediately adjacent rows of memory cells have their
second regions connected together to define a sector. A sector
select line then connects to each of the sectors and appropriate
sector address decoders are provided to activate particular
sectors. Referring to FIG. 10A there is shown a schematic circuit
diagram of the prior art in which four sectors are shown with each
sector having four rows of memory cells having their second regions
connected together. A sector line is connected to each of the four
sectors and when a sector line is activated, all of the second
region of memory cells in that sector receive a voltage supplied on
the sector line.
[0005] Referring to FIG. 10B, there is shown in greater detail the
schematic diagram of an array of non-volatile memory cells of the
prior art. Each of the memory cells is of the type shown and
disclosed in U.S. Pat. No. 5,029,130, which is of the split gate
type having a control gate, first region (designated as bit line
BL) and second region (designated a source line V.sub.SS). As can
be seen in FIG. 10B, the control gates of each of the rows of
memory cells, designated as WL.sub.x (or word line), are connected
singularly and not with each other. Similarly, the column lines
which are the bit lines, designated as BL.sub.x, are connected
individually to the first region of the memory cells in the same
column and not to one another. However, the source line, designated
as V.sub.SS, which is connected to the second region of the memory
cells, are connected together at least for two of the rows of
memory cells that are immediately adjacent to one another.
[0006] For the memory cell of the type disclosed in U.S. Pat. No.
5,029,130, during programming, a high voltage is supplied to the
source line while the bit line has a low voltage supplied thereto.
Thus, there creates a high voltage differential between the second
region and the first region of the selected memory cell. When a
high voltage is supplied to the second region of the selected
memory cell and a low voltage is supplied to the first region of
the selected cell, a depletion region is formed in the channel
region of the selected memory cell. To a first order effect, the
selected source line and the selected bit line of the selected
memory cell can potentially provide possible punch through between
the source line and the bit line. Thus, as shown in FIG. 10B, when
the memory cell 210 is selected, there is the possibility of punch
through effect on memory cell 212 which is in the same column as
the selected memory cell and having the same high voltage supplied
to its second region due to its source line being connected with
the source line of the selected cell 210.
[0007] If the source lines are sufficiently proximate to the
depletion regions between adjacent memory cells, the depletion
region can merge which can enhance the punch through. This is
because the lack of mobile carriers in the merged depletion region
which significantly increases the local substrate resistance. In
addition, the high voltage sets up a potential barrier between the
bit line junction and the substrate. The result of this is that
hole current generated near the bit line junction is retarded from
draining to the substrate. This is conceptually equivalent to a
base resistance in bi-polar devices or a history effect in
partially completed silicon-on-isolated devices. Both of these
effects are well known to enhance punch through. The impact of this
effect further increases if there are significant sources of
substrate current, such as that which occurs either inherently or
parasitically during certain high voltage erase and programming
operations in non-volatile memory devices.
[0008] Finally, the possibility of punch increases as the scale of
integration increases, i.e., as the size of each non-volatile
memory cell decreases.
SUMMARY OF THE INVENTION
[0009] Accordingly, in the present invention, a plurality of
integrated circuit units are arranged in a plurality of rows and
columns where each unit has a first region and a second region
spaced apart from one another with a channel region therebetween
for the conduction of charges between the first region and the
second region. During its operation, a select unit has a voltage
applied to its second region. A first plurality of row lines
electrically connects the second region of units in the same row. A
plurality of column lines electrically connects the first region of
units in the same column. Finally, a plurality of strap lines is
provided with each strap line electrically connecting a second
plurality of row lines not immediately adjacent to one another
wherein row lines strapped together by a first strap line are
interleaved with row lines strapped together by a second strap
line.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] FIG. 1A is a top view of a semiconductor substrate used in
the first step to form isolation regions.
[0011] FIG. 1B is a cross sectional view of the structure taken
along the line 1B-1B showing the initial processing steps.
[0012] FIG. 1C is a top view of the structure showing the next step
in the processing of the structure of FIG. 1B, in which isolation
regions are defined.
[0013] FIG. 1D is a cross sectional view of the structure in FIG.
1C taken along the line 1D-1D showing the isolation trenches formed
in the structure.
[0014] FIG. 1E is a cross sectional view of the structure in FIG.
1D showing the formation of isolation blocks of material in the
isolation trenches.
[0015] FIG. 1F is a cross sectional view of the structure in FIG.
1E showing the final structure of the isolation regions.
[0016] FIGS. 2A-2Q are cross sectional views of the semiconductor
structure in FIG. 1F taken along the line 2A-2A showing in sequence
the steps in the processing of the semiconductor structure in the
formation of a non-volatile memory array of floating gate memory
cells.
[0017] FIGS. 3A-3Q are cross sectional views of a periphery region
of the semiconductor structure showing in sequence the steps in the
processing of the semiconductor structure in the formation of the
non-volatile memory array of floating gate memory cells.
[0018] FIG. 4 is a top plan view of the memory cell array.
[0019] FIGS. 5A-5J are cross sectional views of the semiconductor
structure in FIG. 1F taken along the line 2A-2A showing in sequence
the steps in a first alternate processing embodiment of the
semiconductor structure.
[0020] FIGS. 6A to 6D are cross sectional views of a semiconductor
structure showing in sequence the steps in a second alternate
processing embodiment of the semiconductor structure shown in FIG.
2B.
[0021] FIGS. 7A-7D are cross sectional views of the isolation
region of the semiconductor structure showing in sequence the steps
in the second alternate processing embodiment of the structure
shown in FIG. 3B.
[0022] FIGS. 8A to 8D are cross sectional views of a semiconductor
structure showing in sequence the steps in a third alternate
processing embodiment of the semiconductor structure shown in FIG.
2B.
[0023] FIGS. 9A-9D are cross sectional views of the isolation
region of the semiconductor structure showing in sequence the steps
in the third alternate processing embodiment of the structure shown
in FIG. 3B.
[0024] FIG. 10A is a schematic circuit diagram of the
interconnection of source lines to a sector line in a non-volatile
memory cell array of the prior art.
[0025] FIG. 10B is a detailed circuit diagram of one embodiment of
the non-volatile memory array of the prior art.
[0026] FIG. 11 is a schematic circuit diagram of the connection of
the source lines in the array of non-volatile memory cells of the
present invention, wherein the connected sources lines are
interleaved with one another.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0027] Referring to FIG. 11, there is shown a schematic circuit
diagram of a non-volatile memory cell array of the present
invention. Schematically, there is shown a plurality of source
lines 220A . . . 220N, each source line connecting the second
region or the source region of a non-volatile memory cell in the
same row. The plurality of source lines 220A . . . 220N are divided
into a plurality of sectors with each sector electrically connected
to a plurality of source lines 220 that are not immediately
adjacent to one another. Thus, for example, sector line 230A is
electrically connected by a first strap line 240A which is
connected to source lines 220A, 220C, 220E and 220G. A second
sector line 230B is electrically connected by a second strap line
240B to source lines 220B, 220D, 220F and 220H. A third sector line
230C is electrically connected by a strap line 240C to source lines
220I, 220K, 220M and 2200. Finally, a fourth sector line 230D is
electrically connected to a fourth strap line 240D which
electrically connects to source lines 220J, 220L, 220N and 220P. As
a result, the source lines 220 connecting to one sector line are
interleaved with respect to the source lines 220 that are connected
to another sector line. As a result, no adjacent source lines have
high voltages applied simultaneously at any one operation.
[0028] In comparison to the array of the prior art, it should be
noted that the number of sector lines per array is the same, the
decoding is the same, and the resistance is the same, although the
present invention requires space for an extra vertical strapping
line per source contact to allow the interleave. Finally, the
amount of disturbance is the same. Although punch through due to
source junction at high voltage can still occur in the array of the
present invention, there is now no enhancement due to depletion
region merging.
[0029] As previously stated, the present invention of strapping
alternate source lines can be used with any array of non-volatile
memory cells, such as stacked gate, or split gate (such as that
disclosed in U.S. Pat. No. 5,029,130, whose disclosure is
incorporated herein by reference). Furthermore, the present
strapping invention can be used with any array of integrated
circuit units in which a voltage is applied and punch through may
result, so long s the integrated circuit units are arranged in an
array pattern consisting of rows and columns with the first regions
in the same column connected by a column line and with the second
regions in the same row connected by a row line. One preferred
non-volatile memory cell in an array to be used with the present
strapping invention is described as follows:
[0030] The method of making non-volatile memory cells that can be
used in the present invention is illustrated in FIGS. 1A to 1F and
2A to 2Q (which show the processing steps in making the memory cell
array), and FIGS. 3A-3Q (which show the processing steps in making
the periphery region(s) of the semiconductor structure). The method
begins with a semiconductor substrate 10, which is preferably of P
type and is well known in the art. The thicknesses of the layers
described below will depend upon the design rules and the process
technology generation. What is described herein is for the 0.10
micron process. However, it will be understood by those skilled in
the art that the present invention is not limited to any specific
process technology generation, nor to any specific value in any of
the process parameters described hereinafter.
[0031] Isolation Region Formation
[0032] FIGS. 1A to 1F illustrate the well known STI method of
forming isolation regions on a substrate. Referring to FIG. 1A
there is shown a top plan view of a semiconductor substrate (or a
semiconductor well), which is preferably of P type and is well
known in the art. First and second layers of material 12 and 14 are
formed (e.g. grown or deposited) on the substrate. For example,
first layer 12 can be silicon dioxide (hereinafter "oxide"), which
is formed on the substrate 10 by any well known technique such as
oxidation or oxide deposition (e.g. chemical vapor deposition or
CVD) to a thickness of approximately 50-150 .ANG.. Nitrogen doped
oxide or other insulation dielectrics can also be used. Second
layer 14 can be silicon nitride (hereinafter "nitride"), which is
formed over oxide layer 12 preferably by CVD or PECVD to a
thickness of approximately 1000-5000 .ANG.. FIG. 1B illustrates a
cross-section of the resulting structure.
[0033] Once the first and second layers 12/14 have been formed,
suitable photo resist material 16 is applied on the nitride layer
14 and a masking step is performed to selectively remove the photo
resist material from certain regions (stripes 18) that extend in
the Y or column direction, as shown in FIG. 1C. Where the
photo-resist material 16 is removed, the exposed nitride layer 14
and oxide layer 12 are etched away in stripes 18 using standard
etching techniques (i.e. anisotropic nitride and oxide/dielectric
etch processes) to form trenches 20 in the structure. The distance
W between adjacent stripes 18 can be as small as the smallest
lithographic feature of the process used. A silicon etch process is
then used to extend trenches 20 down into the silicon substrate 10
(e.g. to a depth of approximately 500 .ANG. to several microns), as
shown in FIG. 1D. Where the photo resist 16 is not removed, the
nitride layer 14 and oxide layer 12 are maintained. The resulting
structure illustrated in FIG. 1D now defines active regions 22
interlaced with isolation regions 24.
[0034] The structure is further processed to remove the remaining
photo resist 16. Then, an isolation material such as silicon
dioxide is formed in trenches 20 by depositing a thick oxide layer,
followed by a Chemical-Mechanical-Polishing or CMP etch (using
nitride layer 14 as an etch stop) to remove the oxide layer except
for oxide blocks 26 in trenches 20, as shown in FIG. 1E. The
remaining nitride and oxide layers 14/12 are then removed using
nitride/oxide etch processes, leaving STI oxide blocks 26 extending
along isolation regions 24, as shown in FIG. 1F.
[0035] The STI isolation method described above is the preferred
method of forming isolation regions 24. However, the well known
LOCOS isolation method (e.g. recessed LOCOS, poly buffered LOCOS,
etc.) could alternately be used, where the trenches 20 may not
extend into the substrate, and isolation material may be formed on
the substrate surface in stripe regions 18. FIGS. 1A to 1F
illustrate the memory cell array region of the substrate, in which
columns of memory cells will be formed in the active regions 22
which are separated by the isolation regions 24. It should be noted
that the substrate 10 also includes at least one periphery region
28 in which control circuitry is formed that will be used to
operate the memory cells formed in the memory cell array region.
Preferably, isolation blocks 26 are also formed in the periphery
region 28 during the same STI or LOCOS process described above.
[0036] Memory Cell Formation
[0037] The structure shown in FIG. 1F is further processed as
follows. FIGS. 2A to 2Q show the cross sections of the structure in
the active regions 22 from a view orthogonal to that of FIG. 1F
(along line 2A-2A as shown in FIGS. 1C and 1F), and FIGS. 3A to 3Q
show the cross sections of the structure in the periphery region(s)
28, as the next steps are performed concurrently in both
regions.
[0038] An insulation layer 30 (preferably oxide or nitrogen doped
oxide) is first formed over the substrate 10, as shown in FIGS. 2A
and 3A. The active region portions of the substrate 10 can be doped
at this time for better independent control of the cell array
portion of the memory device relative to the periphery region 28.
Such doping is often referred to as a V.sub.t implant or cell well
implant, and is well known in the art. During this implant, the
periphery region is protected by a photo resist layer, which is
deposited over the entire structure and removed from just the
memory cell array region of the substrate.
[0039] Next, a thick layer of hard mask material 32 such as nitride
is formed over oxide layer 30 (e.g. .about.3500 .ANG. thick). A
plurality of parallel second trenches 34 are formed in the nitride
layer 32 by applying a photo resist (masking) material on the
nitride layer 32, and then performing a masking step to remove the
photo resist material from selected parallel stripe regions. An
anisotropic nitride etch is used to remove the exposed portions of
nitride layer 32 in the stripe regions, leaving second trenches 34
that extend down to and expose oxide layer 30. After the photo
resist is removed, an anisotropic oxide etch is used to remove the
exposed portions of oxide layer 30 and extend second trenches 34
down to the substrate 10. A silicon anisotropic etch process is
then used to extend second trenches 34 down into the substrate 10
in each of the active regions 22 (for example, down to a depth of
approximately one feature size deep, e.g. about 500 .ANG. to
several microns with 0.15 um technology). Alternately, the photo
resist can be removed after trenches 34 are formed into the
substrate 10. The resulting active/periphery regions 22/28 are
shown in FIGS. 2B/3B.
[0040] A layer of insulation material 36 is next formed (preferably
using a thermal oxidation or CVD oxide process) along the exposed
silicon in second trenches 34 that forms the bottom and lower
sidewalls of the second trenches 34 (e.g. .about.60 .ANG. to 150
.ANG. thick). A thick layer of polysilicon 38 (hereinafter "poly")
is then formed over the structure, which fills second trenches 34.
Poly layer 38 can be doped (e.g. n+) by ion implant, or by an
in-situ doped poly process. The resulting active/periphery regions
22/28 are shown in FIGS. 2C/3C.
[0041] A poly etch process (e.g. a CMP process using nitride layer
32 as an etch stop) is used to remove poly layer 38 except for
blocks 40 of the polysilicon 38 left remaining in second trenches
34. A controlled poly etch is then used to lower the height of poly
blocks 40, where the tops of poly blocks 40 are disposed above the
surface of the substrate, but below the tops of STI blocks 26 in
the isolation regions 24, as shown in FIGS. 2D/3D.
[0042] Another optional poly etch is then performed to create
sloped portions 42 on the tops of poly blocks 40 (adjacent the
second trench sidewalls), as shown in FIG. 2E. A thermal oxidation
process is then performed to form or enhance the tips of sloped
portions 42, which oxidizes the exposed top surfaces of the poly
blocks 40 (forming oxide layer 46 thereon), as shown in FIG. 2F.
Oxide spacers 48 are then formed along the sidewalls of the second
trenches 34. Formation of spacers is well known in the art, and
involves the deposition of a material over the contour of a
structure, followed by an anisotropic etch process, whereby the
material is removed from horizontal surfaces of the structure,
while the material remains largely intact on vertically oriented
surfaces of the structure (with a rounded upper surface). Spacers
48 are formed by depositing oxide over the structure (e.g.
approximately 300 to 1000 .ANG. thickness) followed by an
anisotropic oxide etch. The oxide etch also removes the center
portion of oxide layer 46 in each of the second trenches 34. The
periphery region 28 is left unaffected. The resulting
active/periphery regions 22/28 are shown in FIGS. 2G/3G.
[0043] An anisotropic poly etch in combination with some oxide etch
(for adjustment of STI oxide height, along the trench 34) is next
performed, which removes the center portions of the poly blocks 40
that are not protected by oxide spacers 48, leaving a pair of
opposing poly blocks 40a in each of the second trenches 34, as
shown in FIG. 2H. An insulation deposition and anisotropic
etch-back process is then used to form an insulation layer 50 along
the exposed sides of poly blocks 40a inside second trenches 34. The
insulation material could be any insulation material (e.g.
ONO--oxide/nitride/oxide, or other high dielectric materials).
Preferably, the insulation material is oxide, so that the oxide
deposition/etch process also thickens the oxide spacers 48 and
results in the removal of the exposed portions of oxide layer 36 at
the bottom of each second trench 34 to expose the substrate, as
shown in FIGS. 2I/3I.
[0044] Suitable ion implantation that, depending upon if the
substrate is P or N type, may include arsenic, phosphorous, boron
and/or antimony (and possible anneal) is then made across the
surface of the structure to form first (source) regions 52 in the
exposed substrate portions at the bottom of second trenches 34. The
source regions 52 are self-aligned to the second trenches 34, and
have a second conductivity type (e.g. N type) that is different
from a first conductivity type of the substrate (e.g. P type). The
ions have no significant effect on the nitride layer 32. The
resulting active/periphery regions 22/28 are shown in FIGS.
2J/3J.
[0045] A poly deposition step, followed by a poly CMP etch (using
the nitride layer 32 as an etch stop) are used to fill second
trenches 34 with poly blocks 54, as shown in FIG. 2K. A nitride
etch follows, which removes nitride layer 32, and exposes upper
edges of the poly blocks 40a. A tunnel oxide layer 56 is next
formed on the exposed upper edges of poly blocks 40a, either by
thermal oxidation, oxide deposition, or both. This oxide formation
step also forms an oxide layer 58 on the exposed top surfaces of
poly blocks 54, as well as possibly thickening oxide layer 30 over
substrate 10. Optional V.sub.t implantation in the periphery region
28 can be performed at this time by masking off the active regions
22. The resulting active/periphery regions 22/28 are shown in FIGS.
2L/3L.
[0046] The oxide layer 30 serves as the gate oxide for both the
memory cells in the active regions, and the control circuitry in
the periphery region. For each device, the thickness of the gate
oxide dictate's its maximum operating voltage. Thus, if it is
desired that some of the control circuitry operate at a different
voltage than the memory cells or other devices of the control
circuitry, then the thickness of the gate oxide 32 can be modified
at this point in the process. In way of example but not limitation,
photo resist 60 is formed over the structure, followed by a masking
step for selectively removing portions of the photo resist in the
periphery region to expose portions of oxide layer 30. The exposed
portions of oxide layer 30 can be thinned (e.g. by using a
controlled etch) or replaced (e.g. by an oxide etch and oxide
deposition) with oxide layer 30a having the desired thickness, as
illustrated in FIGS. 2M/3M.
[0047] After removal of photo resist 60, a poly deposition step is
used to form a poly layer 62 over the structure (e.g. approximately
500-3000 .ANG. thick). Photo resist deposition and masking steps
follow to form blocks of photo resist 64 on the poly layer in the
periphery region 28, as shown in FIGS. 2N/3N. An anisotropic poly
etch is then used to remove poly layer 62 except for poly blocks 66
under photo resist blocks 64 (in periphery region 28), and poly
spacers 68 adjacent oxide spacers 48 (in active regions 22).
Suitable ion implantation (and anneal) is used to form second
(drain) regions 70 in the substrate active regions and source/drain
regions 72/74 in the substrate periphery region 28 for the devices
therein. The resulting active/periphery regions 22/28 are shown in
FIGS. 20/30.
[0048] After the photo resist blocks 64 are then removed,
insulation spacers 76 are formed by insulation material deposition
and anisotropic etch (e.g. nitride or oxide), and are disposed
against poly spacers 68, oxide spacers 48 and poly blocks 66. A
metal deposition step is then performed, to deposit a metal such as
tungsten, cobalt, titanium, nickel, platinum, or molybdenum over
the active and periphery regions 22/28. The structures are then
annealed, permitting the hot metal to flow and to seep into the
exposed top portions of poly spacers 68 and poly blocks 66 to form
a conductive layer of metalized polysilicon 78 (polycide) thereon.
The metal deposited on the remaining structure is removed by a
metal etch process. The resulting active/periphery regions 22/28
are shown in FIGS. 2P/3P.
[0049] Insulation material 80, such as BPSG or oxide, is then
formed over the entire structure. A masking step is performed to
define etching areas over the drain regions 70/74. The insulation
material 80 is selectively etched in the masked regions to create
contact openings that extend down to drain regions 70/74. The
contact openings are then filled with a conductor metal (e.g.
tungsten) to form metal contacts 82 that are electrically connected
to drain regions 70/74. Drain line contacts 84/86 (e.g. aluminum,
copper, etc.) are added to the active and periphery 22/28 regions
respectively by metal masking over the insulation material 80, to
connect together all the contacts 82 (and thus all the drain
regions 70) in each active region 22, and to connect together a
plurality of drain regions 74 in the periphery region 28. The final
active region memory cell structure is illustrated in FIG. 2Q, and
the final periphery region control circuitry structure is
illustrated in FIG. 3Q.
[0050] As shown in FIG. 2Q, the process forms pairs of memory cells
that mirror each other, with a memory cell formed on each side of
the poly block 54. For each memory cell, first and second regions
52/70 form the source and drain regions respectively (although
those skilled in the art know that source and drain can be switched
during operation). Poly block 40a constitutes the floating gate,
and poly spacer 68 constitutes the control gate. Channel regions 90
for each memory cell are defined in the surface portion of the
substrate that is in-between the source and drain 52/70. Each
channel region 90 includes two portions joined together at an
approximate right angle, with a first (vertical) portion 92
extending along the vertical wall of filled second trench 34 and a
second (horizontal) portion 94 extending between the sidewall of
filled second trench 34 and the drain region 70. Each pair of
memory cells share a common source region 52 that is disposed
underneath filled second trench 34 and is in electrical contact
with poly block 54. Similarly, each drain region 70 is shared
between adjacent memory cells from different mirror sets of memory
cells.
[0051] FIG. 4 is a top view of the resulting structure showing the
interconnection between bit lines 84 and drain regions 70, as well
as control gates 68 which are continuously formed as control (word)
lines that extend across both the active and isolation regions
22/24. The above-described process does not produce source regions
52 that extend across the isolation regions 24 (which can easily be
done by a deep implant, or by removing the STI insulation material
from the isolation region portions of second trenches 34 before ion
implantation). However, poly blocks 54 (which are in electrical
contact with source regions 52) are formed continuously across the
isolation regions to adjacent active regions, and form source lines
each of which electrically connects together all the source regions
52 for each row of paired memory cells.
[0052] The floating gates 40a are disposed in second trenches 34,
with each floating gate facing and insulated from one of the
channel region vertical portions 92, one of the source regions 52
and one of the poly blocks 54. Each floating gate 40a includes an
upper portion that extends above the substrate surface and
terminates in an edge 96 that faces and is insulated from one of
the control gates 68, thus providing a path for Fowler-Nordheim
tunneling through oxide layer 56. Poly blocks 54 each extend along
and are insulated (by oxide layer 50) from floating gates 44a, for
enhanced voltage coupling therebetween. It is important that there
is at most only a partial vertical overlap between any control gate
and any floating gate, so that excessive capacitive coupling
therebetween does not hinder the operation of the memory cell
described below. This means that if there is any vertical overlap
between the control gate and the floating gate, that the control
gate does not extend over (in the horizontal direction) enough to
completely overlap (in the vertical direction) the floating
gate.
[0053] Memory Cell Operation
[0054] The operation of the memory cells will now be described. The
operation and theory of operation of such memory cells are also
described in U.S. Pat. No. 5,572,054, whose disclosure is
incorporated herein by reference with regard to the operation and
theory of operation of a non-volatile memory cell having a floating
gate and a control gate, floating gate to control gate tunneling,
and an array of memory cells formed thereby.
[0055] To initially erase a selected memory cell in any given
active region 22, a ground potential is applied to both its source
52 and drain 70. A high-positive voltage (e.g. +7 to +15 volts) is
applied to the control gate 68. Electrons on the floating gate 40a
are induced through the Fowler-Nordheim tunneling mechanism to
tunnel from the upper end of the floating gate 40a (primarily from
edge 96), through the oxide layer 56, and onto the control gate 68,
leaving the floating gate 40a positively charged. Tunneling is
enhanced by the sharpness of edge 96. It should be noted that since
each of the control gates 68 extends across the active and
isolation regions as continuous control (word) lines, one memory
cell in each active region is `erased` at the same time.
[0056] When a selected memory cell is desired to be programmed, a
small voltage (e.g. 0.5 to 2.0 V) is applied to its drain region
70. A positive voltage level in the vicinity of the threshold
voltage of the MOS structure (on the order of approximately +0.2 to
1 volt) is applied to its control gate 68. A positive high voltage
(e.g. on the order of 5 to 12 volts) is applied to its source
region 52. Electrons generated by the drain region 70 will flow
from the drain region 70 towards the source region 52 through the
deeply depleted horizontal portion 94 of the channel region 90. As
the electrons reach the vertical portion 92 of the channel region
90, they will see the high potential of floating gate 40a (because
the floating gate 40a is strongly voltage-coupled to the positively
charged source region 52 and poly block 54). The electrons will
accelerate and become heated, with most of them being injected into
and through the insulating layer 36 and onto the floating gate 40a.
Low or ground potential is applied to the source/drain regions
52/70 and control gates 68 for memory cell rows/columns not
containing the selected memory cell. Thus, only the memory cell in
the selected row and column is programmed.
[0057] The injection of electrons onto the floating gate 40a will
continue until the reduction of the charge on the floating gate 40a
can no longer sustain a high surface potential along the vertical
channel region portion 92 to generate hot electrons. At that point,
the electrons or the negative charges in the floating gate 40a will
decrease the electron flow from the drain region 70 onto the
floating gate 40a.
[0058] Finally, to read a selected memory cell, ground potential is
applied to its source region 52. A read voltage (e.g. .about.0.5 to
2 volts) is applied to its drain region 70 and approximately 1 to 4
volts (depending upon the power supply voltage of the device) is
applied to its control gate 68. If the floating gate 40a is
positively charged (i.e. the floating gate is discharged of
electrons), then the vertical channel region portion 92 (directly
adjacent to the floating gate 40a) is turned on. When the control
gate 68 is raised to the read potential, the horizontal channel
region portion 94 (directly adjacent the control gate 68) is also
turned on. Thus, the entire channel region 90 will be turned on,
causing electrons to flow from the source region 52 to the drain
region 70. This sensed electrical current would be the "1"
state.
[0059] On the other hand, if the floating gate 40a is negatively
charged, the vertical channel region portion 92 is either weakly
turned on or is entirely shut off. Even when the control gate 68
and the drain region 70 are raised to the read potential, little or
no current will flow through vertical channel region portion 92. In
this case, either the current is very small compared to that of the
"1" state or there is no current at all. In this manner, the memory
cell is sensed to be programmed at the "0" state. Ground potential
is applied to the source/drain regions 52/70 and control gates 68
for non-selected columns and rows so only the selected memory cell
is read.
[0060] The memory cell array includes peripheral circuitry
including conventional row address decoding circuitry, column
address decoding circuitry, sense amplifier circuitry, output
buffer circuitry and input buffer circuitry, which are well known
in the art.
[0061] Thus a memory cell array with reduced size and superior
program efficiency is disclosed. Memory cell size is reduced
significantly because the source regions 52 are buried inside the
substrate 10, and are self-aligned to the second trenches 34, where
space is not wasted due to limitations in the lithography
generation, contact alignment and contact integrity. Each floating
gate 40a has a lower portion disposed in second trench 34 formed in
the substrate for receiving the tunneling electrons during the
program operation and for turning on the vertical channel region
portion 92 during the read operation. Each floating gate 40a also
has an upper portion that extends out of the second trench formed
in the substrate and terminates in an edge facing the control gate
for Fowler Nordheim tunneling thereto during the erase
operation.
[0062] Program efficiency is greatly enhanced by "aiming" the
horizontal portion 94 of the channel region 90 at the floating gate
40a. In conventional programming schemes, the electrons in the
channel region flow in a path parallel to the floating gate, where
a relatively small number of the heated electrons are injected onto
the floating gate. The estimated program efficiency (number of
electrons injected compared to total number of electrons) in such
conventional programming schemes is estimated at about 1/1000.
However, because the horizontal portion of the channel region
defines an electron path that is `aimed` directly at the floating
gate, the program efficiency is improved by 10 fold or even 100
fold, where almost all the electrons are injected onto the floating
gate.
[0063] Also, there is also an enhanced voltage coupling between
each floating gate 40a and the corresponding source region 52 via
the poly block 54 (electrically connected with the source region
52). At the same time, there is relatively low voltage coupling
between the floating gate 40a and the control gate 68. Furthermore,
having source region 52 and drain region 70 separated vertically as
well as horizontally allows easier optimization of reliability
parameters without affecting cell size.
[0064] First Alternate Embodiment
[0065] FIGS. 5A to 5J show the cross sections of the structure in
the active regions 22 for an alternate method for making the memory
cell array. This first alternate process starts with the structure
shown in FIG. 2A. For simplicity, elements in common with the first
embodiment described above are designated using the same element
numbers.
[0066] The thick nitride layer 32 (e.g. .about.1000 to 10,000 .ANG.
in thickness) is formed over oxide layer 30. Parallel second
trenches 34 are formed in the nitride layer 32 by applying a photo
resist (masking) material on the nitride layer 32, and then
performing a masking step to remove the photo resist material from
selected parallel stripe regions. An anisotropic nitride etch is
used to remove the exposed portions of nitride layer 32 in the
stripe regions, leaving second trenches 34 that extend down to and
expose oxide layer 30. After the photo resist is removed, oxide
spacers 102 are formed in second trenches 34 by an oxide deposition
step, followed by an oxide anisotropic etch step. The portions of
oxide layer 30 in the bottom center of the second trenches are also
removed during this oxide etch step, exposing the underlying
substrate 10. The resulting structure is shown in FIG. 5A.
[0067] A silicon anisotropic etch process is used to extend second
trenches 34 down into the substrate 10 in each of the active
regions 22 (for example, down to a depth of approximately 500 .ANG.
to several microns with 0.15 um technology). The width of the
second trenches 34 in substrate 10 is essentially the spacing
between the oxide spacers 102. Suitable ion implantation (and
possible anneal) is then made across the surface of the structure
to form the first (source) regions 52 in the exposed substrate
portions at the bottom of second trenches 34. The source regions 52
are self-aligned to the second trenches 34, and have a second
conductivity type (e.g. N type) that is different from a first
conductivity type of the substrate (e.g. P type). The ions have no
significant effect on the nitride layer 32. The resulting structure
is shown in FIG. 5B.
[0068] Oxide layer 100 is next formed on the exposed silicon
substrate 10 (forming the bottom and lower sidewalls of the second
trenches 34), preferably by thermal oxidation (e.g. .about.70 to
150 .ANG. thick). A thick poly layer is then formed over the
structure, which fills second trenches 34. A poly CMP etch process,
using nitride layer 32 as an etch stop, is used to remove poly
layer except for poly blocks 54 left remaining in second trenches
34. A controlled poly etch is then used to lower the height of poly
blocks 54 below the top of nitride layer 32. An optional oxide
layer 104 is then formed on the poly blocks 54 (e.g. by thermal
oxidation). A thin nitride layer 106 is then deposited over the
structure, followed by masking step and nitride etch to remove the
nitride layer 106 except for those portions over oxide layer 104
and poly blocks 54. This can be accomplished by depositing photo
resist over the structure, followed by a controlled exposure so
that only the photo resist in the second trench 34 is left covering
the deposited nitride. The resulting structure is shown in FIG.
5C.
[0069] Using the nitride layer 106 as a mask, a dry and/or wet
oxide etch is used to remove the oxide spacers 102. A thermal
oxidation process follows, which forms oxide layer 108 on exposed
side portions of poly blocks 54 and on exposed portions of the
substrate. An anisotropic oxide etch is used to removed the oxide
layer 108 just formed on the substrate. The resulting structure is
shown in FIG. 5D.
[0070] Using nitride layers 32 and 106 as masks, a silicon etch is
used to etch away the exposed silicon substrate in second trenches
34 down to a depth even with the bottoms of poly blocks 54.
Additional ion implantation (and possible anneal) is used to expand
source regions 52 underneath second trenches 34, as shown in FIG.
5E.
[0071] An insulation layer 110 is then formed on the second trench
sidewalls, preferably by CVD deposition of oxide (e.g.
.about.70-150 .ANG. thick). A thick poly layer is formed over the
structure which fills second trenches 34, followed by a CMP poly
etch (using nitride layer 32 as an etch stop) and additional poly
etch to form poly blocks 40a having tops that are below that of the
STI oxide blocks 26 in the isolation regions 24. Sloped etching or
oxidation is then used to sharpen edges 96 on the tops of poly
blocks 40a. An oxide deposition and etch back process is then used
to fill the top portions of second trenches 34 with oxide 112,
which seals poly blocks 40a and creates oxide spacers at the tops
of second trenches 34. The resulting structure is shown in FIG. 5F,
and includes three poly blocks in each second trench, surrounded
and sealed by oxide. Poly block 54 is in electrical contact with
source region 52 and disposed between the pair of poly blocks 40a
(which are insulated from source region 52).
[0072] An optional extension of poly block 54 can be performed by
removing nitride layer 106 and oxide layer 104 via controlled
nitride and oxide etches, followed by a poly deposition and poly
CMP etch back. An optional poly etch can be used to lower the new
tops of poly blocks 54 before an oxidation process is used to form
a protective oxide layer 114 over poly blocks 54, as shown in FIG.
5G. A nitride etch is next used to remove nitride layer 32. A
controlled oxide etch is then used to recess the exposed oxide by
about 10 to several hundred angstroms, followed by a thermal
oxidation process that reforms oxide layers 30 and 114 and results
in an indentation in the oxide surrounding the tops of poly blocks
40a). The resulting structure is shown in FIG. 5H.
[0073] A poly deposition and anisotropic poly etch is used to form
poly spacers 68 adjacent oxide spacers 112. Suitable ion
implantation (and anneal) is used to form second (drain) regions 70
in the substrate. Insulation spacers 76 are then formed by
insulation material deposition and anisotropic etch (e.g. nitride
or oxide), and are disposed against poly spacers 68. A metal
deposition step is then performed, to deposit a metal such as
tungsten, cobalt, titanium, nickel, platinum, or molybdenum over
the structure, which is then annealed to permit the hot metal to
flow and to seep into the exposed top portions of poly spacers 68
to form polycide 78 thereon. The remaining metal deposited on the
remaining structure is removed by a metal etch process. The
resulting structure is shown in FIG. 5I.
[0074] Insulation material 80, metal contacts 82, and drain line
contact 84 are formed as described above with respect to FIG. 2Q to
result in the final structure shown in FIG. 5J. The advantage of
this embodiment is the ease with which the solid source line poly
blocks 54 are formed, and their electrical contact with source
regions 52. Moreover, using the poly block 54 to separate the later
formed floating gate poly blocks 40a makes it easier to prevent
shorts between the floating gates.
[0075] Second Alternate Embodiment
[0076] FIGS. 6A to 6G and 7A to 7G illustrate a second alternate
method for making the memory cell array. This second alternate
process begins with the structures shown in FIGS. 2B and 3B, but
without the formation of oxide layer 30 underneath nitride layer
32, as oxide layer 30 is optional for this embodiment. After the
formation of insulation material 36 as described above with respect
to FIG. 2C, the ion implantation (and possible anneal) process is
used to form the first (source) regions 52 in the exposed substrate
portions at the bottom of second trenches 34. A thin poly layer 118
is then formed over the structures, as shown in FIGS. 6A and 7A.
Poly layer 118 can be doped (e.g. n+) by ion implant, or by an
in-situ process. The thickness of poly layer 118 is preferably
50-500 .ANG., and dictates the eventual thickness of the floating
gates for the final memory cell device.
[0077] Oxide is formed over the structure, followed by a
planarizing oxide etch (e.g. CMP etch using portions of poly layer
118 over nitride layer 32 as an etch stop) which fills second
trenches 34 with oxide blocks 120. A poly etch follows that removes
the exposed portions of poly layer 118 (i.e. those portions over
nitride layer 32). An oxide etch is next used to recess the oxide
blocks 120 down even with those portions of poly layer 118 left
disposed over the STI blocks 26 in the isolation regions 24 (e.g.
using portions of poly layer 118 in the inactive regions over STI
blocks 26 as an oxide etch stop). The resulting active/peripheral
region structures are shown in FIGS. 6B and 7B.
[0078] It should be noted that two different portions of poly layer
118, disposed at two different topography levels, are used as an
etch stop in the oxide etch, poly etch, oxide etch process just
described. Specifically, as shown in FIG. 6A, poly layer 118 has
first portions 119a formed over the nitride layer 32 outside the
trench 34. FIG. 6H is the same view of the second trench 34 as
shown in FIG. 6A, but in the isolation regions 24 instead of the
active regions 22. As shown in FIG. 6H, poly layer 118 has second
portions 119b formed over STI blocks 26. Thus, poly layer portions
119a are disposed at a higher topography level than that of poly
layer portions 119b. In order to form oxide block 120 in the active
regions, the first oxide etch is performed using poly layer
portions 119a as an etch stop to evenly fill second trenches 34 in
both the active and isolation regions 22/24. The subsequent oxide
etch uses poly layer portions 119b as an etch stop to set the
proper level of oxide block 120 in the active region and to fully
expose poly layer 118 in the isolation region 24.
[0079] A poly etch is next used to remove exposed portions of poly
layer 118 (i.e. along upper portions of second trenches 34 in the
active regions, and over STI blocks 26 in the isolation regions
24). An oxidation process follows, to form oxide blocks 122 on the
exposed end portions of poly layer 118. Dielectric spacers 124,
such as oxide, are then formed, inside second trenches 34 over
oxide blocks 122 and partially over oxide blocks 120, via oxide
deposition and etch back, as shown in FIG. 6C. Another oxide etch
is then used to remove the exposed center portion of oxide blocks
120 (between spacers 124, which are reduced in height by the oxide
etch), exposing poly layer 118 at the center of second trenches 34.
A poly etch and an oxide etch follow to remove the exposed portions
of poly layer 118 and oxide layer 36 at the bottom center of second
trenches 34, exposing portions of the substrate. The resulting
structures are shown in FIGS. 6D/7D.
[0080] Dielectric spacers 125 are next formed inside second
trenches 34 by depositing nitride (or oxide) over the structure,
followed by an anisotropic nitride etch. Second trenches 34 are
then filled with poly blocks 54 using a poly deposition and CMP
etch back process (using nitride layer 32 as an etch stop), as
shown in FIG. 6E. Nitride layer 32 is removed from the active and
isolation regions 22/24 and periphery region 28 using a nitride
etch. The tunnel oxide layer 56 is next formed on the exposed upper
edges of poly layer 118, either by thermal oxidation, oxide
deposition, or both. Since oxide layer 32 was not formed earlier in
this process, the oxide layer 56 also extends over the exposed
portions of substrate 10. This oxide formation step also forms
oxide layer 58 on the exposed top surfaces of poly blocks 54.
Optional V.sub.t implantation in the periphery region 28 can be
performed at this time by masking off the active regions 22. The
resulting active/periphery regions 22/28 are shown in FIGS.
6F/7F.
[0081] The remaining processing steps described above with respect
to FIGS. 2M through 2Q are next performed on the structures shown
in FIGS. 6F and 7F, resulting in a final active region memory cell
structure illustrated in FIG. 6G, and the final periphery region
control circuitry structure illustrated in FIG. 7G.
[0082] As shown in FIG. 6G, L-shaped poly layer 118 constitutes the
floating gate for each of the memory cells. Each floating gate 118
includes a pair of orthogonally oriented elongated portions
118a/18b joined together at their proximal ends. Floating gate
portion 118a extends along and is insulated from the substrate
sidewall of second trench 34, with an upper segment 118c extending
above the substrate surface. Floating gate portion 118b extends
along and is insulated from a bottom substrate wall of second
trench 34 (i.e. disposed over and insulated from source region 52).
The control gate spacer 68 has a first portion laterally adjacent
to and insulated from the floating gate upper segment 118c, and a
second portion disposed over and insulated from the upper segment
118c. The floating gate segment 118c has a distal end that
terminates in a thin tip portion having an edge 96 that directly
faces and is insulated from the control gate 68, thus providing a
path for Fowler-Nordheim tunneling between the floating gate 118
and the control gate 68.
[0083] The second alternate embodiment provides a memory cell array
with reduced size and superior program efficiency. Memory cell size
is reduced significantly because the source regions 52 are buried
inside the substrate 10, and are self-aligned to the trenches 34,
where space is not wasted due to limitations in the lithography
generation, contact alignment and contact integrity. Program
efficiency is greatly enhanced by "aiming" the horizontal portion
94 of the channel region 90 at the floating gate 118. The L-shaped
floating gate configuration provides many advantages. Because the
floating gate portions 118a/118b are made from a thin layer of poly
material, the upper tip thereof is narrow and enhances
Fowler-Nordheim tunneling to the control gate 68. There is no need
for extensive thermal oxidation steps to form sharp edges for
enhanced tunneling. There is also an enhanced voltage coupling
ratio between each floating gate 118 and the corresponding source
region 52 given the proximity of the horizontal floating gate
portion 118b and the source region 52 (separated only by thin oxide
layer 36). Since the upper tip of floating gate upper segment 118c
of floating gate portion 118a is not formed using an oxide process,
but instead is formed by the deposition of a thin layer of
polysilicon, more heavily doped polysilicon can be used to prevent
poly depletion problems during operation. Moreover, having source
region 52 and drain region 70 separated vertically as well as
horizontally allows easier optimization of reliability parameters
without affecting cell size.
[0084] It should be noted that for this embodiment, voltage
coupling between floating gates 118 and source regions 52 are
sufficient, so that additional voltage coupling with poly blocks
54, while favorable, is not necessary. Poly blocks 54 for this
embodiment serve mainly to electrically connect all the source
regions 52 in each row of paired memory cells together. Therefore,
poly blocks 54 can be omitted from this embodiment, so long as an
electrical contact similar to contact 82 is formed down to each
source region 52. It should also be noted that each poly block 54
needs to be insulated from the substrate as it crosses the
isolation regions, so that it does not short to the substrate. This
is accomplished by making the depth of STI blocks 26 in the
isolation regions deeper than the bottom of second trench 34, or by
ensuring the material for STI blocks 26 etches slower than the
material used to form oxide blocks 120.
[0085] Third Alternate Embodiment
[0086] FIGS. 8A to 8D and 9A to 9D illustrate a third alternate
method for making the memory cell array. This third alternate
process begins with the structures shown in FIGS. 2B and 3B. After
the formation of insulation material 36 as described above with
respect to FIG. 2C, the ion implantation (and possible anneal)
process is used to form the first (source) regions 52 in the
exposed substrate portions at the bottom of second trenches 34.
Poly spacers 126 are then formed in second trenches 34 by forming a
layer of polysilicon over the structure, followed by an anisotropic
poly etch that removes the poly layer except for the poly spacers
126, as shown in FIGS. 8A and 9A. The poly spacers preferably have
a height no greater than the STI blocks 26 in the isolation regions
24 (e.g. use STI blocks 26 in the inactive regions as an etch
stop), which ensures all the polysilicon is removed from the
isolation regions.
[0087] Oxide is formed over the structures of FIGS. 8A/9A, followed
by a planarizing oxide etch (e.g. CMP etch using nitride layer 32
as an etch stop), which fills second trenches 34 with oxide blocks
128. An oxide etch is next used to recess the oxide blocks 128 down
even with the tops of poly spacers 126 (e.g. use poly spacers 126
as an oxide etch stop). Dielectric spacers 130, such as oxide, are
then formed inside second trenches 34 and over poly spacers 126,
via oxide deposition and etch back, as shown in FIG. 8B. Another
oxide etch is then used to remove the exposed center portions of
oxide blocks 128 and oxide layer 36 (between spacers 130, which are
reduced in height by the oxide etch), exposing portions of the
substrate. The resulting structures are shown in FIGS. 8C/9C.
[0088] The remaining processing steps described above with respect
to FIGS. 2K through 2Q are next performed on the structures shown
in FIGS. 8C and 9C, resulting in a final active region memory cell
structure illustrated in FIG. 8D, and the final periphery region
control circuitry structure illustrated in FIG. 9D. In this
embodiment, poly spacers 126 constitute the floating gates, which
are insulated from the control gates 68 via oxide 56. By forming
the floating gates as spacers, the number and/or complexity of
processing steps are reduced. The floating gate spacers 126 each
terminate in a sharp edge 96 that directly faces and is insulated
from the control gate 68, thus providing a path for Fowler-Nordheim
tunneling between the floating gate 126 and the control gate
68.
[0089] It is to be understood that the present invention is not
limited to the embodiment(s) described above and illustrated
herein, but encompasses any and all variations falling within the
scope of the appended claims. For example, trenches 20/34 can end
up having any shape that extends into the substrate, not just the
elongated rectangular shape shown in the figures. Also, although
the foregoing method describes the use of appropriately doped
polysilicon as the conductive material used to form the memory
cells, it should be clear to those having ordinary skill in the art
that in the context of this disclosure and the appended claims,
"polysilicon" refers to any appropriate conductive material that
can be used to form the elements of non-volatile memory cells. In
addition, any appropriate insulator can be used in place of silicon
dioxide or silicon nitride. Moreover, any appropriate material
whose etch property differs from that of silicon dioxide (or any
insulator) and from polysilicon (or any conductor) can be used in
place of silicon nitride. Further, as is apparent from the claims,
not all method steps need be performed in the exact order
illustrated or claimed, but rather in any order that allows the
proper formation of the memory cell. Additionally, the above
described invention is shown to be formed in a substrate which is
shown to be uniformly doped, but it is well known and contemplated
by the present invention that memory cell elements can be formed in
well regions of the substrate, which are regions that are doped to
have a different conductivity type compared to other portions of
the substrate. Lastly, single layers of insulating or conductive
material could be formed as multiple layers of such materials, and
vice versa.
* * * * *