U.S. patent application number 10/473621 was filed with the patent office on 2004-11-25 for multiple power converter system using combining transformers.
Invention is credited to Gurov, Gennady G., Ledenev, Anatoli V., Porter, Robert M..
Application Number | 20040233690 10/473621 |
Document ID | / |
Family ID | 33452483 |
Filed Date | 2004-11-25 |
United States Patent
Application |
20040233690 |
Kind Code |
A1 |
Ledenev, Anatoli V. ; et
al. |
November 25, 2004 |
Multiple power converter system using combining transformers
Abstract
Methods and circuitry for combining the outputs of multiphase
power converters which greatly improves the transient response of
the power conversion system are presented in a variety of
embodiments. Transformers (e.g., 59, 60, 61, 62) may be used to
accomplish the combining function, and with properly phased and
connected windings it is possible to achieve a great reduction in
output ripple current and a simultaneous reduction in transistor
ripple current, which give the designer freedom to reduce the value
of the system output inductor (e.g., 68), improving transient
response.
Inventors: |
Ledenev, Anatoli V.; (Fort
Collins, CO) ; Porter, Robert M.; (Livermore, CO)
; Gurov, Gennady G.; (Fort Collins, CO) |
Correspondence
Address: |
SANTANGELO LAW OFFICES, P.C.
125 SOUTH HOWES, THIRD FLOOR
FORT COLLINS
CO
80521
US
|
Family ID: |
33452483 |
Appl. No.: |
10/473621 |
Filed: |
July 31, 2003 |
PCT Filed: |
August 17, 2001 |
PCT NO: |
PCT/US01/25749 |
Current U.S.
Class: |
363/133 |
Current CPC
Class: |
H02M 3/285 20130101;
H02M 3/1584 20130101; H02M 1/0074 20210501 |
Class at
Publication: |
363/133 |
International
Class: |
H02M 007/538 |
Claims
1. A method of powering electronic circuitry comprising the steps
of: providing an input voltage; a. switching said input voltage
with at least two electronic switches operating at a frequency,
each of said electronic switches having an on time, during which a
voltage across said electronic switch is substantially zero, an off
time, during which a current through said electronic switch is
substantially zero, and a transition time between said on time and
said off time which is substantially less than said on time and
said off time; b. producing switched waveforms from said at least
two electronic switches; c. combining said switched waveforms in a
network to produce an average waveform which is the algebraic mean
of said switched waveforms; and d. applying said average waveform
to a filter to produce an output voltage which is substantially
without time variation.
2. A method of powering electronic circuitry comprising the steps
of: a. providing an input voltage; b. switching said input voltage
with at least two power conversion stages each comprising at least
two electronic switches operating at a frequency, each of said
electronic switches having an on time, during which a voltage
across said electronic switch is substantially zero, an off time,
during which a current through said electronic switch is
substantially zero, and transition time between said on time and
said off time which is substantially less than said on time and
said off time, c. producing switched waveforms from said at least
two electronic switches; d. combining said switched waveforms in a
network to produce a combined current output, such that electrical
current flowing in said power conversion stages is at all times
equalized; and e. applying said combined current output to a filter
to produce an output voltage which is substantially without time
variation.
3. A multiphase power converter comprising: a. at least two power
conversion stages each comprising: at least two electronic switches
operating at a frequency, each of said electronic switches having
an on time, during which a voltage across said electronic switch is
substantially zero, an off time, during which a current through
said electronic switch is substantially zero, and a transition time
between said on time and said off time which is substantially less
than said on time and said off time, said at least two electronic
switches producing switched waveforms; b. a network of combining
elements which combine said switched waveforms into a combined
waveform which comprises the algebraic average of said switched
waveforms; and c. an output filter which converts said combined
waveform into an output voltage which is substantially without time
variation.
4. A multiphase power converter comprising: a. at least two power
conversion stages each comprising: at least two electronic switches
operating at a frequency, each of said electronic switches having
an on time, during which a voltage across said electronic switch is
substantially zero, an off time, during which the current through
said electronic switch is substantially zero, and transition time
between said on time and said off time which is substantially less
than said on time and said off time, said at least two electronic
switches producing switched waveforms; b. a network of combining
elements which combine said switched waveforms such that electrical
current flowing in said at least two power conversion stages is at
all times equalized; and c. an output filter which converts said
combined waveform into an output voltage which is substantially
without time variation.
5. A multiphase power converter as described in claims 3 or 4
wherein said at least two power conversion stages are buck
converters.
6. A multiphase power converter as described in claims 3 or 4
wherein said network of combining elements are transformers.
7. A multiphase power converter as described in claims 3 or 4
wherein said output filter comprises a series combination of an
inductor and a capacitor.
8. A multiphase power converter as described in claims 7 wherein
the ratio of a ripple voltage across said inductor to an input
voltage is smaller by a factor equal to the number of said at least
two power conversion stages.
9. A multiphase power converter as described in claims 3 or 4
wherein a ripple current in each of said power conversion stages
alternates with a period less than the sum of said on time and said
off time.
10. A multiphase power converter as described in claims 3 or 4
wherein a ripple current in each of said power conversion stages
has an amplitude smaller than a ripple current in said output
filter.
11. A method of powering a programmable processor comprising the
steps of: a. accepting at least a first buck converter power input;
b. affecting said first buck converter power input with at least
one high effective input inductance; c. creating a first
directional effect in a passive electrical element from said first
buck converter input; d. accepting at least a second buck converter
power input; e. affecting said second buck converter power input
with at least one high effective input inductance; f. creating a
second directional effect in said passive electrical element from
said second buck converter power input wherein said second
directional effect opposes said first directional effect; g.
combining said at least two power inputs to create a combined power
signal; h. creating a low effective output inductance power output
from said combined power signal; i. establishing a high current,
low voltage power output from said low effective output inductance
power output; j. providing said high current, low voltage power
output to a programmable processor; and k. at least partially
powering said programmable processor by said high current, low
voltage power output.
12. A method of powering a programmable processor as described in
claim 11 wherein said steps of affecting said at least two power
inputs with at least one high effective input inductance and
establishing a high current, low voltage power output from said low
effective output inductance power output comprises the step of
utilizing an identical network.
13. A method of powering a programmable processor as described in
claim 12 wherein said step of utilizing an identical network
comprises the step of utilizing transformer circuitry.
14. A method of powering a programmable processor as described in
claim 12 wherein said step of providing said power output to said
programmable processor comprises the step of providing a power
output selected from a group consisting of: providing a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V, providing a maximum
current of greater than about 20, 50, 100, or 200 amps, providing a
voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a
maximum current of greater than about 20, 50, 100, or 200 amps in
any combination, providing a high rate of current change, providing
a typical current change of greater than about 0.1, 1, 5, or 10
A/ns, and providing a power output where the voltage drop of the
output conductor is significant relative to the voltage
delivered.
15. A method of powering a programmable processor as described in
claim 14 wherein said step of providing said power output to said
programmable processor further comprises the step of providing
circuitry exhibiting an output inductance selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output inductance less than about 50 nH, an output
inductance less than about 20 nH, an output inductance less than
about 10 nH, an output inductance less than about 2 nH, an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
16. A method of powering a programmable processor as described in
claim 15 and further comprising the step of creating at least one
of said power inputs from a power element selected from a group
consisting of: an isolated source, an interleaved switched voltage
source, a bipolar source, an interleaved bipolar source, any
permutations or combinations of the foregoing, an isolated source
with substantially only a regulation delta filter element, an
interleaved switched voltage source with substantially only a
regulation delta filter element, a bipolar source with
substantially only a regulation delta filter element, an
interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
17. A method of powering a programmable processor as described in
claim 13 wherein said step of utilizing transformer circuitry
comprises the step of utilizing a non-air gap transformer.
18. A method of powering a programmable processor as described in
claim 13 wherein said step of utilizing transformer circuitry
comprises the step of utilizing a substantially coincident
transformer.
19. A method of powering a programmable processor as described in
claim 12 and further comprising the steps of accepting at least
three buck converter power inputs and wherein said step of
combining said at least two power inputs comprises the step of
utilizing a tiered coupling of said at least three buck converter
power inputs.
20. A method of powering a programmable processor as described in
claim 19 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs comprises the steps of:
a. establishing a first order connection network having a plurality
of first order inputs and a first order output; and b. establishing
a second order connection network having a plurality of second
order inputs and which outputs said first order inputs.
21. A method of powering a programmable processor as described in
claim 20 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs further comprises the
step of establishing a third order connection network having a
plurality of third order inputs and which outputs said second order
inputs.
22. A method of powering a programmable processor as described in
claim 21 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs further comprises the
step of establishing a fourth order connection network having a
plurality of fourth order inputs and which outputs said third order
inputs.
23. A method of powering a programmable processor as described in
claim 19 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs comprises the step of
utilizing components selected from a group consisting of:
magnetically coupled and series connected inductor elements,
magnetically coupled inductor elements, transformers, transformers
connected in part to a power input and in part to another of said
transformers, magnetically coupled and series connected inductor
elements linking multiple power inputs, unequal transformers, equal
transformers, and transformers linking multiple power inputs.
24. A method of powering a programmable processor as described in
claim 19 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs comprises the steps of:
a. connecting a first power input to a second power input by first
and second inductor elements connected at a first intermediate
series connection; b. magnetically coupling said first and second
inductor elements; c. establishing a first intermediate output from
said first intermediate series connection; d. connecting a third
power input to a fourth power input by third and fourth inductor
elements connected at a second intermediate series connection; e.
magnetically coupling said third and fourth inductor elements; f.
establishing a second intermediate output from said second
intermediate series connection; g. connecting said first
intermediate output to said second intermediate output by fifth and
sixth inductor elements connected at a third intermediate series
connection; h. magnetically coupling said fifth and sixth inductor
elements; and i. establishing said power output from said third
intermediate series connection.
25. A method of powering a programmable processor as described in
claim 19 wherein said step of utilizing a tiered coupling of said
at least three buck converter power inputs comprises the steps of:
a. connecting a first power input to a first transformer; b.
connecting a second power input to a second transformer; c.
connecting a third power input to a third transformer; d.
connecting a fourth power input to a fourth transformer; e.
connecting said first transformer to said second transformer; f.
connecting said second transformer to said third transformer; g.
connecting said third transformer to said fourth transformer; h.
connecting said fourth transformer to said first transformer; i.
connecting said first transformer to a common intermediate output;
j. connecting said second transformer to a common intermediate
output; k. connecting said third transformer to a common
intermediate output; l. connecting said fourth transformer to a
common intermediate output; m. connecting said intermediate output
to a filter element; and n. providing said power output from said
filter element.
26. A method of powering a programmable processor as described in
claim 12 or 19 and further comprising the step of driving at least
two of said buck converter power inputs by a substantially
uninterrupted sequenced conduction drive element.
27. A method of powering a programmable processor as described in
claim 26 wherein said step of driving at least two of said buck
converter power inputs by a substantially uninterrupted sequenced
conduction drive comprises the step of driving said at least two
buck converter power inputs substantially centered at a constant
conduction timing.
28. A method of powering a programmable processor as described in
claim 12 or 19 and further comprising the step of driving said at
least two buck converter power inputs by a multiphase drive
element.
29. A method of powering a programmable processor as described in
claim 26 and further comprising the step of affecting said power
output by a series inductive element after accomplishing said step
of combining said at least two power inputs to create a combined
power signal.
30. A method of powering a programmable processor as described in
claim 12, 13, 14, 15, 17, 18, or 19 wherein said step of providing
said power output to said programmable processor comprises the step
of providing said power output to an element selected from a group
consisting of: at least a portion of a computer system, a
microprocessor, a computer component, a microprocessor running at
at least hundreds of megahertz, a microprocessor running at at
least 1, 2, 5, or 10 gigahertz, memory management circuitry,
graphic display circuitry, input-output circuitry, a central
processing element, telecommunication circuitry, radar circuitry,
and vehicle power circuitry.
31. A method of powering a programmable processor as described in
claim 27 wherein said step of providing said power output to said
programmable processor comprises the step of providing said power
output to an element selected from a group consisting of: at least
a portion of a computer system, a microprocessor, a computer
component, a microprocessor running at at least hundreds of
megahertz, a microprocessor running at at least 1, 2, 5, or 10
gigahertz, memory management circuitry, graphic display circuitry,
input-output circuitry, a central processing element,
telecommunication circuitry, radar circuitry, and vehicle power
circuitry.
32. A programmable processor power supply comprising: a. at least a
first buck converter element; b. at least one high effective input
inductance to which said first buck converter element is
responsive; c. a first passive directional effect element
responsive to said first buck converter element; d. at least a
second buck converter element; e. at least one high effective input
inductance to which said second buck converter element is
responsive; f. a second passive directional effect element
responsive to said second buck converter element wherein said
second passive directional effect opposes said first directional
effect; g. a combiner network responsive to said first and said
second buck converter elements; h. a low effective output
inductance power output responsive to said combiner network; i. a
high current, low voltage power output from said low effective
output inductance power output; and j. a programmable processor
which is responsive to said high current, low voltage power
output.
33. A programmable processor power supply as described in claim 32
wherein said at least one high effective input inductance and said
low effective output inductance power output each comprise an
identical network.
34. A programmable processor power supply as described in claim 33
wherein said identical network comprises a transformer
circuitry.
35. A programmable processor power supply as described in claim 33
wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: a low voltage output of less than about 2, 1.8, 1.5,
1.3, 1.0, or 0.4V, an output having a maximum current of greater
than about 20, 50, 100, or 200 amps, an output having a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a maximum
current of greater than about 20, 50, 100, or 200 amps in any
combination, a high rate of current change output, a typical
current change of greater than about 0.1, 1, 5, or 10 A/ns output,
and a power output where the voltage drop of the output conductor
is significant relative to the voltage delivered.
36. A programmable processor power supply as described in claim 35
wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output with an inductance less than about 50 nH, an
output with an inductance less than about 20 nH, an output with an
inductance less than about 10 nH, and an output with an inductance
less than about 2 nH, and wherein said inputs are effected by
elements selected from a group consisting of: an effective input
inductance greater than about 100 nH, an effective input inductance
greater than about 200 nH, an effective input inductance greater
than about 500 nH, and an effective input inductance greater than
about 1000 nH.
37. A programmable processor power supply as described in claim 36
wherein said power inputs comprise an element selected from a group
consisting of: an isolated source, an interleaved switched voltage
source, a bipolar source, an interleaved bipolar source, any
permutations or combinations of the foregoing, an isolated source
with substantially only a regulation delta filter element, an
interleaved switched voltage source with substantially only a
regulation delta filter element, a bipolar source with
substantially only a regulation delta filter element, an
interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
38. A programmable processor power supply as described in claim 34
wherein said transformer circuitry comprises a non-air gap
transformer.
39. A programmable processor power supply as described in claim 34
wherein said transformer circuitry comprises a substantially
coincident transformer.
40. A programmable processor power supply as described in claim 33
wherein said power inputs comprise at least three power inputs and
further comprising a tiered coupling of said at least three power
inputs.
41. A programmable processor power supply as described in claim 40
wherein said tiered coupling comprises: a. a first order connection
network having a plurality of first order inputs and a first order
output; and b. a second order connection network having a plurality
of second order inputs and which outputs said first order
inputs.
42. A programmable processor power supply as described in claim 41
wherein said tiered coupling further comprises a third order
connection network having a plurality of third order inputs and
which outputs said second order inputs.
43. A programmable processor power supply as described in claim 42
wherein said tiered coupling further comprises a fourth order
connection network having a plurality of fourth order inputs and
which outputs said third order inputs.
44. A programmable processor power supply as described in claim 40
wherein said tiered coupling comprises components selected from a
group consisting of: magnetically coupled and series connected
inductor elements, magnetically coupled inductor elements,
transformers, transformers connected in part to a power input and
in part to another of said transformers, magnetically coupled and
series connected inductor elements linking multiple power inputs,
unequal transformers, equal transformers, and transformers linking
multiple power inputs.
45. A programmable processor power supply as described in claim 40
wherein said tiered coupling comprises: a. a first power input; b.
a second power input connected to said first power input by first
and second inductor elements connected at a first intermediate
series connection; c. a magnetic coupling between said first and
second inductor elements; d. a first intermediate output from said
first intermediate series connection; e. a third power input; f. a
fourth power input connected to said third power input by third and
fourth inductor elements connected at a second intermediate series
connection; g. a magnetic coupling between said third and fourth
inductor elements; h. a second intermediate output from said second
intermediate series connection; i. fifth and sixth inductor
elements connecting said first intermediate output and said second
intermediate output and connected at a third intermediate series
connection; j. a magnetically coupling between said fifth and sixth
inductor elements; and k. a power output from said third
intermediate series connection.
46. A programmable processor power supply as described in claim 40
wherein said tiered coupling comprises: a. a first power input
connected to a first transformer; b. a second power input connected
to a second transformer; c. a third power input connected to a
third transformer; d. a fourth power input connected to a fourth
transformer; e. a connection between said first transformer and
said second transformer; f. a connection between said second
transformer and said third transformer; g. a connection between
said third transformer and said fourth transformer; h. a connection
between said fourth transformer and said first transformer; i. a
connection between said first transformer and a common intermediate
output; j. a connection between said second transformer and said
common intermediate output; k. a connection between said third
transformer and said common intermediate output; l. a connection
between said fourth transformer and said common intermediate
output; m. a connection between said intermediate output to a
filter element; and n. a power output connected to said filter
element.
47. A programmable processor power supply as described in claim 33
or 40 and further comprising a substantially uninterrupted
sequenced conduction drive element to which said power inputs are
responsive.
48. A programmable processor power supply as described in claim 47
wherein said substantially uninterrupted sequenced conduction drive
element is substantially centered at a constant conduction
timing.
49. A programmable processor power supply as described in claim 33
or 40 and further comprising a multiphase drive element to which
said power inputs are responsive.
50. A programmable processor power supply as described in claim 47
and further comprising a series inductive element responsive to
said transformer circuitry and to which said programmable processor
is responsive.
51. A programmable processor power supply as described in claim 33,
34, 35, 36, 38, 39, or 40 wherein said programmable processor
comprises a programmable processor selected from a group consisting
of: at least a portion of a computer system, a microprocessor, a
computer component, a microprocessor running at at least hundreds
of megahertz, a microprocessor running at at least 1, 2, 5, or 10
gigahertz, memory management circuitry, graphic display circuitry,
input-output circuitry, a central processing element,
telecommunication circuitry, radar circuitry, and vehicle power
circuitry.
52. A programmable processor power supply as described in claim 48
wherein said programmable processor comprises a programmable
processor selected from a group consisting of: at least a portion
of a computer system, a microprocessor, a computer component, a
microprocessor running at at least hundreds of megahertz, a
microprocessor running at at least 1, 2, 5, or 10 gigahertz, memory
management circuitry, graphic display circuitry, input-output
circuitry, a central processing element, telecommunication
circuitry, radar circuitry, and vehicle power circuitry.
53. A method of powering a programmable processor comprising the
steps of: a. accepting at least two power inputs; b. affecting said
at least two power inputs with at least one high effective input
inductance; c. combining said at least two power inputs to create a
combined power signal; d. creating a low effective output
inductance power output affecting said combined power signal; e.
establishing a high current, low voltage power output affecting
said low effective output inductance power output; f. providing
said high current, low voltage power output to said programmable
processor; and g. at least partially powering said programmable
processor by said high current, low voltage power output.
54. A method of powering a programmable processor as described in
claim 53 wherein said step of establishing a high current, low
voltage power output from said low effective output inductance
power output comprises the step of utilizing only passive
elements.
55. A method of powering a programmable processor as described in
claim 53 wherein said steps of affecting said at least two power
inputs with at least one high effective input inductance and
establishing a high current, low voltage power output from said low
effective output inductance power output comprises the step of
utilizing an identical network.
56. A method of powering a programmable processor as described in
claim 55 wherein said step of utilizing an identical network
comprises the step of utilizing transformer circuitry.
57. A method of powering a programmable processor as described in
claim 56 and further comprising the step of affecting said power
output by a series inductive element after accomplishing said step
of utilizing transformer circuitry.
58. A method of powering a programmable processor as described in
claim 57 wherein said step of affecting said power output by a
series inductive element after accomplishing said step of utilizing
transformer circuitry comprises the step of affirmatively affecting
said power output by an inherent output inductance.
59. A method of powering a programmable processor comprising the
steps of: a. accepting at least a first power input; b. creating a
first directional effect in a passive electrical element from said
first power input; c. accepting at least a second power input; d.
creating a second directional effect in said passive electrical
element from said second power input wherein said second
directional effect opposes said first directional effect; e.
combining said at least two power inputs to create a high current,
low voltage power output; f. providing said high current, low
voltage power output to said programmable processor; and g. at
least partially powering said programmable processor by said high
current, low voltage power output.
60. A method of powering a programmable processor as described in
claim 59 wherein said step of combining said at least two power
inputs to create a high current, low voltage power output comprises
the step of utilizing only passive elements.
61. A method of powering a programmable processor as described in
claim 60 wherein said step of utilizing only passive elements
comprises the step of utilizing an inductive element.
62. A method of powering a programmable processor as described in
claim 59 wherein said steps of creating a first directional effect
in a passive electrical element from said first power input and
creating a second directional effect in said passive electrical
element from said second power input wherein said second
directional effect opposes said first directional effect each
comprise the step of establishing a magnetic field.
63. A method of powering a programmable processor as described in
claim 62 wherein said step of creating a second directional effect
in said passive electrical element from said second power input
wherein said second directional effect opposes said first
directional effect comprises the step of establishing a magnetic
field which has a direction opposite to that established by said
step of creating a first directional effect in a passive electrical
element from said first power input.
64. A method of powering a programmable processor as described in
claim 59 and further comprising the steps of: a. affecting said at
least two power inputs with at least one high effective input
inductance; and b. creating a low effective output inductance power
output responsive to said first and second power inputs.
65. A method of powering a programmable processor as described in
claim 61 wherein said step of utilizing an inductive element
comprises the step of utilizing transformer circuitry.
66. A method of powering a programmable processor as described in
claim 65 and further comprising the step of utilizing a series
inductor element after said transformer circuitry.
67. A method of powering a programmable processor as described in
claim 66 wherein said step of utilizing a series inductor element
comprises the step of affirmatively utilizing an inherent
inductance.
68. A method of powering a programmable processor comprising the
steps of: a. accepting at least two power inputs; b. combining said
at least two power inputs to create a high current, low voltage
power output; c. providing said high current, low voltage power
output to a programmable processor having a current draw; d. at
least partially powering said programmable processor by said high
current, low voltage power output; and e. abruptly changing said
current draw of said programmable processor while maintaining a
substantially constant voltage on said power output.
69. A method of powering a programmable processor as described in
claim 68 wherein said step of abruptly changing said current draw
of said programmable processor while maintaining a substantially
constant voltage on said power output comprises the step of
abruptly changing said current draw of said programmable processor
to a current selected from a group consisting of: greater than
about 20 amps, greater than about 50 amps, greater than about 100
amps, greater than about 200 amps, changing a current by at least
about 100% of said current draw, and changing a current by at least
about 100% of a maximum current draw.
70. A method of powering a programmable processor as described in
claim 69 wherein said step of providing said power output to said
programmable processor comprises the step of providing a power
output selected from a group consisting of: providing a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V.
71. A method of powering a programmable processor as described in
claim 68 wherein said step of abruptly changing a current draw from
said high current, low voltage power output while not substantially
changing said low voltage of said high current, low voltage power
output comprises the step of not substantially changing said low
voltage of said high current, low voltage power output by more than
a voltage change selected from a group consisting of: less than
about 20% of said low voltage power output, less than about 10% of
said low voltage power output, less than about 5% of said low
voltage power output, and less than about 2% of said low voltage
power output.
72. A method of powering a programmable processor as described in
claim 70 wherein said step of abruptly changing a current draw from
said high current, low voltage power output while not substantially
changing said low voltage of said high current, low voltage power
output comprises the step of not substantially changing said low
voltage of said high current, low voltage power output by more than
a voltage change selected from a group consisting of: less than
about 20% of said low voltage power output, less than about 10% of
said low voltage power output, less than about 5% of said low
voltage power output, and less than about 2% of said low voltage
power output.
73. A method of powering a programmable processor as described in
claim 71 wherein said step of abruptly changing a current draw from
said high current, low voltage power output while not substantially
changing said low voltage of said high current, low voltage power
output comprises the step of abruptly changing said current draw
selected from a group consisting of: a typical current change of
greater than about 0.1, 1, 5, or 10 A/ns.
74. A method of powering a programmable processor as described in
claim 72 wherein said step of abruptly changing a current draw from
said high current, low voltage power output while not substantially
changing said low voltage of said high current, low voltage power
output comprises the step of abruptly changing said current draw
selected from a group consisting of: a typical current change of
greater than about 0.1, 1, 5, or 10 A/ns.
75. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said step of providing said power
output to said programmable processor comprises the step of
providing a power output selected from a group consisting of:
providing a voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or
0.4V, providing a maximum current of greater than about 20, 50,
100, or 200 amps, providing a voltage of less than about 2, 1.8,
1.5, 1.3, 1.0, or 0.4V and a maximum current of greater than about
20, 50, 100, or 200 amps in any combination, providing a high rate
of current change, providing a typical current change of greater
than about 0.1, 1, 5, or 10 A/ns, and providing a power output
where the voltage drop of the output conductor is significant
relative to the voltage delivered.
76. A method of powering a programmable processor as described in
claim 53, 64, or 68 wherein said step of providing said power
output to said programmable processor further comprises the step of
providing circuitry exhibiting an output inductance selected from a
group consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output inductance less than about 50 nH, an output
inductance less than about 20 nH, an output inductance less than
about 10 nH, an output inductance less than about 2 nH, an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
77. A method of powering a programmable processor as described in
claim 53, 59, or 68 and further comprising the step of creating at
least one of said power inputs from a buck converter element.
78. A method of powering a programmable processor as described in
claim 77 wherein said step of creating at least one of said power
inputs from a buck converter element comprises the steps of: a.
repetitively operating a first active element; b. feeding power
through said first active element to said power input during a
first input time; c. sequentially and repetitively operating a
second active element; and d. feeding power through said second
active element to said power input during a second input time which
is different from said first input time.
79. A method of powering a programmable processor as described in
claim 77 wherein said step of creating at least one of said power
inputs from a buck converter element comprises the step of
repetitively operating active elements selected from a group
consisting of: a switch element, a diode element, a buck converter
element having two switch elements, and a buck converter element
having a switch element and a diode element.
80. A method of powering a programmable processor as described in
claim 53, 59, or 68 and further comprising the step of creating at
least one of said power inputs from a power element selected from a
group consisting of: an isolated source, an interleaved switched
voltage source, a bipolar source, at least two bipolar sources, an
interleaved bipolar source, any permutations or combinations of the
foregoing, an isolated source with substantially only a regulation
delta filter element, an interleaved switched voltage source with
substantially only a regulation delta filter element, a bipolar
source with substantially only a regulation delta filter element,
an interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
81. A method of powering a programmable processor as described in
claim 77 wherein said step of providing said power output to said
programmable processor comprises the step of providing a power
output selected from a group consisting of: providing a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V, providing a maximum
current of greater than about 20, 50, 100, or 200 amps, providing a
voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a
maximum current of greater than about 20, 50, 100, or 200 amps in
any combination, providing a high rate of current change, providing
a typical current change of greater than about 0.1, 1, 5, or 10
A/ns, and providing a power output where the voltage drop of the
output conductor is significant relative to the voltage
delivered.
82. A method of powering a programmable processor as described in
claim 81 wherein said step of providing said power output to said
programmable processor further comprises the step of providing
circuitry exhibiting an output inductance selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output inductance less than about 50 nH, an output
inductance less than about 20 nH, an output inductance less than
about 10 nH, an output inductance less than about 2 nH, an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
83. A method of powering a programmable processor as described in
claim 82 and further comprising the step of creating at least one
of said power inputs from a power element selected from a group
consisting of: an isolated source, an interleaved switched voltage
source, a bipolar source, an interleaved bipolar source, any
permutations or combinations of the foregoing, an isolated source
with substantially only a regulation delta filter element, an
interleaved switched voltage source with substantially only a
regulation delta filter element, a bipolar source with
substantially only a regulation delta filter element, an
interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
84. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said step of combining said at least
two power inputs comprises the step of magnetically coupling said
at least two power inputs.
85. A method of powering a programmable processor as described in
claim 84 wherein said step of magnetically coupling said at least
two power inputs comprises the step of affecting said at least two
power inputs by transformer circuitry.
86. A method of powering a programmable processor as described in
claim 85 wherein said step of affecting said at least two power
inputs by transformer circuitry comprises the step of affecting
said at least two power inputs by a reduced magnetic field stored
energy transformer.
87. A method of powering a programmable processor as described in
claim 85 wherein said step of affecting said at least two power
inputs by transformer circuitry comprises the step of affecting
said at least two power inputs by a non-air gap transformer.
88. A method of powering a programmable processor as described in
claim 85 wherein said step of affecting said at least two power
inputs by transformer circuitry comprises the step of affecting
said at least two power inputs by a substantially coincident
transformer.
89. A method of powering a programmable processor as described in
claim 85 wherein said step of affecting said at least two power
inputs by transformer circuitry comprises the step of affecting
said at least two power inputs by a substantially insaturable
transformer.
90. A method of powering a programmable processor as described in
claim 87 wherein said step of providing said power output to said
programmable processor comprises the step of providing a power
output selected from a group consisting of: providing a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V, providing a maximum
current of greater than about 20, 50, 100, or 200 amps, providing a
voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a
maximum current of greater than about 20, 50, 100, or 200 amps in
any combination, providing a high rate of current change, providing
a typical current change of greater than about 0.1, 1, 5, or 10
A/ns, and providing a power output where the voltage drop of the
output conductor is significant relative to the voltage
delivered.
91. A method of powering a programmable processor as described in
claim 90 wherein said step of providing said power output to said
programmable processor further comprises the step of providing
circuitry exhibiting an output inductance selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output inductance less than about 50 nH, an output
inductance less than about 20 nH, an output inductance less than
about 10 nH, an output inductance less than about 2 nH, an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
92. A method of powering a programmable processor as described in
claim 91 and further comprising the step of creating at least one
of said power inputs from a buck converter element.
93. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said step of combining said at least
two power inputs comprises the step of utilizing a reverse polarity
element.
94. A method of powering a programmable processor as described in
claim 93 wherein said step of utilizing a reverse polarity element
comprises the step of utilizing a reverse polarity transformer.
95. A method of powering a programmable processor as described in
claim 94 wherein said step of utilizing a reverse polarity
transformer comprises the steps of: a. establishing a first coil
having a positive side; b. establishing a second coil having a
negative side; c. connecting said positive side of said first coil
to said negative side of said second coil; and d. magnetically
coupling said first and second coils.
96. A method of powering a programmable processor as described in
claim 87 and further comprising the step of utilizing a reverse
polarity transformer.
97. A method of powering a programmable processor as described in
claim 88 and further comprising the step of utilizing a reverse
polarity transformer.
98. A method of powering a programmable processor as described in
claim 94 wherein said step of providing said power output to said
programmable processor comprises the step of providing a power
output selected from a group consisting of: providing a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V, providing a maximum
current of greater than about 20, 50, 100, or 200 amps, providing a
voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a
maximum current of greater than about 20, 50, 100, or 200 amps in
any combination, providing a high rate of current change, providing
a typical current change of greater than about 0.1, 1, 5, or 10
A/ns, and providing a power output where the voltage drop of the
output conductor is significant relative to the voltage
delivered.
99. A method of powering a programmable processor as described in
claim 98 wherein said step of providing said power output to said
programmable processor further comprises the step of providing
circuitry exhibiting an output inductance selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output inductance less than about 50 nH, an output
inductance less than about 20 nH, an output inductance less than
about 10 nH, an output inductance less than about 2 nH, an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
100. A method of powering a programmable processor as described in
claim 99 and further comprising the step of creating at least one
of said power inputs from a buck converter element.
101. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said step of accepting said power
inputs comprises the step of accepting at least three power inputs
and wherein said step of combining said at least two power inputs
comprises the step of utilizing a tiered coupling of said at least
three power inputs.
102. A method of powering a programmable processor as described in
claim 101 wherein said step of utilizing a tiered coupling of said
at least three power inputs comprises the steps of: a. establishing
a first order connection network having a plurality of first order
inputs and a first order output; and b. establishing a second order
connection network having a plurality of second order inputs and
which outputs said first order inputs.
103. A method of powering a programmable processor as described in
claim 102 wherein said step of utilizing a tiered coupling of said
at least three power inputs further comprises the step of
establishing a third order connection network having a plurality of
third order inputs and which outputs said second order inputs.
104. A method of powering a programmable processor as described in
claim 103 wherein said step of utilizing a tiered coupling of said
at least three power inputs further comprises the step of
establishing a fourth order connection network having a plurality
of fourth order inputs and which outputs said third order
inputs.
105. A method of powering a programmable processor as described in
claim 101 wherein said step of utilizing a tiered coupling of said
at least three power inputs comprises the step of utilizing
components selected from a group consisting of: magnetically
coupled and series connected inductor elements, magnetically
coupled inductor elements, transformers, transformers connected in
part to a power input and in part to another of said transformers,
magnetically coupled and series connected inductor elements linking
multiple power inputs, unequal transformers, equal transformers,
and transformers linking multiple power inputs.
106. A method of powering a programmable processor as described in
claim 101 wherein said step of utilizing a tiered coupling of said
at least three power inputs comprises the steps of: a. connecting a
first power input to a second power input by first and second
inductor elements connected at a first intermediate series
connection; b. magnetically coupling said first and second inductor
elements; c. establishing a first intermediate output from said
first intermediate series connection; d. connecting a third power
input to a fourth power input by third and fourth inductor elements
connected at a second intermediate series connection; e.
magnetically coupling said third and fourth inductor elements; f.
establishing a second intermediate output from said second
intermediate series connection; g. connecting said first
intermediate output to said second intermediate output by fifth and
sixth inductor elements connected at a third intermediate series
connection; h. magnetically coupling said fifth and sixth inductor
elements; and i. establishing said power output from said third
intermediate series connection.
107. A method of powering a programmable processor as described in
claim 101 wherein said step of utilizing a tiered coupling of said
at least three power inputs comprises the steps of: a. connecting a
first power input to a first transformer; b. connecting a second
power input to a second transformer; c. connecting a third power
input to a third transformer; d. connecting a fourth power input to
a fourth transformer; e. connecting said first transformer to said
second transformer; f. connecting said second transformer to said
third transformer; g. connecting said third transformer to said
fourth transformer; h. connecting said fourth transformer to said
first transformer; i. connecting said first transformer to a common
intermediate output; j. connecting said second transformer to said
common intermediate output; k. connecting said third transformer to
said common intermediate output; l. connecting said fourth
transformer to said common intermediate output; m. connecting said
intermediate output to a filter element; and n. providing said
power output from said filter element.
108. A method of powering a programmable processor as described in
claim 107 wherein said steps of: connecting said first transformer
to said second transformer, connecting said second transformer to
said third transformer, connecting said third transformer to said
fourth transformer, and connecting said fourth transformer to said
first transformer each have an input side to their respective
transformers, and wherein said steps of: connecting said first
transformer to said second transformer, said second transformer to
said third transformer, connecting said third transformer to said
fourth transformer, and connecting said fourth transformer to said
first transformer each comprise the step of utilizing said input
side to connect to the respective adjacent transformer, and wherein
said steps of: connecting said first transformer to said second
transformer, connecting said second transformer to said third
transformer, connecting said third transformer to said fourth
transformer, and connecting said fourth transformer to said first
transformer each comprise the step of utilizing a reverse polarity
transformer connection.
109. A method of powering a programmable processor as described in
claim 75 wherein said step of accepting said power inputs comprises
the step of accepting at least three power inputs and wherein said
step of combining said at least two power inputs comprises the step
of utilizing a tiered coupling of said at least three power
inputs.
110. A method of powering a programmable processor as described in
claim 77 wherein said step of accepting said power inputs comprises
the step of accepting at least three power inputs and wherein said
step of combining said at least two power inputs comprises the step
of utilizing a tiered coupling of said at least three power
inputs.
111. A method of powering a programmable processor as described in
claim 80 wherein said step of accepting said power inputs comprises
the step of accepting at least three power inputs and wherein said
step of combining said at least two power inputs comprises the step
of utilizing a tiered coupling of said at least three power
inputs.
112. A method of powering a programmable processor as described in
claim 81 wherein said step of accepting said power inputs comprises
the step of accepting at least three power inputs and wherein said
step of combining said at least two power inputs comprises the step
of utilizing a tiered coupling of said at least three power
inputs.
113. A method of powering a programmable processor as described in
claim 87 wherein said step of accepting said power inputs comprises
the step of accepting at least three power inputs and wherein said
step of combining said at least two power inputs comprises the step
of utilizing a tiered coupling of said at least three power
inputs.
114. A method of powering a programmable processor as described in
claim 53, 59, or 68 and further comprising the step of driving at
least two of said power inputs by a substantially uninterrupted
sequenced conduction drive element.
115. A method of powering a programmable processor as described in
claim 114 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
116. A method of powering a programmable processor as described in
claim 53, 59, or 68 and further comprising the step of driving said
at least two power inputs by a multiphase drive element.
117. A method of powering a programmable processor as described in
claim 75 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
118. A method of powering a programmable processor as described in
claim 117 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
119. A method of powering a programmable processor as described in
claim 75 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
120. A method of powering a programmable processor as described in
claim 76 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
121. A method of powering a programmable processor as described in
claim 120 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
122. A method of powering a programmable processor as described in
claim 76 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
123. A method of powering a programmable processor as described in
claim 77 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
124. A method of powering a programmable processor as described in
claim 123 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
125. A method of powering a programmable processor as described in
claim 77 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
126. A method of powering a programmable processor as described in
claim 81 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
127. A method of powering a programmable processor as described in
claim 126 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
128. A method of powering a programmable processor as described in
claim 81 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
129. A method of powering a programmable processor as described in
claim 87 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
130. A method of powering a programmable processor as described in
claim 129 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
131. A method of powering a programmable processor as described in
claim 87 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
132. A method of powering a programmable processor as described in
claim 93 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
133. A method of powering a programmable processor as described in
claim 132 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
134. A method of powering a programmable processor as described in
claim 93 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
135. A method of powering a programmable processor as described in
claim 101 and further comprising the step of driving at least two
of said power inputs by a substantially uninterrupted sequenced
conduction drive element.
136. A method of powering a programmable processor as described in
claim 135 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
137. A method of powering a programmable processor as described in
claim 131 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
138. A method of powering a programmable processor as described in
claim 80 and further comprising the step of driving at least two of
said power inputs by a substantially uninterrupted sequenced
conduction drive element.
139. A method of powering a programmable processor as described in
claim 138 wherein said step of driving at least two of said power
inputs by a substantially uninterrupted sequenced conduction drive
comprises the step of driving said at least two power inputs
substantially centered at a constant conduction timing.
140. A method of powering a programmable processor as described in
claim 80 and further comprising the step of driving said at least
two power inputs by a multiphase drive element.
141. A method of powering a programmable processor as described in
claim 85 and further comprising the step of affecting said power
output by a series inductive element after accomplishing said step
of affecting said at least two power inputs by transformer
circuitry.
142. A method of powering a programmable processor as described in
claim 53, 59, or 68 and further comprising the step of affecting
said power output by a series inductive element after accomplishing
said step of combining said at least two power inputs.
143. A method of powering a programmable processor as described in
claim 142 wherein said step of affecting said power output by a
series inductive element comprises the step of affecting said power
output by an uncoupled inductive element.
144. A method of powering a programmable processor as described in
claim 143 wherein said step of affecting said power output by an
uncoupled inductive element comprises the step of affirmatively
affecting said power output by an inherent output inductance.
145. A method of powering a programmable processor as described in
claim 80 and further comprising the step of affirmatively affecting
said power output by an inherent output inductance after
accomplishing said step of affecting said at least two power inputs
by transformer circuitry.
146. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said power output comprises a power
output which is the algebraic mean of said at least two power
inputs.
147. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said power output comprises a power
output which is the algebraic average of said at least two power
inputs.
148. A method of powering a programmable processor as described in
claim 53, 59, or 68 wherein said step of providing said power
output to said programmable processor comprises the step of
providing said power output to an element selected from a group
consisting of: at least a portion of a computer system, a
microprocessor, a computer component, a microprocessor running at
at least hundreds of megahertz, a microprocessor running at at
least 1, 2, 5, or 10 gigahertz, memory management circuitry,
graphic display circuitry, input-output circuitry, a central
processing element, telecommunication circuitry, radar circuitry,
and vehicle power circuitry.
149. A programmable processor power supply comprising: a. at least
two power inputs; b. at least one high effective input inductance
to which said at least two power inputs are responsive; c. a
combiner network responsive to said at least two power inputs d. a
low effective output inductance power output responsive to said
combiner network; e. a high current, low voltage power output
responsive to said low effective output inductance power output;
and f. a programmable processor power connection which is
responsive to said high current, low voltage power output.
150. A programmable processor power supply as described in claim
149 wherein said at least one high effective input inductance and
said low effective output inductance power output each are
substantially affected by only passive elements.
151. A programmable processor power supply as described in claim
149 wherein said at least one high effective input inductance and
said low effective output inductance power output each comprise an
identical network.
152. A programmable processor power supply as described in claim
151 wherein said identical network comprises transformer
circuitry.
153. A programmable processor power supply as described in claim
152 and further comprising a series inductive element responsive to
said transformer circuitry and to which said programmable processor
power connection is responsive.
154. A programmable processor power supply as described in claim
153 wherein said series inductive element responsive to said
transformer circuitry comprises an affirmatively utilized inherent
output inductance.
155. A programmable processor power supply comprising: a. at least
a first power input; b. a first passive directional effect element
responsive to said first power input; c. at least a second power
input; d. a second passive directional effect element responsive to
said second power input wherein said second passive directional
effect opposes said first directional effect; e. a combiner network
responsive to said first and said second power inputs; f. a high
current, low voltage power output; g. a programmable processor
power connection which is responsive to said high current, low
voltage power output.
156. A programmable processor power supply as described in claim
155 wherein said first passive directional effect element and said
second passive directional effect element each are substantially
affected by only passive elements.
157. A programmable processor power supply as described in claim
156 wherein said first passive directional effect element and said
second passive directional effect element comprise an inductive
element.
158. A programmable processor power supply as described in claim
155 wherein said first passive directional effect element and said
second passive directional effect element comprise a magnetic field
element.
159. A programmable processor power supply as described in claim
155 and further comprising: a. at least one high effective input
inductance to which said first and second power inputs are
responsive; and b. at least one low effective output inductance
power output responsive to said first and second power inputs.
160. A programmable processor power supply as described in claim
157 wherein said inductive element comprises transformer
circuitry.
161. A programmable processor power supply as described in claim
160 and further comprising a series inductive element responsive to
said transformer circuitry and to which said programmable processor
power connection is responsive.
162. A programmable processor power supply as described in claim
161 wherein said series inductive element responsive to said
transformer circuitry comprises an affirmatively utilized inherent
output inductance.
163. A programmable processor power supply comprising: a. at least
two power inputs; b. a combiner network responsive to said at least
two power inputs; c. a high current, low voltage, abruptly
changeable, substantially constant voltage power output responsive
to said combiner network; and d. a programmable processor
responsive to said high current, low voltage, abruptly changeable,
substantially constant power output.
164. A programmable processor power supply as described in claim
163 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output having
at least about a 20 amp maximum current, a power output having at
least about a 50 amp maximum current, a power output having at
least about a 100 amp maximum current, a power output having at
least about a 200 amp maximum current, a power output having a
current change of at least about 100% of a current draw, and a
power output having a current change of at least about 100% of a
maximum current draw.
165. A programmable processor power supply as described in claim
164 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output
outputting less than about 2 volts, a power output outputting less
than about 1.8 volts, a power output outputting less than about 1.5
volts, a power output outputting less than about 1.3 volts, a power
output outputting less than about 1.0 volts, and a power output
outputting less than about 0.4 volts.
166. A programmable processor power supply as described in claim
163 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output
preventing a changes in voltage of less than about 20% of said low
voltage output, a power output preventing a changes in voltage of
less than about 10% of said low voltage output, a power output
preventing a changes in voltage of less than about 5% of said low
voltage output, and a power output preventing a changes in voltage
of less than about 2% of said low voltage output.
167. A programmable processor power supply as described in claim
165 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output
preventing a changes in voltage of less than about 20% of said low
voltage output, a power output preventing a changes in voltage of
less than about 10% of said low voltage output, a power output
preventing a changes in voltage of less than about 5% of said low
voltage output, and a power output preventing a changes in voltage
of less than about 2% of said low voltage output.
168. A programmable processor power supply as described in claim
166 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output adapted
to provide a change in current of greater than about 0.1, 1, 5, or
10 A/ns.
169. A programmable processor power supply as described in claim
167 wherein said high current, low voltage, abruptly changeable,
substantially constant voltage power output comprises a power
output selected from a group consisting of: a power output adapted
to provide a change in current of greater than about 0.1, 1, 5, or
10 A/ns.
170. A programmable processor power supply as described in claim
149, 155, or 163 wherein said high current, low voltage power
output comprises a high current, low voltage power output selected
from a group consisting of: a low voltage output of less than about
2, 1.8, 1.5, 1.3, 1.0, or 0.4V, an output having a maximum current
of greater than about 20, 50, 100, or 200 amps, an output having a
voltage of less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a
maximum current of greater than about 20, 50, 100, or 200 amps in
any combination, a high rate of current change output, a typical
current change of greater than about 0.1, 1, 5, or 10 A/ns output,
and a power output where the voltage drop of the output conductor
is significant relative to the voltage delivered.
171. A programmable processor power supply as described in claim
149, 159, or 163 wherein said high current, low voltage power
output comprises a high current, low voltage power output selected
from a group consisting of: an output inductance less than about
{fraction (1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of
said input inductance, an output with an inductance less than about
50 nH, an output with an inductance less than about 20 nH, an
output with an inductance less than about 10 nH, an output with an
inductance less than about 2 nH, and wherein said inputs are
effected by elements selected from a group consisting of: an
effective input inductance greater than about 100 nH, an effective
input inductance greater than about 200 nH, an effective input
inductance greater than about 500 nH, and an effective input
inductance greater than about 1000 nH.
172. A programmable processor power supply as described in claim
149, 155, or 163 wherein said power inputs comprise buck converter
elements.
173. A programmable processor power supply as described in claim
172 wherein said buck converter elements comprise: a. a first
active element; b. a second active element; and c. sequential and
repetitive active element control element to which said first
active element and said second active element are sequentially
responsive.
174. A programmable processor power supply as described in claim
172 wherein said buck converter elements comprise an element
selected from a group consisting of: a switch element, a diode
element, a buck converter element having two switch elements, and a
buck converter element having a switch element and a diode
element.
175. A programmable processor power supply as described in claim
149, 155, or 163 wherein said power inputs comprise an element
selected from a group consisting of: an isolated source, an
interleaved switched voltage source, a bipolar source, an
interleaved bipolar source, any permutations or combinations of the
foregoing, an isolated source with substantially only a regulation
delta filter element, an interleaved switched voltage source with
substantially only a regulation delta filter element, a bipolar
source with substantially only a regulation delta filter element,
an interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
176. A programmable processor power supply as described in claim
172 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: a low voltage output of less than about 2, 1.8, 1.5,
1.3, 1.0, or 0.4V, an output having a maximum current of greater
than about 20, 50, 100, or 200 amps, an output having a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a maximum
current of greater than about 20, 50, 100, or 200 amps in any
combination, a high rate of current change output, a typical
current change of greater than about 0.1, 1, 5, or 10 A/ns output,
and a power output where the voltage drop of the output conductor
is significant relative to the voltage delivered.
177. A programmable processor power supply as described in claim
176 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output with an inductance less than about 50 nH, an
output with an inductance less than about 20 nH, an output with an
inductance less than about 10 nH, an output with an inductance less
than about 2 nH, and wherein said inputs are effected by elements
selected from a group consisting of: an effective input inductance
greater than about 100 nH, an effective input inductance greater
than about 200 nH, an effective input inductance greater than about
500 nH, and an effective input inductance greater than about 1000
nH.
178. A programmable processor power supply as described in claim
177 wherein said power inputs comprise an element selected from a
group consisting of: an isolated source, an interleaved switched
voltage source, a bipolar source, an interleaved bipolar source,
any permutations or combinations of the foregoing, an isolated
source with substantially only a regulation delta filter element,
an interleaved switched voltage source with substantially only a
regulation delta filter element, a bipolar source with
substantially only a regulation delta filter element, an
interleaved bipolar source with substantially only a regulation
delta filter element, an isolated source with substantially only a
parasitic element filter, an interleaved switched voltage source
with substantially only a parasitic element filter, a bipolar
source with substantially only a parasitic element filter, and an
interleaved bipolar source with substantially only a parasitic
element filter.
179. A programmable processor power supply as described in claim
149, 155, or 163 wherein said combiner network comprises a magnetic
coupling.
180. A programmable processor power supply as described in claim
179 wherein said combiner network comprises transformer
circuitry.
181. A programmable processor power supply as described in claim
180 wherein said transformer circuitry comprises a reduced magnetic
field stored energy transformer.
182. A programmable processor power supply as described in claim
180 wherein said transformer circuitry comprises a non-air gap
transformer.
183. A programmable processor power supply as described in claim
180 wherein said transformer circuitry comprises a substantially
coincident transformer.
184. A programmable processor power supply as described in claim
180 wherein said transformer circuitry comprises a substantially
insaturable transformer.
185. A programmable processor power supply as described in claim
182 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: a low voltage output of less than about 2, 1.8, 1.5,
1.3, 1.0, or 0.4V, an output having a maximum current of greater
than about 20, 50, 100, or 200 amps, an output having a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a maximum
current of greater than about 20, 50, 100, or 200 amps in any
combination, a high rate of current change output, a typical
current change of greater than about 0.1, 1, 5, or 10 A/ns output,
and a power output where the voltage drop of the output conductor
is significant relative to the voltage delivered.
186. A programmable processor power supply as described in claim
185 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output with an inductance less than about 50 nH, an
output with an inductance less than about 20 nH, an output with an
inductance less than about 10 nH, an output with an inductance less
than about 2 nH, and wherein said inputs are effected by elements
selected from a group consisting of: an effective input inductance
greater than about 100 nH, an effective input inductance greater
than about 200 nH, an effective input inductance greater than about
500 nH, and an effective input inductance greater than about 1000
nH.
187. A programmable processor power supply as described in claim
186 wherein said power inputs comprise buck converter elements.
188. A programmable processor power supply as described in claim
149, 155, or 163 wherein said combiner network comprises a reverse
polarity element.
189. A programmable processor power supply as described in claim
188 wherein said reverse polarity element comprises a reverse
polarity transformer.
190. A programmable processor power supply as described in claim
189 wherein said reverse polarity transformer comprises: a. a first
coil having a positive side; b. a second coil having a negative
side; c. a connection between said positive side of said first coil
and said negative side of said second coil; and d. a magnetic
coupling between said first and second coils.
191. A programmable processor power supply as described in claim
182 wherein said combiner network comprises a reverse polarity
transformer.
192. A programmable processor power supply as described in claim
183 wherein said combiner network comprises a reverse polarity
transformer.
193. A programmable processor power supply as described in claim
189 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: a low voltage output of less than about 2, 1.8, 1.5,
1.3, 1.0, or 0.4V, an output having a maximum current of greater
than about 20, 50, 100, or 200 amps, an output having a voltage of
less than about 2, 1.8, 1.5, 1.3, 1.0, or 0.4V and a maximum
current of greater than about 20, 50, 100, or 200 amps in any
combination, a high rate of current change output, a typical
current change of greater than about 0.1, 1, 5, or 10 A/ns output,
and a power output where the voltage drop of the output conductor
is significant relative to the voltage delivered.
194. A programmable processor power supply as described in claim
193 wherein said high current, low voltage power output comprises a
high current, low voltage power output selected from a group
consisting of: an output inductance less than about {fraction
(1/10)}, {fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, an output with an inductance less than about 50 nH, an
output with an inductance less than about 20 nH, an output with an
inductance less than about 10 nH, an output with an inductance less
than about 2 nH, and wherein said inputs are effected by elements
selected from a group consisting of: an effective input inductance
greater than about 100 nH, an effective input inductance greater
than about 200 nH, an effective input inductance greater than about
500 nH, and an effective input inductance greater than about 1000
nH.
195. A programmable processor power supply as described in claim
194 wherein said power inputs comprise buck converter elements.
196. A programmable processor power supply as described in claim
149, 155, or 163 wherein said power inputs comprise at least three
power inputs and further comprising a tiered coupling of said at
least three power inputs.
197. A programmable processor power supply as described in claim
196 wherein said tiered coupling comprises: a. a first order
connection network having a plurality of first order inputs and a
first order output; and b. a second order connection network having
a plurality of second order inputs and which outputs said first
order inputs.
198. A programmable processor power supply as described in claim
197 wherein said tiered coupling further comprises a third order
connection network having a plurality of third order inputs and
which outputs said second order inputs.
199. A programmable processor power supply as described in claim
198 wherein said tiered coupling further comprises a fourth order
connection network having a plurality of fourth order inputs and
which outputs said third order inputs.
200. A programmable processor power supply as described in claim
196 wherein said tiered coupling comprises components selected from
a group consisting of: magnetically coupled and series connected
inductor elements, magnetically coupled inductor elements,
transformers, transformers connected in part to a power input and
in part to another of said transformers, magnetically coupled and
series connected inductor elements linking multiple power inputs,
unequal transformers, equal transformers, and transformers linking
multiple power inputs.
201. A programmable processor power supply as described in claim
196 wherein said tiered coupling comprises: a. a first power input;
b. a second power input connected to said first power input by
first and second inductor elements connected at a first
intermediate series connection; c. a magnetic coupling between said
first and second inductor elements; d. a first intermediate output
from said first intermediate series connection; e. a third power
input; f. a fourth power input connected to said third power input
by third and fourth inductor elements connected at a second
intermediate series connection; g. a magnetic coupling between said
third and fourth inductor elements; h. a second intermediate output
from said second intermediate series connection; i. fifth and sixth
inductor elements connecting said first intermediate output and
said second intermediate output and connected at a third
intermediate series connection; j. a magnetically coupling between
said fifth and sixth inductor elements; and k. a power output from
said third intermediate series connection.
202. A programmable processor power supply as described in claim
196 wherein said tiered coupling comprises: a. a first power input
connected to a first transformer; b. a second power input connected
to a second transformer; c. a third power input connected to a
third transformer; d. a fourth power input connected to a fourth
transformer; e. a connection between said first transformer and
said second transformer; f. a connection between said second
transformer and said third transformer; g. a connection between
said third transformer and said fourth transformer; h. a connection
between said fourth transformer and said first transformer; i. a
connection between said first transformer and a common intermediate
output; j. a connection between said second transformer and said
common intermediate output; k. a connection between said third
transformer and said common intermediate output; l. a connection
between said fourth transformer and said common intermediate
output; m. a connection between said intermediate output to a
filter element; and n. a power output connected to said filter
element.
203. A programmable processor power supply as described in claim
202 wherein said connection between said first transformer and said
second transformer, connection between said second transformer and
said third transformer, connection between said third transformer
and said fourth transformer, and connection between said fourth
transformer and said first transformer each have an input side to
their respective transformers, and wherein said connection between
said first transformer and said second transformer, connection
between said second transformer and said third transformer,
connection between said third transformer and said fourth
transformer, and connection between said fourth transformer and
said first transformer each comprise a connection between said
input side to an adjacent transformer, and wherein said connection
between said first transformer and said second transformer,
connection between said second transformer and said third
transformer, connection between said third transformer and said
fourth transformer, and connection between said fourth transformer
and said first transformer each comprise a reverse polarity
transformer connection.
204. A programmable processor power supply as described in claim
170 wherein said power inputs comprise at least three power inputs
and further comprising a tiered coupling of said at least three
power inputs.
205. A programmable processor power supply as described in claim
172 wherein said power inputs comprise at least three power inputs
and further comprising a tiered coupling of said at least three
power inputs.
206. A programmable processor power supply as described in claim
175 wherein said power inputs comprise at least three power inputs
and further comprising a tiered coupling of said at least three
power inputs.
207. A programmable processor power supply as described in claim
176 wherein said power inputs comprise at least three power inputs
and further comprising a tiered coupling of said at least three
power inputs.
208. A programmable processor power supply as described in claim
182 wherein said power inputs comprise at least three power inputs
and further comprising a tiered coupling of said at least three
power inputs.
209. A programmable processor power supply as described in claim
149, 155, or 163 and further comprising a substantially
uninterrupted sequenced conduction drive element to which said
power inputs are responsive.
210. A programmable processor power supply as described in claim
209 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
211. A programmable processor power supply as described in claim
149, 155, or 163 and further comprising a multiphase drive element
to which said power inputs are responsive.
212. A programmable processor power supply as described in claim
170 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
213. A programmable processor power supply as described in claim
212 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
214. A programmable processor power supply as described in claim
170 and further comprising a multiphase drive element to which said
power inputs are responsive.
215. A programmable processor power supply as described in claim
171 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
216. A programmable processor power supply as described in claim
215 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
217. A programmable processor power supply as described in claim
171 and further comprising a multiphase drive element to which said
power inputs are responsive.
218. A programmable processor power supply as described in claim
172 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
219. A programmable processor power supply as described in claim
218 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
220. A programmable processor power supply as described in claim
172 and further comprising a multiphase drive element to which said
power inputs are responsive.
221. A programmable processor power supply as described in claim
176 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
222. A programmable processor power supply as described in claim
221 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
223. A programmable processor power supply as described in claim
176 and further comprising a multiphase drive element to which said
power inputs are responsive.
224. A programmable processor power supply as described in claim
182 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
225. A programmable processor power supply as described in claim
224 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
226. A programmable processor power supply as described in claim
182 and further comprising a multiphase drive element to which said
power inputs are responsive.
227. A programmable processor power supply as described in claim
188 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
228. A programmable processor power supply as described in claim
227 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
229. A programmable processor power supply as described in claim
188 and further comprising a multiphase drive element to which said
power inputs are responsive.
230. A programmable processor power supply as described in claim
196 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
231. A programmable processor power supply as described in claim
230 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
232. A programmable processor power supply as described in claim
196 and further comprising a multiphase drive element to which said
power inputs are responsive.
233. A programmable processor power supply as described in claim
175 and further comprising a substantially uninterrupted sequenced
conduction drive element to which said power inputs are
responsive.
234. A programmable processor power supply as described in claim
233 wherein said substantially uninterrupted sequenced conduction
drive element is substantially centered at a constant conduction
timing.
235. A programmable processor power supply as described in claim
175 and further comprising a multiphase drive element to which said
power inputs are responsive.
236. A programmable processor power supply as described in claim
180 and further comprising a series inductive element responsive to
said transformer circuitry and to which said programmable processor
is responsive.
237. A programmable processor power supply as described in claim
149, 155, or 163 and further comprising a series inductive element
responsive to said combiner network and to which said programmable
processor is responsive.
238. A programmable processor power supply as described in claim
237 wherein said series inductive element responsive comprises an
uncoupled inductive element.
239. A programmable processor power supply as described in claim
238 wherein said uncoupled inductive element comprises an
affirmatively utilized inherent output inductance.
240. A programmable processor power supply as described in claim
175 and further comprising an affirmatively utilized inherent
output inductance responsive to said transformer circuitry and to
which said programmable processor is responsive.
241. A programmable processor power supply as described in claim
149, 155, or 163 wherein said combiner network comprises an
algebraic mean combiner network.
242. A programmable processor power supply as described in claim
149, 155, or 163 wherein said combiner network comprises an
algebraic average combiner network.
243. A programmable processor power supply as described in claim
149, 155, or 163 wherein said programmable processor comprises a
programmable processor selected from a group consisting of: at
least a portion of a computer system, a microprocessor, a computer
component, a microprocessor running at at least hundreds of
megahertz, a microprocessor running at at least 1, 2, 5, or 10
gigahertz, memory management circuitry, graphic display circuitry,
input-output circuitry, a central processing element,
telecommunication circuitry, radar circuitry, and vehicle power
circuitry.
Description
I. TECHNICAL FIELD
[0001] The present invention generally relates to the area of
powering low voltage, high current electronics such as found in the
field of computing, and much of the following description is
presented in that context. The invention is applicable to a wide
variety of circumstances wherein a variety of power absorbing loads
may abruptly change their power absorbing characteristics (that is
to say, their impedance may undergo a rapid change). The invention
may also be applicable if such loads are separated physically such
that the voltage which may be dropped across the dynamic impedance
of the power carrying conductors is a significant fraction of the
voltage delivered to such loads. It may also be increasingly
applicable to applications wherein design tradeoffs are forcing a
steady decrease in operating voltages. Such situations may arise in
telecommunications, radar systems, vehicle power systems and the
like, as well as in computing systems.
II. BACKGROUND
[0002] The architecture of computing systems has undergone
tremendous changes in the recent past, due principally to the
advance of microcomputers from the original four-bit chips running
at hundreds of kilohertz to the most modem 32 and 64 bit
microprocessors running at hundreds of megahertz. As the chip
designers push to higher and higher speeds, problems may arise
which relate to thermal issues. That is, as the speed of a circuit
is increased, the internal logic switches each may discharge its
surrounding capacitance that much faster. Since the energy stored
in that capacitance may be considered fixed (at a given voltage),
as the speed is increased, that energy, which may be dissipated in
the switches, may be dumped into the switch that many more times
per second. Since energy per second may be defined as power, the
power lost in the switches therefore increases directly with
frequency.
[0003] On the other hand, the energy stored in a capacitance may
increase as the square of the voltage, so a capacitor charged to
two volts may store only 44% of the energy that may be stored in
that same capacitor charged to three volts. For this reason, a
microcomputer designed to operate at two volts will, when run at
the same speed, dissipate much less power than the same
microprocessor operating at three volts. There may be a tendency,
therefore, to lower the operating voltage of microprocessors.
[0004] Other considerations may cause the microprocessor to exhibit
a lower maximum speed if operated at a lower voltage as compared to
a higher operating voltage. That is, if a circuit is operating at
full speed, and the voltage on that circuit is simply reduced, the
circuit may not operate properly, and the speed of the circuit (the
"clock speed") may have to be reduced. To maintain full speed
capability and still operate at lower voltage, the circuit may have
to be redesigned to a smaller physical size. For the past few
years, these steps may have been considered the general course of
microprocessor design. Microprocessor designers, seeking the
maximum speed for their products, may expend considerable effort
evaluating any number of considerations, including:
[0005] higher speed chips and potential chip value;
[0006] higher speed chips and potential heat dissipation;
[0007] potential limitations to the removal of heat;
[0008] lower voltages and the potential reduction of heat generated
at a given speed; and
[0009] smaller devices and potential speed at a given voltage.
[0010] There may be many more important trade-off considerations
for the designers in evaluating microprocessor design.
[0011] The evaluation of microprocessor considerations may have
lead to the production of designs that operate at lower and lower
voltages. Early designs may have operated at higher voltages, such
as five volts, which have been subsequently reduced to current
designs operating at lower voltages, such as 2.0 volts. Further
reductions may occur, and future designs might be operated at 1.8,
1.5, 1.3, 1.0, and even below one volt, perhaps as low as 0.4
volts.
[0012] Meanwhile, advances in heat removal may permit processors to
run at higher and higher heat dissipation levels. Early chips may
have dissipated perhaps a watt; current designs may operate at the
50 watt level, and heat removal designs in the near future may be
able to dissipate as much as 150 watts of power generated by the
processor. Since the power dissipated may be considered
proportional to the square of the operating voltage, even as the
ability to remove heat is improved, lower operating voltages may
still be desirable.
[0013] All of this might be viewed in the context of higher speed
chips having a higher monetary value. Therefore, designers may be
driven to increase the speed, potentially driving the size of the
chips smaller, the voltages lower, and the power up. As may be
generally known, as the voltage drops the current increases for a
given power, power being defined as voltage times current. If at
the same time improvements in heat removal permit higher powers,
the current may increase still further. This may mean that the
current rises very rapidly. Early chips may have drawn small
fractions of an ampere of supply current to operate, whereas
current designs may use up to 50 amperes, and future designs may
use as much as 150 amperes or more.
[0014] As the speed of the processors increase, the dynamics of
their power supply requirements may also increase. A processor may
be drawing very little current because it is idling, and then an
event may occur (such as the arrival of a piece of key data from a
memory element or a signal from an outside event) which may cause
the processor to suddenly start rapid computation. This may produce
an abrupt change in the current drawn by the processor, which may
potentially have serious electrical consequences. It may also
require an unusually low output impedance or inductance.
[0015] As may be generally known, inductance is the measure of
energy storage in magnetic fields. Current-carrying conductors have
associated with the current a magnetic field, which represents
energy storage. As it may be generally known, the energy stored in
a magnetic field is half the volume integral of the square of the
magnetic field. Since the field may be considered linearly related
to the current in the conductor, it may be shown that the energy
stored by a current-carrying conductor is proportional to half the
square of the current, and the constant of proportionality may be
called the "inductance" of the conductor. The energy stored in the
system may be supplied by the source of electrical current, and for
a given power source there may be a limit to the rate at which
energy can be supplied, which means that the stored energy must be
built up over time. Therefore, the presence of an energy storage
mechanism may slow down a circuit, as the energy may be produced
and metered into the magnetic field at some rate before the current
can build up.
[0016] The available voltage, the inductance, and the rate of
change of current in a conductor may be related by the following
equation, well known to those skilled in the art:
V=L*.sub.--I/.sub.--t,
[0017] where L is the inductance of the conductor, and _I/_t is the
rate of change of current in the conductor.
[0018] This equation may be read to provide that the voltage
required to produce a given current in a load on a power system
increases as the time scale is reduced, and also increases as the
inductance of any connection to that load is increased. In a
corresponding fashion, as the speed of microprocessors may be
increased, the time scale may be reduced, and as the voltage may be
reduced, the equation may be read to require the inductance to be
dropped proportionally.
[0019] Often, in powering semiconductor devices, a designer may not
need to consider the inductance of the connections to the device,
but with modem high speed circuits these considerations may force
the attention to be brought to lowering the inductance of the
connections. Microprocessors may currently operate at about two
volts, and may tolerate a voltage transient on their supply lines
of about 7%, or 140 millivolts. These same microprocessors may
require that their supply current change at a rate of nearly one
ampere per nanosecond, or 10.sup.9 amperes/second. The above
equation may be read to indicate that an inductance of 140
picohenries (1.4*10.sup.-10 H) may drop a voltage of 140
millivolts. To put this number in perspective, the inductance of a
wire one inch in length in free space may be approximately 20,000
picohenries. While the inductance of a connection may be reduced by
paralleling redundant connections, to create a connection with an
inductance of 140 picohenries with conductors about a centimeter
long might require nearly 100 parallel conductors.
[0020] The foregoing discussion might provide the source of low
voltage physically close to the microprocessor, which in turn might
provide the source of low voltage to be physically small. While it
may be suggested that capacitors might be used to supply energy
during the delay interval required for the current in the
conductors to rise, the inductance of the connections to the
capacitors may be considered limiting to this approach. The
designer may be faced with placing the source of power very close
to the processor to provide adequate stability to the processor's
power source under rapid changes in current draw. This requirement
may become increasingly prevalent as the voltages drop and the
currents increase, because the former may reduce the allowable
transient size and the latter may increase the potential rate of
change of current. Both factors may reduce the permissible
inductance of the connection.
[0021] The foregoing remarks may not be limited in computers to the
actual central microprocessor. Other elements of a modem computer,
such as memory management circuits, graphic display devices, high
speed input output circuitry and other such ancillary circuitry may
have been increased in speed nearly as rapidly as the central
processing element, wherein the same considerations would
apply.
[0022] All modem electronics circuitry, including computers, may be
powered by switch-mode power conversion systems. Such a system may
generally be considered to convert incoming power from the utility
line to the voltages and currents required by the electronic
circuitry. In low power business and consumer electronics, such as
desktop personal computers, the incoming power is generally
supplied as an alternating voltage, generally 115 volts in the
United States, and 220 volts in much of the rest of the world. The
frequency of alternation may be either 50 or 60 Hertz, depending
upon location. Such utility power is generally converted to low
voltage steady (direct) current, or dc, and may be regulated to a
few percent in order to be useful as power for the electronic
circuits. A device which may perform such conversion is generally
called a "power supply". While it may possible to create a low
voltage regulated dc power source using simple transformers,
rectifiers, and linear regulators, such units may generally be
heavy, bulky and inefficient. In these applications it may be
desirable to reduce weight and size, and these approaches may be
unsuitable for this reason alone. In addition, the inefficiency of
linear regulators may also be unacceptable. Efficiency may be
defined as the ratio of output power to input power, and a low
efficiency might imply that heat is being developed in the unit
which could be transferred to the environment to keep the unit
cool. Generally, the lower the efficiency the more heat to be
transferred, therefore a possible reason for finding an alternate
approach.
[0023] For these reasons, virtually all modem electronics circuitry
is powered by switchmode conversion systems. These systems
typically operate as follows. The incoming utility power is first
converted to unregulated direct current by a rectifier. The
rectified dc is then converted to a higher frequency, typically
hundreds of kilohertz, by electronic switches. This higher
frequency power is then transformed by a suitable transformer to
the appropriate voltage level; this transformer also provides
isolation from the utility power, required for safety reasons. The
resulting isolated higher frequency power is then rectified again,
and filtered into steady direct current for use by the electronics.
Regulation of the output voltage is usually accomplished by control
of the conduction period of the electronic switches. The resulting
power conversion unit is smaller and lighter in weight than earlier
approaches because the size and weight of the transformer and
output filter are reduced proportionally to the increase in
frequency over the basic utility power frequency. All of this is
well known in the prior art.
[0024] In a complex electronic system, various voltages may be
required. For example, in a computer system the peripherals (such
as disk drives) may require +12 volts, some logic circuits may
require +5 volts, input/output circuits may additionally require -5
volts, memory interface and general logic may require 3.3 volts,
and the central microprocessor may require 2.0 volts. The central
power source (the device that is connected directly to the utility
power) standards may require delivery of delivers +12, 3.3 and
.ANG.5 volts, and any required lower voltages may be derived from a
+5 or +12 volt supply line by additional circuitry, generally known
as voltage regulation modules, or VRMs, generally placed near to
the circuits that require the lower voltage. These additional
circuits may again convert the higher voltage supply to high
frequency ac power, modifying the voltage through control of the
period of the ac power, and again re-rectifying to the lower
voltage dc. The VRM may take many forms, but a commonly used
circuit approach may be the so-called "buck converter", which may
"chop" the input voltage to a square wave with an average voltage
equal to the required output voltage, and then may filter the
square waveform to remove the alternating component, leaving the
desired low voltage dc. Because the switching action may produce
abrupt transitions, and for other reasons, it may be desirable to
smooth such transitions, thus it may be desirable to have a
relatively high input impedance or inductance. This can, of course,
conflict with the previously mentioned desire for a low output
impedance or inductance.
[0025] There may be several other problems with this standard
approach, and one of particular relevance here may relate to the
speed of response of the regulation system. A rapid change in the
load impedance may cause a disturbance in the output voltage unless
corrected, possibly by some control loop. This disturbance may be
caused by the response of the filtering system used to remove the
alternating component from the square wave output. The speed with
which the control loop can respond may depend upon the
characteristics of that filtering system and also upon the
frequency of operation of the converter (the "switching
frequency").
[0026] One may increase this speed of response by storing less
energy in the filtering system. Such a filtering system may
comprise a simple series connection of an inductor and a capacitor.
Storing less energy may require reducing the value of the
inductance and capacitance, but may be limited in the ability to
reduce these values by the potential necessity to adequately remove
the ac component (called "ripple") generally at the output of the
filter. The ripple may be reduced for a given value of inductance
and capacitance by increasing the switching frequency, but this
again may be limited by the ability of the electronic switches used
in creating the square waveform from the dc input. Such switches
may have a limited operating frequency, and may exhibit losses
(known as "switching losses") which may increase with the operating
frequency.
[0027] What is needed, then, is a VRM power conversion approach or
a power supply which may operate at a relatively low frequency to
permit efficient operation of the electronic switches, which may
have a low output ripple, low output impedance, high input
impedance, which may store less energy in the output filter for a
given frequency, and which may be at least as low in cost as prior
art technology. Accordingly, substantial attempts such as those
previously described by those skilled in the art may not have fully
addressed the considerations raised. The present invention may be
considered to address many of the previously mention considerations
and may be considered in some aspects a development away from that
which was previously known in the art.
III. DISCLOSURE OF THE INVENTION
[0028] Accordingly, it is an object of the present invention to
provide a means of converting medium voltage dc power to a low
voltage dc power at high current, permitting operation at higher
efficiency than can be achieved using prior art techniques.
[0029] It is another object of the present invention to maintain
that efficiency over a wide range of load conditions.
[0030] It is yet another object of the invention to provide a
source of low voltage dc power at high currents which can sustain
its voltage across a varying load even in the presence of high
rates of change of current draw.
[0031] It is also an object of the preset invention to provide
closer control of the output voltage of the power converter, even
for extremely short time periods. That is to say, it is an object
to provide a power source with better transient response to changes
in load.
[0032] It is a further object of the invention to provide a power
conversion system which stores less energy than that required by
the prior art.
[0033] It is additionally an object of the present invention to
provide a power conversion system which can be produced at lower
cost than alternative approaches with similar characteristics.
[0034] Accordingly, the present invention is directed to a system
of power conversion for performing a conversion from medium voltage
dc to low voltage, high current dc at the point of power
consumption with high efficiency and fast response.
[0035] The present invention utilizes a plurality of simple power
converters, combined with coupled inductors, so arranged that the
group of converters act together to produce a combined output which
exhibits low voltage, high current, and fast regulation
response.
IV. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG. 1 depicts one embodiment of a buck converter in
accordance with principles known in the prior art, together with
its waveforms.
[0037] FIG. 2 depicts a particular embodiment of a four phase buck
converter in accordance with principles known in the prior art.
[0038] FIG. 3 depicts the waveforms for the four phase buck
converter circuit embodiment of FIG. 2.
[0039] FIG. 4 depicts one embodiment of a power converter using two
buck converters combined with a combining transformer in accordance
with the present invention together with its waveforms.
[0040] FIG. 5 depicts a four phase power converter embodiment in
accordance with the present invention.
[0041] FIG. 6 depicts waveforms for the power converter circuit
embodiment of FIG. 5.
[0042] FIG. 7 is an embodiment of the invention depicting a four
phase converter using four 1:1 transformers in a parallel output
configuration in accordance with the present invention.
[0043] FIG. 8 depicts the waveforms for the parallel output four
phase converter embodiment shown in FIG. 7.
[0044] FIG. 9 is an embodiment of the invention depicting a four
phase converter in a parallel output configuration using three 1:1
transformers in accordance with the present invention.
[0045] FIG. 10 is an embodiment of the invention depicting a four
phase converter using four 1:4 transformers in a series output
configuration in accordance with the present invention.
[0046] FIG. 11 is an embodiment of the invention depicting a four
phase converter in a series output configuration in accordance with
the present invention which utilizes three 1:4 transformers.
[0047] FIG. 12 is an embodiment of the invention depicting a three
phase converter in a mixed combiner circuit in accordance with the
present invention which utilizes 1:1 transformers.
[0048] FIG. 13 is an embodiment of the invention depicting a three
phase converter in a mixed combiner circuit in accordance with the
present invention which utilizes 1:3 transformers.
[0049] FIG. 14 is a series of waveforms which explain voltage an
current events during an abrupt current draw transition.
[0050] FIG. 15 shows a tiered combination using one unequal
transformer.
[0051] FIGS. 16, 17, and 18 shown other topologies for tiered
networks.
[0052] FIG. 19 shows an isolated power input design.
[0053] FIGS. 20 and 21 depict regulation details of one isolated
power input design.
[0054] FIG. 22 shows an isolated single AC input source design.
V. MODE(S) FOR CARRYING OUT THE INVENTION
[0055] As can be easily understood, the basic concepts of the
present invention may be embodied in a variety of ways. These
concepts involve both processes or methods as well as devices to
accomplish such. In addition, while some specific circuitry is
disclosed, it should be understood that these not only accomplish
certain methods but also can be varied in a number of ways. As can
be seen from the drawings, the basic concepts of the present
invention may be embodied in many different ways. Importantly, as
to all of the foregoing, all of these facets should be understood
to be encompassed by this disclosure.
[0056] In the production of a low regulated dc voltage from a
higher voltage source, the so-called "buck" converter may be
commonly used. This converter, illustrated in FIG. 1, may be
considered a simple circuit with generally four basic components:
two electronic switches, one inductor, and one capacitor. If the
output voltage is large compared with the voltage drop across a
diode, the lower electronic switch may be replaced by a diode.
[0057] The circuit in FIG. 1 works as follows. Switches 2 may be
periodically and alternately actuated so that part of the period
the voltage at node 3, one type of a power input, may be equal to
zero and part of the period the voltage may be equal to supply
voltage 1. Thus the voltage at node 3 may be a pulsed waveform, as
shown in the lower portion of FIG. 1, with an average value
generally less than input voltage 1. During the time the upper
switch is on, the current may increase in inductor 4 and during the
time the lower switch is on the current in inductor 4 may decrease.
Once the power input is accepted, the output voltage 7 across or
powering load 5 (such schematically as a resistance), or the
programmable processor or a part thereof, may be equal to the
average value of the pulsed waveform at node 3 (and, therefore, may
be less than input voltage 1) and may be dc with a superimposed
ripple as shown in the lower part of FIG. 1. Regulation or
adjustment of the output 7 is obtained by varying the percentage of
the time the upper switch is closed relative to the lower
switch.
[0058] As mentioned above, the direction of microprocessor and
specialized semiconductor integrated circuits may be such that the
powering voltages and transient response time may be decreasing
rapidly while the current is increasing. A principal problem with
transient response may center around inductor 4. To achieve a fast
transient response, inductance 4 may be made as small as possible.
Neglecting issues such as regulation loop response and delay, the
buck converter may have a maximum capability to increase its output
current which is equal to the input voltage 1 minus the output
voltage 7, divided by the value of inductor 4. The converter's
ability to decrease the output current may be the output voltage 7
divided by the value of inductor 4, generally different and a
smaller number. It may be desirable, therefore, to decrease the
value of inductor 4 to the minimum possible level.
[0059] The ability of the designer to decrease the value of
inductor 4 may be limited by two principal factors: the ripple
voltage 9 on the output of the converter and the ripple current 8
in the inductor 4. An important factor in the design of inductor 4
may be the ratio of ripple current 8 to the average value of output
current flowing in load resistance 5, as it affects the core
material and its size and cost. Further, a large ripple current 8
may increase the losses in switches 2, which may require that they
be sized larger and cost more. Perhaps even more important, the
presence of large ripple currents may cause voltage drops across
parasitic inductances in the wiring and packaging of the various
components, and layout may become increasingly difficult or
impossible. In practice, the value of inductor 4 may be reduced
until the efficiency of the converter is as low as is permissible,
and the value of capacitor 6 may be made as large as possible to
lower output ripple 9 to acceptable values and to reduce the
voltage over- or under-shoot during transient conditions. It should
be mentioned that again there may be limits on the designer to
increasing the value of capacitor 6, related to the technology of
capacitors, and an increase in value may correlate to an increase
in cost.
[0060] Of course, the design of a power supply for a complex
electronic system such as a computer workstation may involve many
more factors and tradeoffs than indicated in this discussion.
[0061] In an attempt to improve the transient response and lower
the output ripple, designers have constructed systems of N buck
converters wired in parallel, as shown in FIG. 2 for the case of
four converters. Switch pairs 10, 11, 12, 13 may be driven
simultaneously, or in a phase sequence by delaying each pair's
switching action by a fraction of a switching period. As can be
understood, there can be multiple inputs such as first power input
14, second power input 15, third power input 16, and fourth power
input 17.
[0062] FIG. 3 shows possible waveforms for a phased sequence
switching design. Generally this "multiphase" approach may be used
because the magnitude of the output ripple 20 may thereby be
reduced for the same value of capacitor 6 when compared to
paralleled inputs, here buck converters, driven simultaneously.
This multiphase drive may also lower the input ripple (the ac
current drawn from power supply 1), which may be an advantage; the
drive circuits, or merely a sequential and repetitive active
element control element, easily understood to exist for FIG. 2, may
become more complex, but may not be too expensive as these may be
considered low level circuits which can be incorporated into a
single integrated circuit. In operation such a power supply creates
at least one of the power inputs from repetitive operation of
active elements, such as the switches shown for this buck converter
element 10 combined. A first active element 10 upper is operated to
feed power through the first active element 10 upper to establish
the power input 14 during a first input time. Sequentially, the
second active element 10 lower is operated to feed the power
through the second active element 10 lower to establish the first
power input 14 during a second input time which can be different
from the first input time. As mentioned earlier this may be
accomplished by using two switch elements as shown or it may be a
switch element and a diode element (for example, by replacing 10
lower with a diode in the figure). There may also be a sequential
and repetitive active element control element to which the active
elements are sequentially responsive.
[0063] The multiple inputs may be combined to create a combined
power signal which may then be further conditioned or not to create
the power output such as the output voltage 7. As explained later,
by the present invention, this may be algebraic mean or even the
algebraic average of the inputs. The entire combination may be
achieved by a combiner network (shown in FIG. 3 as the combination
of the various inductors 19). This combiner network may thus be
responsive to at least two power inputs and if properly configured
may actually be configured to be an algebraic mean combiner network
or perhaps an algebraic average combiner network.
[0064] As has been already mentioned, the transient response of a
buck converter or other such power input may be determined by the
input voltage 1, the output voltage 7 and the value of series
inductor 19 in FIG. 2. If the N converters are driven
simultaneously (i.e., not in multiphase), each of the inductors 19
may be made larger by a factor of the number of converters in the
system (four in FIG. 2), as the total response of the output may be
the sum of the individual converters. In this case the ripple
current 21 may be N times smaller and the dc current N times
smaller, leaving the ratio unchanged from the single converter
case. The individual converter's ability to produce a change in the
output 7 may be smaller by a factor of N, but the system of
converters may be able to change the output at the same rate as the
single converter case. Since each converter may handle 1/N of the
current and have 1/N of the current ripple, each converter may be
made smaller by a factor of N. The output ripple frequency,
however, is the fundamental frequency and there may be no
improvement over the single converter case--that is, the value of
capacitor 6 may not be reduced. The apparent gain in dividing the
single buck converter into a system of smaller ones is the easing
of the handling of parasitic reactance of the wiring and packaging
of the various components, at the expense of increasing the number
of components by N.
[0065] If, on the other hand, the converter system is driven in a
multiphase manner, as shown in the waveforms of FIG. 3, each buck
converter may be governed by its own ability to modify the output
current in its turn. At the moment of switching each converter can
change the output by a factor 1/N (1/4 in this case), but within a
total period all N converters will be actuated and therefore again
the system of converters may be able to change the output at the
same rate as the single converter case of FIG. 1.
[0066] The ripple current 21 in inductors 19 may be determined by
the difference between the input voltage 1 and output voltage 7
divided by the inductance, and may be the same as the simultaneous
drive case just mentioned: the ripple current being N times smaller
and the dc current in the inductor 19 also N times smaller, and the
ratio of ripple current 21 to output current 18 for each converter
unchanged from the single converter case of FIG. 1. There may be a
reduction in output ripple by a factor of N, because the size of
the current impulses absorbed by capacitor 6 may be reduced by a
factor of N (4 in this case) and the frequency of these impulses
increased by the same factor. This may permit a reduction in the
size of capacitor 6 in some cases. Also, there may be a reduction
in the pulsed current drawn by the system of converters from input
source 1 for the same reason. These reductions in peak input and
output ripple current may permit some ease in layout of the circuit
and some tolerance to the reactance of the wiring and the packaged
electronic components comprising the system.
[0067] Nevertheless, assuming that the designer has optimized the
value of inductors 19 in the same way for the multiphase system of
FIG. 2 as in the single buck converter--that is, to choose a
reasonable maximum value for the ratio of the ripple current 21 to
the dc current 18 and for the root-mean-square current losses in
switch pairs 10, 11, 12 and 13, there may be no improvement in
transient response.
[0068] Thus, whether the multiple buck conversion systems of the
prior art are driven simultaneously or in multiphase, there may be
no improvement in transient response, and the advantages of such
systems may be marginal and related to some ease of layout in
return for significantly higher cost.
[0069] The present invention in particular embodiments uses
combining transformers or other combining networks to overcome the
limitations of the prior art converter systems. Significantly, one
combining network can serve both inputs. The multiple inputs can
use an identical network which, as explained herein, can serve as
both a high effective input inductance and a low effective output
inductance. Further, this can be accomplished while even utilizing
only passive elements (perhaps only inductors and capacitors as
shown). Thus the inputs are each substantially affected (that is
affected in a manner which can cause a significant impact on
operation of the programmable processor) by only passive electrical
elements. To understand how particular embodiments of the invention
are accomplished, it may be best to start with an embodiment of but
two converters as shown in FIG. 4. In FIG. 4 it may be seen that
switches 22 and 24 comprise a first switching stage 33 and switches
23 and 25 comprise a second switching stage 34. These two stages
are driven in "multiphase", as will be seen in the waveforms of
FIG. 4. The outputs of these two stages may be combined in
combining transformer 26 before being presented to an output filter
comprised of inductor 31 and capacitor 6.
[0070] The design can thus serve as a programmable processor power
supply which can have a high current, low voltage power output 7
for a programmable processor 5. With this basic aspect of design,
the power output 7 can supply a current draw which can abruptly
change by the demand of the programmable processor while
maintaining a substantially constant voltage on the power output,
This can be significant in that it can prevent either an
overvoltage spike or an undervoltage, which can either damage,
destroy, or stop a programmable processor from properly
functioning. Thus the power output 7 can actually be an abruptly
changeable, substantially constant voltage power output.
[0071] In FIG. 14 one can see what is commonly referred to as the
1.sup.st and 2.sup.nd spikes when there is an abrupt current draw
transition. The first spike is usually considered as a result of
the ESL and ESR of the bypass capacitors. The second spike is
usually considered as a result of the a result of the capacitance
value of the microprocessor bypass capacitor and the power supply
output inductance. The equation V=L I.sup.2/CV describes the
approximate relationship between the value of a current step and
the resulting voltage step due to power supply output inductance
and microprocessor bypass capacitance. For a given output
capacitance the transient response capability of a power supply is
largely determined by the output inductance. A smaller output
inductance gives better voltage regulation capability. In FIG. 14,
the second spike is due to the bypass capacitance and the power
supply output inductance. In the object of the invention the output
inductance can be made arbitrarily small to enable the next
generation of microprocessors to be powered using reasonable
amounts of bypass capacitance. In the extreme, the programmable
processor power supply power output inductance may approach zero if
the power supply is operated in a substantially uninterrupted
sequenced conduction (SUSC) mode (also herein called the sweet
spot).
[0072] By this basic design principle extended for specific
applications, power can now be supplied to a programmable processor
with various parameters previously not achievable. These include
the following in any combination or permutation:
[0073] a power output having at least about a 20 amp maximum
current,
[0074] a power output having at least about a 50 amp maximum
current,
[0075] a power output having at least about a 100 amp maximum
current,
[0076] a power output having at least about a 200 amp maximum
current,
[0077] a power output having a current change of at least about
100% of a current draw,
[0078] a power output having a current change of at least about
100% of a maximum current draw,
[0079] a power output outputting less than about 2 volts,
[0080] a power output outputting less than about 1.8 volts,
[0081] a power output outputting less than about 1.5 volts,
[0082] a power output outputting less than about 1.3 volts,
[0083] a power output outputting less than about 1.0 volts,
[0084] a power output outputting less than about 0.4 volts,
[0085] a power output preventing a changes in voltage of less than
about 20% of said low voltage output,
[0086] a power output preventing a changes in voltage of less than
about 10% of said low voltage output,
[0087] a power output preventing a changes in voltage of less than
about 5% of said low voltage output,
[0088] a power output preventing a changes in voltage of less than
about 2% of said low voltage output,
[0089] a high rate of current change output,
[0090] a typical current change of greater than about 0.1 A/ns
output,
[0091] a typical current change of greater than about 1A/ns
output,
[0092] a typical current change of greater than about 5 A/ns
output, and even
[0093] a typical current change of greater than about 10 A/ns
output.
[0094] Further the programmable processor may be configured in a
wide range of new systems needing such capability, such as next
generation microprocessors running at at least hundreds of
megahertz, 1 GHz, 2 GHz, 5 GHz, or even 10 GHz, memory management
circuitry, graphic display circuitry, input-output circuitry, a
central processing element, telecommunication circuitry, radar
circuitry, and even vehicle power circuitry.
[0095] To understand how these may be possible, it is helpful to
understand the waveforms in FIG. 4. Switching produces the input
current pulses 29 at some voltage. The pulses are affected by an
effective input inductance (the inductance altering the switched
input). Since it is desirable to provide a steady DC output, it is
desirable to have the inputs affected by a high effective input
inductance. This causes the slope on the buck phase pulses as
shown. Thus the high effective input inductance is an item to which
the multiple power inputs are responsive. This high effective input
inductance may have a variety of values, but in the initially
anticipated designs it may have effective values of greater than
about 100, 200, 500, or even 1000 nH. Configuring the sequenced
drive to achieve the voltage pulses as shown, it can be seen how an
output voltage 7 equal to one-fourth of the input voltage 1 can be
achieved. In this case, switches 22 and 24 and switches 23 and 25
each may produce a waveform with a 25% duty factor; that is, the
period of conduction of switches 22 and 23 may be one-third of the
periods of conduction of switches 24 and 25. Thus the average value
of the voltage at nodes 27 and 28 may be one-fourth of the input
voltage. Since there can be no steady state dc voltage across the
windings of transformer 26, the average dc voltage at node 30 may
also be one-fourth of the input voltage. The alternating component
of the voltage at node 30 may be half the algebraic sum of the
voltages at nodes 27 and 28: 1 V 30 = 1 2 ( V 27 + V 28 )
[0096] and, as shown in FIG. 4, may therefore be a square wave of
twice the switching frequency of the individual switching stages
and half the amplitude. The ripple current 35 in filter inductor 31
may be reduced therefore by a factor of, 2 = 1 2 V i n - V out V i
n - V out = 1 2 V i n - 2 V out V i n - V out
[0097] which, for the case of FIG. 4 (V.sub.in=4V.sub.out), reduces
to one-third of the magnitude of the ripple current in the buck
converter of FIG. 1, for the same value of inductance, input
voltage and output voltage. Thus, to maintain the same ratio of
ripple current 35 to average output current 32 in inductor 31 of
FIG. 4 as compared to inductor 4 in FIG. 1, one could reduce the
value of inductor 31 by a factor of three.
[0098] Further, the average current 26 in switching transistor 22
during its conduction period may be half of the average output
current by the action of transformer 26, and the ac component of
current 26 may also be half of the ac component 35 of current 32 in
inductor 31. Of course, as there are four switches in FIG. 4 as
compared to two switches in FIG. 1, the total losses in the
totality of switches in the two figures may be the same if the
inductor is reduced by the above factor of three.
[0099] As mentioned this reduction in the inductor 31 is consistent
with a goal of a fast response system, namely, providing a low
effective output inductance (that which causes or limits an ability
to permit fast current changes). This can permit a low effective
output inductance power output which is responsive to a combiner
network which also exhibits the high effective input inductance.
Even more surprising, it permits this while using an identical
network! Again the values can be considerable--especially when
taken in light of the input inductance mentioned earlier. They can
include an output inductance less than about {fraction (1/10)},
{fraction (1/100)}, or {fraction (1/1000)} of said input
inductance, and even an output with an inductance less than about
50, 20, 10, or even 2 nH. The reduction in the value of output
inductor 31 and the overall effective output inductance may produce
an improved transient response by the same factor of three or more
over that of the simple buck converter of FIG. 1 or the multiple
buck converter system of FIG. 2.
[0100] Note from the foregoing that, if V.sub.out=V.sub.in/2 and
the factor.sub.--=0, the ripple current is zero. Graphically, this
occurs because the square waves at nodes 27 and 28 add together in
this case to form a waveform which may be "pure dc"; that is, a
waveform without any variations or "gaps". In this case the
inductor could, in principle, be reduced to very nearly zero. This
case is an example of what has been defined as SUSC mode or "sweet
spot" throughout this application. From this it may be seen that,
if one has the freedom to choose the input voltage to be exactly
twice the required output voltage, one can obtain very fast
transient response in such a circuit. Of course, the designer
should allow for variations in both the input and output voltage,
but by working close to the point where .sub.--=0, the transient
response may be greatly improved. As will be seen, systems with N
converters have in general (N-1) "magic ratios", where improvement
may be possible in transient response by reduction of the value of
the filter inductor without increase in output ripple, inductor
complexity, or switch losses. Even if the system of the present
invention is operated at input/output ratios different from these
special points, however, a substantial reduction in the value of
the filter inductance and a concomitant increase in transient
response.
[0101] By using a transformer or magnetic coupling as part of the
combining network--even with a 1:1 turns ratio--substantial benefit
can be achieved. The transformer circuitry may serve to
magnetically couple or as a magnetic coupling of the two power
inputs. When the first input is operated, it can act to create a
first directional effect (a magnetic field) in the combiner
network. When the second input is operating it can act to create a
second directional effect in the same element. Importantly, by
correctly configuring the design, this second directional effect
can oppose the first. Thus the inductive element or the transformer
winding can establish a magnetic field in opposite directions. Thus
the combiner network can include a reverse polarity element or even
a reverse polarity transformer. In either case, a first coil with a
positive side may be connected to a second coil with a negative
side and the two can be magnetically coupled. By such a reverse
polarity connection, the first passive directional effect element
and the second passive directional effect element can oppose each
other. Since the magnetic field elements oppose in this regard, the
result can be both a high input inductance and a low output
inductance.
[0102] Further, the transformer element, if used can be a reduced
magnetic field stored energy transformer in that there is no need
to include much energy storage. It may even be a non-air gap
transformer. In selecting the transformer design, it may be
desirable to provide a transformer in which the winding largely
overlap. Thus the transformer can be a substantially coincident
transformer. This can serve to provide better opposition and it can
even permit the transformer to be a substantially insaturable
transformer because over the range used it cannot be saturated.
Finally although the discussion is in the context of an equal, 1:1
transformer (equal windings), naturally there are designs which may
prefer unequal transformers as well. As shown, the transformer can
be linked to multiple power inputs to achieve the desired
effect.
[0103] FIG. 5 shows a four-converter embodiment of the present
invention. Here switch pairs 36, 37, 38 and 39 may be driven in a
multiphase manner as shown in the waveforms of FIG. 6. Outputs 40,
41, may be combined with combining transformer 44, outputs 42 and
43 may be combined with combining transformer 45, and the resulting
signals 47 and 48 may be combined in combining transformer 46 to
form a single output which is connected to an output filter
comprised of inductor 50 and capacitor 6. Mathematically, this
single output is the algebraic mean of the voltages at nodes 40,
41, 42 and 43: 3 V 49 = 1 4 n = 40 n = 42 ( V n )
[0104] The waveforms of FIG. 6 are drawn for an output voltage 7
equal to one-eighth of the input voltage 1. In this case, switch
pairs 36, 37, 38 and 39 may each produce a waveform with a 12.5%
duty factor; that is, the period of conduction of the upper switch
of each pair is one-seventh of the period of conduction of the
lower switch of each pair. As previously mentioned, the pairs may
be driven in multiphase as shown in FIG. 6. Thus the average value
of the voltage at each of the nodes 40, 41, 42 and 43 is one-eighth
of the input voltage. Since there may be no steady state dc voltage
across the windings of transformer 44, the average dc voltage at
node 47 is also one-eighth of the input voltage. The alternating
component of the voltage at node 47 may be half the algebraic sum
of the voltages at nodes 40 and 41, and, as shown in FIG. 6 may be
a square wave of twice the switching frequency of the individual
switching stages 36 and 37, having half the amplitude of voltages
40 or 41. Similarly, there may be no steady state dc voltage across
the windings of transformer 45, and so the average dc voltage at
node 48 is also one-eighth of the input voltage, and the
alternating component of the voltage at node 48 is half the
algebraic sum of the voltages at nodes 42 and 43. Therefore, as
shown in FIG. 6, the voltage at node 48 may also be a square wave
of twice the switching frequency of the individual switching stages
38 and 39 and having half the amplitude of the voltage at nodes 42
and 43.
[0105] The voltage at nodes 47 and 48 may be further combined in
combining transformer 46 to form a signal at node 49, which by the
same reasoning as above may be a square wave with an average value
of one-eighth of the input voltage at a frequency four times that
of the individual switching stages 36, 37, 38, and 39, and so
having a peak amplitude of one-fourth of the input voltage.
[0106] The ripple current 53 in filter inductor 50 may be reduced
from that of ripple current 5 for the buck converter of FIG. 1,
therefore, by a factor of: 4 = 1 4 V i n - V out V i n - V out = 1
4 V i n - 4 V out V i n - V out ,
[0107] which, for the case of FIG. 5 (V.sub.in=8V.sub.out) reduces
to one-seventh, for the same value of inductance, input voltage and
output voltage in the two cases. Thus, to maintain the same ratio
of ripple current 53 to average output current 52 in inductor 50 of
FIG. 5 as compared to inductor 4 in FIG. 1, one could reduce the
value of inductor 50 by a factor of seven.
[0108] By affecting the output by a series inductive element after
utilizing the transformer circuitry the power output can be finally
conditioned for use. This series inductive element can serve as
that which smooths the output for an regulation needed, since not
all operation usually can occur at a substantially centered
constant conduction timing or a substantially uninterrupted
sequenced conduction point. Further, with proper design, it may
even be possible to use inherent output inductances to
affirmatively affecting the output as desired. The entire system
can be designed for inherent inductance or can use a separately
provided series inductor element. As shown, this is an uncoupled
inductive element provided in series which is responsive to the
transformer circuitry.
[0109] Returning to the specific example of FIG. 5, further it can
be seen that the average current 51 in switching transistors 36
during their conduction period may be one-fourth of the average
output current, by the action of transformers 44, 45 and 46, and
the ac component of current 51 may also be one quarter of the ac
component 53 of current 52 in inductor 50. Of course, as there are
eight switches in the embodiment of FIG. 5 as compared to two
switches in the embodiment of FIG. 1, the total losses in the
totality of switches in the two figures may be the same if the
inductor is reduced by the above factor of seven.
[0110] This reduction in the value of output inductor 50 may
produce an improved transient response by this same factor of seven
over that of the buck converter of FIG. 1 or the multiple buck
converter system of FIG. 2.
[0111] As can be understood from the example in FIG. 5, the
multiple inputs (three or more) can be tiered or can be connected
by a tiered coupling, one type of which is shown. These may involve
equal, or unequal transformers as shown in FIG. 15. As shown in
FIG. 5, the design can serve to establish a first order connection
network 86 (which can utilize an unequal transformer as shown) with
a plurality of first order inputs 83 and 84 where the first order
output 87 serves as the power output. In a tiered design, there may
be established second order output 84 which is created from a
second order connection network 85 which has second order inputs
83.
[0112] In understanding the tiered designs such as that shown in
FIG. 5, a system may be established by connecting a first power
input 40 to a second power input 41 by first and second inductor
elements 88 and 89 connected at a first intermediate series
connection 90. These two inductor elements 88 and 89 may be
magnetically coupled and may establish a first intermediate output
91 from first intermediate series connection 90. Similarly the
third power input 42 and the fourth power input 43 may be connected
by third and fourth inductor elements 96 and 97 connected at a
second intermediate series connection 98 and may also be
magnetically coupled as shown to create the second intermediate
output 99. The second intermediate output 99 from said second
intermediate series connection 98 may be connected to the first
intermediate output 91 by fifth and sixth inductor elements 92 and
93 connected at a third intermediate series connection 94. These in
turn may be magnetically coupled and may create the final power
output 95. Of course, this can be expanded to any number of tiers
and to other topologies.
[0113] In the configuration shown as merely another example in FIG.
7, it can be understood that the first power input 101 is connected
to the first transformer 59, the second power input 102 is
connected to the second transformer 60, the third power input 103
is connected to the third transformer 61, and the fourth power
input 104 is connected to the fourth transformer 62. The first
transformer 59 is connected to said second transformer 60, the
second transformer 60 is connected to the third transformer 61, the
third transformer 61 is connected to the fourth transformer 62, and
the fourth transformer 62 is connected to the first transformer 59.
As mentioned earlier this may be done utilizing a reverse polarity
transformer connection. Each of the transformers is also connected
to a common intermediate output 67 which is connected to a filter
element 68 from which power is provided. Again this can be expanded
to any number of tiers and to other topologies. Some of the many
possible examples are shown in FIGS. 16, 17, and 18.
[0114] FIG. 6 shows waveforms for the case of the output voltage
equal to one-eighth of the input voltage. If the ratio of input to
output voltage is lowered to four, each of the individual switch
pairs 36, 37, 38, and 39 may be switching at a 25% duty factor, and
the waveforms at nodes 47 and 48 may be at a 50% duty factor. This
means that the waveform at node 49 may be a steady dc voltage equal
to one-fourth of the input voltage 1, as the waveforms at nodes 47
and 48 may exactly interleave with no gaps. In this case the
inductor could, in principle, be reduced to very nearly zero. In
analogy to the case of the circuit shown in the embodiment of FIG.
4 operated at a ratio of V.sub.in/V.sub.out=2, if one has the
freedom to choose the input voltage to be four times the output
voltage, for the circuit in FIG. 5 one can obtain very fast
transient response. As before, the designer should allow for
variations in both the input and output voltage, but by working
close to a point where .sub.--=0, he or she may greatly improve the
transient response.
[0115] If the ratio of input to output voltage of the circuit in
FIG. 5 is further reduced (raising the output voltage for a given
input) below 25%, the voltage at node 49 may switch between
one-fourth and one-half of the input voltage, at a duty factor
which may depend upon the duty factor of the individual switch
pairs 36, 37, 38, and 39. When the duty factor of individual switch
pairs 36, 37, 38, and 39 reaches 50%, the voltage at node 49 may
again be a steady dc voltage, in this case one-half of the input
voltage 1. Again the output inductor 50 may be reduced in value to
nearly zero. This effect may repeat again at a duty factor of
individual switch pairs 36, 37, 38, and 39 of 75%, where the
voltage at node 49 becomes three-quarters of the input voltage 1.
Thus the equation for the ripple reduction from that of ripple
current 5 for the simple buck converter of FIG. 1 becomes, in
general, 5 = NV i n - MV out V i n - V out ,
[0116] where N is the number of individual switch pairs and M is an
integer taking on the discrete values 1,2,3, . . . (N-1) producing
the reduced single phase current delta 54. When
NV.sub.in-MV.sub.out is near to zero, a great reduction in the
value of the filter inductor may be possible with a concomitant
improvement in transient response of the converter. This may occur
once for the system of FIG. 4, three times for the system of FIG.
5, and in general (N-1) times for a system of N converters.
[0117] FIG. 7 shows a different configuration of combining
transformers and switch pairs, resulting in yet another embodiment
of the present invention. Here the nodes 55, 56, 57, and 58 from
four switch pairs may be connected as shown in the figure to create
an output voltage through combiner transformers 59, 60, 61, and 62,
each of which may have a turns ratio of 1:1 (that is, the number of
turns on the primary and secondary winding are the same). Because
of this 1:1 turns ratio, the voltages across the two windings of
transformer 59 may be the same, which is to say:
V.sub.67-V.sub.66=V.sub.55-V.sub.63,
[0118] where V.sub.67 is the voltage at node 67, V.sub.66 is the
voltage at node 66, and so on. Similarly for transformer 60:
V.sub.67-V.sub.63=V.sub.56-V.sub.64
[0119] And for transformer 61:
V.sub.67-V.sub.64=V.sub.57-V.sub.65
[0120] And finally for transformer 62:
V.sub.67-V.sub.65=V.sub.58-V.sub.66
[0121] Adding these equations together yields the single
equation:
4V.sub.67=V.sub.55+V.sub.56+V.sub.57+V.sub.58
[0122] Or 6 V 67 = 1 4 ( V 55 + V 56 + V 57 + V 58 )
[0123] Assuming the switch pairs connected to nodes 55, 56, 57, and
58 are driven in multiphase as in the case of the embodiment shown
in FIG. 5, the resulting waveforms are shown in FIG. 8, which upon
inspection are the same as those of FIG. 6. Therefore all of the
comments regarding the embodiment of FIG. 5 may apply as well to
the embodiment of FIG. 7. Thus the embodiment of FIG. 7 may permit
the reduction of the value of inductor 68 in the same manner and to
the same extent as does the embodiment of FIG. 5.
[0124] It may be observed that, while FIG. 7 shows a certain
pleasing symmetry, there may be more free variables than are
required in the equations for the circuit. That is, V.sub.63,
V.sub.64 and V.sub.65 are all free to be established at any ac
voltage so long as the average of that voltage is the same as the
other nodes connected to the combining transformers. Therefore one
might simply connect one of the switch pairs directly to one of
these nodes and the output voltage directly to another, and doing
so eliminates one of the transformers. This configuration is shown
in FIG. 9.
[0125] The concept of the embodiment of FIG. 9 resulting in the
same performance as the embodiment of FIG. 7 may be seen by writing
the equations of the transformer nodes in the same way as before.
For transformer 59 in FIG. 9:
V.sub.67-V.sub.58=V.sub.55-V.sub.63
[0126] where as before V.sub.67 is the voltage at node 67, V.sub.58
is the voltage at node 58, and so on. Similarly for transformer
60:
V.sub.67-V.sub.63=V.sub.56-V.sub.64
[0127] And for transformer 61:
V.sub.67-V.sub.64=V.sub.57-V.sub.67
[0128] Again adding these three equations yields the result: 7 V 67
= 1 4 ( V 55 + V 56 + V 57 + V 58 )
[0129] This may be the same as for the four transformer case and so
the remarks made for the embodiment of FIGS. 5 and 7 may be as well
applied to the embodiment of FIG. 9.
[0130] Yet another embodiment, using transformers with a 1:4 ratio
may be seen in FIG. 10 where inputs at nodes 69, 70, 71, and 72 are
combined. Here the secondaries of transformers 73, 74, 75 and 76
may be connected in series to form an output voltage to be applied
to the output filter. As before one may write an equation for each
of the transformers to find the circuit operation. Alternatively,
for this configuration one may note that the output of the
combining transformers at node 81 may be simply the sum of the
outputs of the secondary voltages added to the voltage at the
common node 77. That is, mathematically, 8 V 81 = V 77 + 1 4 ( V 72
- V 77 ) + 1 4 ( V 71 - V 77 ) + 1 4 ( V 70 - V 77 ) + 1 4 ( V 69 -
V 77 ) , or V 81 = 1 4 n = 69 n = 72 V n ,
[0131] which is the same result as for the other embodiments in
FIGS. 5, 7, and 9, and so the circuit performance for this
embodiment using 1:4 transformers may be the same as the
embodiments using 1:1 transformers. In analogy with the case of
FIG. 7, one of the transformers may be eliminated if it is noted
that the voltage at node 77 is undefined (i.e., could be any ac
voltage with a dc component equal to the output voltage), and might
as well be made equal to one of the switched nodes. This is shown
in FIG. 11, where the output voltage may be seen to be, as before,
the sum of the secondary voltages added to the voltage at the
common mode, which in this case is V.sub.72: 9 V 81 = V 72 + 1 4 (
V 71 - V 72 ) + 1 4 ( V 70 - V 72 ) + 1 4 ( V 69 - V 72 ) , V 81 =
1 4 n = 69 n = 72 V n .
[0132] Thus the equations of performance and the waveform of the
voltage applied to the output inductor 82 in FIG. 11 may be the
same as that for the other embodiments of four phase power
converters according to the present invention, namely FIGS. 5, 7, 9
and 10.
[0133] In general, one may combine N switch pairs with N-1
transformers, and it will be seen by extension that a reduction in
the ripple current in the output inductor may be achieved by a
factor of: 10 = NV i n - MV out V i n - V out
[0134] where N is the number of individual switch pairs and M is an
integer taking on the discrete values 1,2,3, . . . (N-1). This
reduction in ripple current permits the designer to reduce the
value of the output inductor by the same amount, to return the
ripple current back to its original value. Further to this
principle, when (NV.sub.in-MV.sub.out) is near zero, a great
reduction in the value of the filter inductor is possible with a
concomitant large improvement in transient response of the
converter. This will occur in general (N-1) times for a system of N
converters as the ratio of output to input voltage is varied.
[0135] It should be noted that the above descriptions and the
waveforms in FIGS. 4, 6 and 8 assume that the source impedance of
the combined waveform at the point of application to the output
filter inductor (node 30 in FIG. 4, node 49 in FIG. 5, node 67 in
FIGS. 7 and 9, and node 81 in FIGS. 10 and 11) is low compared to
the impedance of the output filter and load placed on the
converter. That is to say, the on resistance from drain to source
(R.sub.ds(on)) of the switching devices as reflected to those nodes
should be low compared to load resistance 5, and the leakage
inductance of the combining transformers must be small compared to
the output inductance. In general, the former inequality will be
approximately valid because otherwise too large a fraction of the
input power will be lost in the switching devices. It may be,
however, that it is inconvenient, difficult, or costly to implement
the combining transformers such that their individual leakage
inductances are small compared to the desired value of output
filter inductance. In this case the inductance of the output filter
inductor (31 in FIG. 4, 52 in FIG. 5, 68 in FIGS. 7 and 9, and 82
in FIGS. 10 and 11) may be reduced by the effective value of the
leakage inductance at the combining node (node 30 in FIG. 4, node
49 in FIG. 5, node 67 in FIGS. 7 and 9, and node 81 in FIGS. 10 and
11). If this is done, the waveforms of the voltage at the combining
node will not be as shown in the figure, because of the possible
distorting effect of the combining transformers' leakage
inductance, but circuit operation and the current in inductor 31 in
FIG. 4, 52 in FIG. 5, 68 in FIGS. 7 and 9, or 82 in FIGS. 10 and 11
will be the same as that of the circuit with ideal transformers and
the appropriate value of output inductance. In this way
compensation may be made of the non-ideal nature of the combining
transformers.
[0136] Of course the circuit and method of the invention may have
isolated inputs. That is, it is possible to use conventional
isolated power conversion circuits as an input to the coupled
output section. For example a phase shifted bridge circuit may be
used on a primary side. This circuit could have a transformer
isolating the primary side from the rectifier side. In this
instance the circuit feeding the coupled inductor section could
have a bipolar input.
[0137] Some embodiments of this circuit are shown in FIGS. 19, 20,
and 21. These include feeding a four input tiered combiner output
section, although as shown in FIG. 22 a single AC input source can
also be effectively used. The inputs can be isolated sources, may
be interleaved switched voltage sources, bipolar sources,
interleaved bipolar sources, or any permutations or combinations of
these.
[0138] The four inputs in FIGS. 19, of course, can be operated with
the SUSC mode. In this mode, the output may only have brief
transients that are artifacts of regulation, thus more limited
filtering may be needed. As shown in the waveforms of FIGS. 20 and
21, these transients may be caused by short periods of time when
the regulation causes disruption of the SUSC ideal. The output
filter now may only need to be large enough to filter the
regulation delta and thus there may be only a source with
substantially only a regulation delta filter element. Although
applicable to virtually any designs of the invention, as most
graphically shown by the waveforms of FIGS. 20 and 21, by
substantially centering operation about a point at which constant
conduction would occur a higher percentage of the time (e.g., using
a SUSC drive), only the small pulse at which sequencing is adjusted
off the SUSC point needs to be filtered. Thus, a smaller filter,
less energy, and faster response is possible. As mentioned earlier,
this, of course, may be accomplished by inherent inductances or
parasitic elements. Thus the system may be designed to
affirmatively use substantially only a parasitic element filter
with any of the types of sources available. This technique will be
extremely valuable as a method of powering generations of
processors well into the future.
[0139] It should be pointed out, however, that the coupling
coefficient of the combining transformers may need to be adequate;
that is, that the leakage inductance may need to be much smaller
than the magnetizing inductance, and that the cancellation of the
flux in the transformer cores may need to be adequate to prevent
saturation of the magnetic material, in order that the circuit
operate properly.
[0140] Finally, while the discussion above is directed toward a
system of buck converters, it should be understood that the
invention applies as well to any collection of power conversion
stages. In general, this invention can be embodied in a variety of
ways. In addition, each of the various elements of the invention
and claims may also be achieved in a variety of manners. This
disclosure should be understood to encompass each such variation,
be it a variation of an embodiment of any apparatus embodiment, a
method or process embodiment, or even merely a variation of any
element of these. Particularly, it should be understood that as the
disclosure relates to elements of the invention, the words for each
element may be expressed by equivalent apparatus terms or method
terms--even if only the function or result is the same. Such
equivalent, broader, or even more generic terms should be
considered to be encompassed in the description of each element or
action. Such terms can be substituted where desired to make
explicit the implicitly broad coverage to which this invention is
entitled. As but one example, it should be understood that all
action may be expressed as a means for taking that action or as an
element which causes that action. Similarly, each physical element
disclosed should be understood to encompass a disclosure of the
action which that physical element facilitates. Regarding this last
aspect, the disclosure of a "switch" should be understood to
encompass disclosure of the act of "switching"--whether explicitly
discussed or not--and, conversely, were there only disclosure of
the act of "switching", such a disclosure should be understood to
encompass disclosure of a "switch." Such changes and alternative
terms are to be understood to be explicitly included in the
description.
[0141] The foregoing discussion and the claims which follow
describe the preferred embodiments of the invention. Particularly
with respect to the claims it should be understood that changes may
be made without departing from their essence. In this regard it is
intended that such changes would still fall within the scope of the
present invention. It is simply not practical to describe and claim
all possible revisions which may be accomplished to the present
invention. To the extent such revisions utilize the essence of the
invention each would naturally fall within the breadth of
protection accomplished by this patent. This is particularly true
for the present invention since its basic concepts and
understandings are fundamental in nature and can be applied in a
variety of ways to a variety of fields.
[0142] Any acts of law, statutes, regulations, or rules mentioned
in this application for patent; or patents, publications, or other
references listed or mentioned in this application for patent are
hereby incorporated by reference, however, as to each, to the
extent that such information or statements incorporated by
reference might be considered inconsistent with the patenting of
this/these invention(s) such statements are expressly not to be
considered as made by the applicant(s). In addition, as to each
term used it should be understood that unless its utilization in
this application is inconsistent with such interpretation, common
dictionary definitions should be understood as incorporated for
each term and all definitions, alternative terms, and synonyms such
as contained in the Random House Webster's Unabridged Dictionary,
second edition are hereby incorporated by reference.
[0143] Additionally, the various combinations and permutations of
all elements or applications can be created and presented. Each
dependent claim may be presented as a dependency on each and every
one of the independent claims presented. In this regard it should
be understood that for practical reasons and so as to avoid adding
potentially hundreds of claims, the applicant has presented the
claims with initial dependencies only. Support should be understood
to exist to the degree required under new matter laws--including
but not limited to European Patent Convention Article 123(2) and
United States Patent Law 35 USC 132 or other such laws--to permit
the addition of any of the various dependencies or other elements
presented under one independent claim as dependencies or elements
under any other independent claim. All can also be done to optimize
the design or performance in a specific application. Further,
unless the context requires otherwise, the word "comprise" or
variations such as "comprises" or "comprising", should be
understood to imply the inclusion of a stated element or step or
group of elements or steps but not the exclusion of any other
element or step or group of elements or steps.
* * * * *