U.S. patent application number 10/249653 was filed with the patent office on 2004-11-04 for level shifter circuit.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Lencioni, Michael J..
Application Number | 20040217798 10/249653 |
Document ID | / |
Family ID | 33309312 |
Filed Date | 2004-11-04 |
United States Patent
Application |
20040217798 |
Kind Code |
A1 |
Lencioni, Michael J. |
November 4, 2004 |
LEVEL SHIFTER CIRCUIT
Abstract
A level shifter circuit is disclosed. The level shifter circuit
includes a first level shifter circuit and a second level shifter
circuit. The first level shifter circuit and the second level
shifter circuit are substantially identical with each other. The
second level shifter circuit is coupled to the first level shifter
circuit via a couple of transistors to provide an output and a
complementary output, respectively.
Inventors: |
Lencioni, Michael J.; (South
Burlington, VT) |
Correspondence
Address: |
BRACEWELL & PATTERSON, L.L.P.
P.O. BOX 969
AUSTIN
TX
78767-0969
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
33309312 |
Appl. No.: |
10/249653 |
Filed: |
April 29, 2003 |
Current U.S.
Class: |
327/333 |
Current CPC
Class: |
H03K 3/356113 20130101;
H03K 3/012 20130101 |
Class at
Publication: |
327/333 |
International
Class: |
H03L 005/00 |
Claims
1-6. cancelled
7. cancelled
8. A level shifter circuit comprising: a primary level shifter
circuit having a first invertor circuit coupled to a power source
via a first p-channel transistor, and a second invertor circuit
coupled to said power source via a second p-channel transistor,
wherein an output of said first invertor circuit is connected to a
gate of said second p-channel transistor, and an output of said
second invertor circuit is connected to a gate of said first
p-channel transistor; and a secondary level shifter circuit
substantially identical to said primary level shifter circuit,
wherein said secondary level shifter circuit is coupled to said
primary level shifter circuit via a first driver transistor to
provide an output and a second driver transistor to provide an
complementary output.
9. cancelled
10. cancelled
11. The circuit of claim 8, wherein said secondary level shifter
circuit includes a third invertor circuit coupled to said power
source via a third p-channel transistor, and a second invertor
circuit coupled to said power source via a fourth p-channel
transistor.
12. The circuit of claim 11, wherein an output of said third
invertor circuit is connected to a gate of said fourth p-channel
transistor, and an output of said third invertor circuit is
connected to a gate of said third p-channel transistor.
13. The circuit of claim 12, wherein one of said plurality of
driver transistors is connected between said output of said second
invertor circuit and output of said third invertor circuit to
provide said output.
14. The circuit of claim 13, wherein another one of said plurality
of driver transistors is connected between said output of said
first invertor circuit and output of said fourth invertor circuit
to provide said complementary output.
15. The circuit of claim 14, wherein said first and second driver
transistors are n-channel transistors.
Description
BACKGROUND OF INVENTION
[0001] 1. Technical Field
[0002] The present invention relates to electronic circuits in
general, and in particular, to level shifter circuits. Still more
particularly, the present invention relates to a level shifter
circuit having improved characteristics in low to high voltage
conversion operations.
[0003] 2. Description of the Related Art
[0004] Modern integrated circuit (IC) devices often have to
interface with IC devices from previous technology generations.
However, the complementary metal-oxide semiconductor (CMOS) voltage
levels on IC devices from previous technology generations are
usually different from those on IC devices from the current
technology generation. Thus, in order to ensure proper interfacing
between different CMOS voltage levels, modern IC devices must
include output buffer circuits that are capable of driving voltages
greater or less than the source voltage.
[0005] Generally speaking, an output buffer circuit includes a
level shifter circuit that is coupled to a power supply having a
voltage different from the source voltage. In response to the
values of the input signals, the level shifter circuit uses a set
of output drivers to provide output voltages accordingly. For
example, an output buffer circuit that receives input signals
ranging from 0 V to 0.7 V output is capable of providing output
signals ranging from 0 V to 3.3 V, accordingly.
[0006] The present disclosure describes a level shifter circuit
having improved characteristics in low to high voltage transition
operations.
SUMMARY OF INVENTION
[0007] In accordance with a preferred embodiment of the present
invention, a level shifter circuit includes a first level shifter
circuit and a second level shifter circuit.
[0008] The first level shifter circuit and the second level shifter
circuit are substantially identical with each other. The second
level shifter circuit is coupled to the first level shifter circuit
via a couple of transistors to provide an output and a
complementary output, respectively.
[0009] All objects, features, and advantages of the present
invention will become apparent in the following detailed written
description.
BRIEF DESCRIPTION OF DRAWINGS
[0010] The invention itself, as well as a preferred mode of use,
further objects, and advantages thereof, will best be understood by
reference to the following detailed description of an illustrative
embodiment when read in conjunction with the accompanying drawings,
wherein:
[0011] FIG. 1 is a circuit diagram of a level shifter circuit
according to the prior art; and
[0012] FIG. 2 is a circuit diagram of a level shifter circuit in
accordance with a preferred embodiment of the present
invention.
DETAILED DESCRIPTION
[0013] Referring now to the drawings, and in particular, to FIG. 1,
there is depicted a circuit diagram of a level shifter circuit
according to the prior art. As shown, a level shifter circuit 10
includes a p-channel transistor 11 and a p-channel transistor 12
having its respective source connected to a power source V.sub.DD2.
Also, the drain of p-channel transistor 11 is connected to the
source of a p-channel transistor 13, and the drain of p-channel
transistor 12 is connected to the source of a p-channel transistor
14. The drain of p-channel transistor 13 is connected to the gate
of p-channel transistor 12 and to the drain of an n-channel
transistor 15. The drain of p-channel transistor 14 is connected to
the gate of p-channel transistor 11 and to the drain of an
n-channel transistor 16. Both the source of n-channel transistor 15
and the source of n-channel transistor 16 are connected to
ground.
[0014] An input signal IN is fed to the gate of p-channel
transistor 13 and to the gate of n-channel transistor 15 while a
complementary input signal /IN is fed to the gate of p-channel
transistor 14 and to the gate of n-channel transistor 16. An output
signal OUT can be extracted from the drain of p-channel transistor
14 and the drain of n-channel transistor 16. Similarly, an
complementary output signal /OUT can be extracted from the drain of
p-channel transistor 13 and the drain of n-channel transistor
15.
[0015] Level shifter circuit 10 converts an input signal IN having
a voltage amplitude ranging from 0 to V.sub.DD1 into an output
signal OUT having a voltage amplitude ranging from 0 to V.sub.DD2.
During operation, when the electric potential of the input signal
IN is at a logical high of V.sub.DD1, n-channel transistor 15 is
turned on and p-channel transistor 13 is turned off, the electric
potential of 0 V (i.e., logical low) is fed to the gate of
p-channel transistor 12 to turn p-channel transistor 12 on. On the
other hand, the electric potential of the complementary input
signal /IN is at a logical low of 0 V, and thus n-channel
transistor 16 is turned off while p-channel transistor 14 is turned
on. Therefore, both p-channel transistors 12 and 14 are turned on
and the electric potential is shifted such that the output signal
OUT becomes V.sub.DD2. It is to be noted that p-channel transistor
11 is turned off to ensure that the gate of p-channel transistor 12
is held at a logical low of GND.
[0016] In contrast, when the electric potential of the input signal
IN to level shifter circuit 10 is at a logical low of 0 V, the
electric potential of 0 V occurs at output OUT. Accordingly, an
input signal having a voltage amplitude of 0 to V.sub.DD1 can be
converted to an output signal having a voltage amplitude of 0 to
V.sub.DD1.
[0017] Level shifter circuit 10 can easily perform voltage level
conversions between voltage amplitudes having small differences.
However, as the difference between voltage amplitudes becomes
larger and as V.sub.DD1 approaches the threshold voltage of
n-channel transistors, it becomes more difficult for level shifter
circuit 10 to perform voltage level conversions, resulting in
problems as follows.
[0018] Assume V.sub.DD1 and V.sub.DD2 of level shifter circuit 10
to be 1.2 V and 5.0. Also assume the threshold voltages of
p-channel transistors 11-14 are -0.9 V, and threshold voltages of
n-channel transistors 15-16 are 0.9 V. Under such conditions in a
steady state of a normal operating condition, if the electric
potential of the input signal IN is changed from a logical low of 0
V to a logical high of 1.2 V, then the voltage between the gate and
the source of n-channel transistor 15 exceeds the threshold voltage
of n-channel transistor 15, thereby turning n-channel transistor 15
on. In addition, because the source electric potential of p-channel
transistor 13 is initially 5 V, the voltage between the gate and
the source p-channel transistor 13 is -4.1 V, which exceeds the
threshold voltage of p-channel transistor 13. Thus, p-channel
transistor 13 is turned on. P-channel transistor 11 is also turned
on initially, and therefore a penetrating current flows between the
voltage source V.sub.DD2 and GND through p-channel transistors 11,
13 and n-channel transistor 15. Such condition continues as long as
either p-channel transistor 11 or p-channel transistor 13 is not
turned off.
[0019] Furthermore, as the voltage of voltage source V.sub.DD1 gets
closer to the threshold voltage of a n-channel transistor, the
drive strength of the n-channel transistor dramatically decreases
in accordance with the various process and temperature conditions.
As a result, the effectiveness of level shifter circuit 10 is
reduced.
[0020] With reference now to FIG. 2, there is depicted a circuit
diagram of a level shifter circuit, in accordance with a preferred
embodiment of the present invention.
[0021] As shown, a level shifter circuit 20 includes a primary
level shifter circuit and a secondary level shifter circuit. The
primary level shifter circuit includes p-channel transistors 21-24
and n-channel transistors 25-26. The secondary level shifter
circuit includes p-channel transistors 31-34 and n-channel
transistors 35-36. The primary level shifter circuit is coupled to
the secondary level shifter circuit via n-channel transistors
27-28.
[0022] For the primary level shifter circuit, both the source of
p-channel transistor 21 and the source of p-channel transistor 22
are connected to a power source V.sub.DD2. Also, the drain of
p-channel transistor 21 is connected to the source of p-channel
transistor 23, and the drain of p-channel transistor 22 is
connected to the source of p-channel transistor 24. The drain of
p-channel transistor 23 is connected to the gate of p-channel
transistor 22, the drain of n-channel transistor 25 and the drain
of n-channel transistor 28. The drain of p-channel transistor 24 is
connected to the gate of p-channel transistor 21, the drain of
n-channel transistor 26 and the drain of n-channel transistor 27.
The sources of n-channel transistors 25-28 are all connected to
ground.
[0023] For the secondary level shifter circuit, both the source of
p-channel transistor 31 and the source of p-channel transistor 33
are connected to power source V.sub.DD2. The drain of p-channel
transistor 31 is connected to the source of p-channel transistor
33, and the drain of p-channel transistor 33 is connected to the
source of p-channel transistor 34. The drain of p-channel
transistor 33 is connected to the drain of n-channel transistor 35,
the gate of p-channel transistor 32 and the gate of n-channel
transistor 27. The drain of p-channel transistor 34 is connected to
the drain of n-channel transistor 36, the gate of p-channel
transistor 31 and the gate of n-channel transistor 28. The sources
of n-channel transistors 35-36 are connected to ground.
[0024] An input signal IN can be fed to the gates of p-channel
transistors 23, 33 and the gates of n-channel transistors 25, 35
while a complementary input signal /IN can be fed to the gates of
p-channel transistors 24, 34 and the gates of n-channel transistors
26, 36 to extract an output signal OUT from the drain of n-channel
transistor 27. Similarly, an complementary output signal /OUT can
be extracted from the drain of n-channel transistor 28.
[0025] For level shifter circuit 20, input signals IN switch from 0
V to V.sub.DD1 and output signals OUT switch from 0 V to V.sub.DD2,
accordingly. V.sub.DD1 is generally less than V.sub.DD2. For
example, V.sub.DD1 equals 0.7 V and V.sub.DD2 equals 3.3 V.
[0026] When input signal IN switches from a logical 0 to a logical
1, transistors 25, 35 are turned on, and transistors 23, 33 are
turned off. In turn, transistors 22 and 32 are turned on. On the
other hand, transistors 24, 34 are turned on, and transistors 26,
36 are turned off. Consequently, transistors 21 and 31 are turned
off. Thus, transistor 27 is turned off and transistor 28 is turned
on. As a result, a logical 1 (i.e., V.sub.DD2) occurs at output
OUT, and a logical 0 (i.e., GND) occurs at complementary output
/OUT.
[0027] When input signal IN switches from a logical 1 to a logical
0, transistors 25, 35 are turned off, and transistors 23, 33 are
turned on. In turn, transistors 22 and 32 are turned off. On the
other hand, transistors 24, 34 are turned off, and transistors 26,
36 are turned on. Consequently, transistors 21 and 31 are turned
on. Thus, transistor 27 is turned on and transistor 28 is turned
off. As a result, a logical 0 (i.e., GND) occurs at output OUT, and
a logical 1 (i.e., V.sub.DD2) occurs at complementary output
/OUT.
[0028] As has been described, the present invention provides a
level shifter circuit having improved characteristics in low to
high voltage transition operations. The primary advantage of the
present invention is that output transistors, such as n-channel
transistors 27 and 28, are able to receive a full V.sub.DD2 voltage
at their respective gates, which can increase their drive
strength.
[0029] While the invention has been particularly shown and
described with reference to a preferred embodiment, it will be
understood by those skilled in the art that various changes in form
and detail may be made therein without departing from the spirit
and scope of the invention.
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