U.S. patent application number 10/839512 was filed with the patent office on 2004-10-21 for semiconductor integrated circuit.
Invention is credited to Kimura, Ryohei.
Application Number | 20040207455 10/839512 |
Document ID | / |
Family ID | 19041177 |
Filed Date | 2004-10-21 |
United States Patent
Application |
20040207455 |
Kind Code |
A1 |
Kimura, Ryohei |
October 21, 2004 |
Semiconductor integrated circuit
Abstract
A discriminating method for a trimming error is provided. A fuse
is connected between an output terminal and a terminal having a
potential at a VDD or VSS level, and an output voltage at the time
of the trimming error is fixed. Alternatively, when the trimming
error occurs, short circuit is established between VDD and VSS, and
a large current is made to flow, thereby making error detection
easy.
Inventors: |
Kimura, Ryohei; (Chiba-shi,
JP) |
Correspondence
Address: |
Bruce L. Adams
Adams & Wilks
31st Floor
50 Broadway
New York
NY
10004
US
|
Family ID: |
19041177 |
Appl. No.: |
10/839512 |
Filed: |
May 5, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10839512 |
May 5, 2004 |
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10188685 |
Jul 3, 2002 |
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6774702 |
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Current U.S.
Class: |
327/525 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 23/5258 20130101; G11C 17/165 20130101; G11C 29/50008
20130101; G11C 29/028 20130101; G11C 17/18 20130101; G11C 29/02
20130101; G11C 29/027 20130101; H01L 2924/0002 20130101; G11C 17/16
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
327/525 |
International
Class: |
H01H 037/76 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 5, 2001 |
JP |
2001-204757 |
Claims
1.-9. (canceled).
10. A CMOS circuit, comprising: a CMOS circuit; a MOS transistor
connected to the CMOS circuit and having a source terminal, a gate
terminal, and a drain terminal, the source terminal being connected
to a power supply voltage and the gate terminal being connected to
a test signal terminal; and a fuse element having one end connected
to the drain terminal and another end connected to an output
terminal of the CMOS circuit.
11. A CMOS circuit according to claim 10; wherein the power supply
voltage to which the source terminal is connected is a negative
power supply voltage.
12. A CMOS circuit according to claim 10; wherein the power supply
voltage to which the source terminal is connected is a positive
power supply voltage.
13. A CMOS circuit, comprising: a CMOS circuit; a MOS transistor
connected to the CMOS circuit and having a source terminal, a gate
terminal, and a drain terminal, the drain terminal being connected
to an output terminal of the CMOS circuit and the gate terminal
being connected to a test signal terminal; and a fuse element
having one end connected to the source terminal and another end
connected to a power supply voltage.
14. A CMOS circuit according to claim 13; wherein the power supply
voltage to which the fuse element is connected is a negative power
supply voltage.
15. A CMOS circuit according to claim 13; wherein the power supply
voltage to which the fuse element is connected is a positive power
supply voltage.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor integrated
circuit for discriminating trimming failure.
[0003] 2. Description of the Related Art
[0004] An example of conventional trimming is shown in FIG. 8. The
conventional trimming is then described. In FIG. 8, the resistance
between a terminal 811 and a negative power supply VSS corresponds
to a resistance 841 by cutting a fuse 821. Further, if the fuse 821
is not cut, the resistance between the terminal 811 and the
negative power supply VSS corresponds to a combined resistance of
the resistance 841 and a resistance 842. A voltage of the terminal
811 of the circuit in FIG. 8 is controlled by the resistance ratio
to a resistance 843.
[0005] In the conventional trimming, a non-conforming article is
generally provided if trimming is not performed. However, there is
a possibility that a conforming article is provided without
performing trimming depending on a range of an efficiency voltage
of a test. In this case, even if laser is radiated to the position
off the fuse so that trimming fails to be performed because of
positional deviation of trimming alignment, or the like, the
conforming article may be provided at the time of the test. In
addition, there is a fear that the radiation of laser to the wrong
position affects long-term reliability, and thus, the
non-conforming article has to be correctly discriminated.
SUMMARY OF THE INVENTION
[0006] In order to solve the above-described problems, an object of
the present invention is to provide a semiconductor integrated
circuit having a structure in which a dummy fuse is used to
discriminate failure in accordance with an output thereof in the
case of a trimming error. The semiconductor integrated circuit as
structured above has a strong point in that success or failure of
trimming can be discriminated in accordance with whether the output
is fixed to VSS or VDD or not. Further, such a structure is adopted
in which, if trimming is not performed, short circuit is
established between positive and negative power supply voltages,
whereby the success or failure of trimming can be discriminated by
examining a consumption current.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In the accompanying drawings:
[0008] FIG. 1 is a structural diagram of a CMOS circuit of the
present invention;
[0009] FIG. 2 is a structural diagram of a CMOS circuit of the
present invention;
[0010] FIG. 3 is a structural diagram of a CMOS circuit of the
present invention;
[0011] FIG. 4 is a structural diagram of a CMOS circuit of the
present invention;
[0012] FIG. 5 is a structural diagram of a CMOS circuit of the
present invention;
[0013] FIG. 6 is a structural diagram of a CMOS circuit of the
present invention;
[0014] FIG. 7 is a structural diagram of a CMOS circuit of the
present invention;
[0015] FIG. 8 shows an example of a structural diagram of a
conventional trimming mechanism;
[0016] FIG. 9 is a layout example of a trimming mechanism of the
present invention;
[0017] FIG. 10 is a circuit diagram of the trimming mechanism of
the present invention; and
[0018] FIG. 11 is a layout example of a trimming mechanism of the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] Hereinafter, embodiments of the present invention will be
described with reference to the accompanying drawings. FIGS. 1 to 7
show examples of a structure of a CMOS circuit according to the
present invention.
[0020] FIG. 1 is a diagram showing an embodiment of the present
invention, in which one end of a fuse 121 is connected between an
output of a CMOS circuit 100 and an output terminal 111, and
another end of the fuse 121 is connected to a transistor 131. In
FIG. 1, if trimming is correctly performed, the fuse 121 is cut,
and a potential of the output terminal 111 is determined by the
CMOS circuit 100. In the case where trimming failure occurs, when a
signal is input to a test terminal 112 to make the transistor 131
conductive, the output terminal 111 is connected to a negative
power supply voltage VSS via the fuse 121, and thus, the potential
of the output terminal 111 becomes VSS. Therefore, a trimming error
is detected.
[0021] FIG. 2 is a diagram showing another embodiment of the
present invention, in which one end of a fuse 221 is connected
between an output of a CMOS circuit 200 and an output terminal 211,
and another end of the fuse 221 is connected to a transistor 231.
In FIG. 2, if trimming is correctly performed, the fuse 221 is cut,
and a potential of the output terminal 211 is determined by the
CMOS circuit 200. In the case where trimming failure occurs, when a
signal is input to a test terminal 212 to make the transistor 231
conductive, the output terminal 211 is connected to a positive
power supply voltage VDD via the fuse 221, and thus, the potential
of the output terminal 211 becomes VDD. Therefore, a trimming error
is detected.
[0022] FIG. 3 is a diagram showing another embodiment of the
present invention, in which a transistor 331 and a fuse 321 are
connected in series between an output of a CMOS circuit 300 and an
output terminal 311. In FIG. 3, if trimming is correctly performed,
the fuse 321 is cut, and a potential of the output terminal 311 is
determined by the CMOS circuit 300. In the case where trimming
failure occurs, when a signal is input to a test terminal 312 to
make the transistor 331 conductive, the output terminal 311 is
connected to a negative power supply voltage VSS via the fuse 321,
and thus, the potential of the output terminal 311 becomes VSS.
Therefore, a trimming error is detected.
[0023] FIG. 4 is a diagram showing another embodiment of the
present invention, in which a transistor 431 and a fuse 421 are
connected in series between an output of a CMOS circuit 400 and an
output terminal 411. In FIG. 4, if trimming is correctly performed,
the fuse 421 is cut, and a potential of the output terminal 411 is
determined by the CMOS circuit 400. In the case where trimming
failure occurs, when a signal is input to a test terminal 412 to
make the transistor 431 conductive, the output terminal 411 is
connected to a positive power supply voltage VDD via the fuse 421,
and thus, the potential of the output terminal 411 becomes VDD.
Therefore, a trimming error is detected.
[0024] In FIG. 5, if trimming is correctly performed, a fuse 521 is
cut, and a current does not flow through a transistor 531. In the
case where trimming failure occurs, when a signal is input to a
test terminal 512 to make the transistor 531 conductive, a through
current flows. Therefore, a trimming error is detected.
[0025] In FIG. 6, if trimming is correctly performed, a fuse 621 is
cut, and a current does not flow through a transistor 631. In the
case where trimming failure occurs, when a signal is input to a
test terminal 612 to make the transistor 631 conductive, a through
current flows. Therefore, a trimming error is detected.
[0026] In FIG. 7, if trimming is correctly performed, a fuse 721 or
a fuse 722 is cut, and a through current does not flow through
transistors 731 and 732. In the case where trimming failure occurs,
when signals are input to test terminals 712 and 713 to make the
transistors 731 and 732 conductive, respectively, a through current
flows. Therefore, a trimming error is detected.
[0027] FIG. 9 and FIG. 10 are a layout example and a circuit
diagram corresponding thereto, respectively. In FIG. 9, laser
trimming is conducted in accordance with an alignment 951. If
trimming is correctly performed to main fuses 921 and 922, a fuse
for error detection 923 is also necessarily cut. On the contrary,
in the case where the trimming of the main fuses 921 and 922 is not
correctly performed since laser trimming is not performed in
accordance with the alignment because of the existence of
impurities, or the like, the fuse for error detection is not cut as
well. Therefore, a trimming error is detected.
[0028] Also, in the case where positional deviation occurs when a
plurality of chips are aligned with one alignment as shown in FIG.
11, success or failure of trimming of the main fuse is judged by
the fuse for error detection.
[0029] The present invention is implemented in accordance with the
embodiment described above, and provides the following effects: the
output terminal voltage is fixed to the power supply voltage when
trimming failure occurs; the detection of the trimming error is
facilitated by flowing a large current; and thus, the
discrimination of the circuit in which trimming has not been
correctly performed is enabled.
* * * * *