U.S. patent application number 10/838384 was filed with the patent office on 2004-10-14 for implementation of si-ge hbt module with cmos process.
This patent application is currently assigned to LSI Logic Corporation. Invention is credited to Allman, Derryl J., Banerjee, Robi, Price, David T..
Application Number | 20040203212 10/838384 |
Document ID | / |
Family ID | 30114200 |
Filed Date | 2004-10-14 |
United States Patent
Application |
20040203212 |
Kind Code |
A1 |
Banerjee, Robi ; et
al. |
October 14, 2004 |
Implementation of Si-Ge HBT module with CMOS process
Abstract
A semiconductor device wherein Si-Ge is the base of a bipolar
transistor and a Silicon layer is the emitter. A method of making
such a semiconductor device including steps of forming a Silicon
dioxide layer on a Silicon substrate, using a photo resist
application and exposure to define where a HBT device will be
placed. Plasma etching the Silicon dioxide layer to define an
undercut, epitaxially growing an Si-Ge layer and a Silicon layer,
and continuing manufacture to form one or more bipolar and CMOS
devices and define interconnect and passivation.
Inventors: |
Banerjee, Robi; (Gresham,
OR) ; Allman, Derryl J.; (Camas, WA) ; Price,
David T.; (Gresham, OR) |
Correspondence
Address: |
LSI LOGIC CORPORATION
1621 BARBER LANE
MS: D-106 LEGAL
MILPITAS
CA
95035
US
|
Assignee: |
LSI Logic Corporation
Milpitas
CA
|
Family ID: |
30114200 |
Appl. No.: |
10/838384 |
Filed: |
May 4, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10838384 |
May 4, 2004 |
|
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10191670 |
Jul 9, 2002 |
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6767842 |
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Current U.S.
Class: |
438/312 ;
257/197; 257/E21.371; 257/E21.696; 257/E27.015 |
Current CPC
Class: |
H01L 29/66242 20130101;
H01L 27/0623 20130101; H01L 21/8249 20130101 |
Class at
Publication: |
438/312 ;
257/197 |
International
Class: |
H01L 031/0328; H01L
031/072 |
Claims
What is claimed is:
1. A semiconductor device comprising: a Silicon substrate; Si-Ge on
the Silicon substrate; and Silicon on the Si-Ge, wherein the Si-Ge
forms the base of a bipolar transistor and the Silicon on the Si-Ge
forms the emitter of the bipolar transistor.
2. A semiconductor device as defined in claim 1, wherein said
semiconductor device includes a Silicon region which does not
include any Si-Ge, and includes a Si-Ge region which includes Si-Ge
on the Silicon substrate.
3. A semiconductor device as defined in claim 3, wherein said
Silicon region includes an oxide layer and said Si-Ge region does
not include an oxide layer.
4. A semiconductor device as defined in claim 1, wherein said
semiconductor device includes a layer of Silicon dioxide on the
Silicon substrate, said layer of Silicon dioxide having an exposed
area in which the Si-Ge is disposed.
5. A semiconductor device as defined in claim 1, wherein said
semiconductor device includes a Silicon region which does not
include any Si-Ge, and includes a Si-Ge region which includes Si-Ge
on the Silicon substrate, further comprising a Silicon layer in
said Si-Ge region, wherein the Si-Ge on the Silicon substrate forms
a Si-Ge layer, said Silicon layer being disposed on the Si-Ge
layer, said Si-Ge layer being disposed between said Silicon
substrate and said Silicon layer in said Si-Ge region.
6. A method of making a semiconductor device comprising: providing
a Silicon substrate; depositing Si-Ge on the Silicon substrate;
depositing Silicon on the Si-Ge; providing that said semiconductor
device is configured such that the Si-Ge forms the base of a
bipolar transistor and the Silicon on the Si-Ge forms the emitter
of the bipolar transistor.
7. A method as defined in claim 6, further comprising forming a
Silicon dioxide layer on the Silicon substrate.
8. A method as defined in claim 7, further comprising masking at
least a portion of the oxide layer which is disposed on the Silicon
substrate to define an implant well.
9. A method as defined in claim 8, further comprising masking and
implanting dopant to form a collector region of the bipolar
transistor.
10. A method as defined in claim 9, removing at least a portion of
the Silicon dioxide layer which is disposed on the Silicon
substrate in order to expose a portion of the Silicon substrate and
create an undercut.
11. A method as defined in claim 10, further comprising forming a
Si-Ge layer on the exposed portion of the Silicon substrate.
12. A method as defined in claim 11, further comprising forming a
Silicon layer on the Si-Ge layer which is disposed on the Silicon
substrate.
13. A method as defined in claim 10, wherein the step of removing
at least a portion of the Silicon dioxide layer comprises wet
etching the portion of the Silicon dioxide layer.
14. A method as defined in claim 11, wherein the step of forming a
Si-Ge layer on the exposed portion of the Silicon substrate
comprises epitaxially growing the Si-Ge layer.
15. A method as defined in claim 12, wherein the step of forming a
Silicon layer on the Si-Ge layer comprises epitaxially growing the
Silicon layer.
16. A method as defined in claim 6, further comprising masking and
implanting dopant to define base and emitter regions of the bipolar
transistor.
Description
BACKGROUND
[0001] The present invention generally relates to semiconductor
process integration, and more specifically relates to a
semiconductor device which has Si-Ge on Silicon and a layer of
Si-Ge forms the base of a bipolar transistor and a layer of Silicon
on the layer of Si-Ge forms the emitter of the bipolar transistor,
and a method of making a semiconductor device where the method
includes depositing Si-Ge on Silicon, and the method provides that
a layer of Si-Ge forms the base of a bipolar transistor and a layer
of Silicon on the layer of Si-Ge forms the emitter of the bipolar
transistor.
[0002] The semiconductor industry has been constantly striving to
improve the data transfer speed for communications using
silicon-based semiconductor devices (i.e., semiconductor products).
To date, various schemes and improvements have been proposed, both
in the area of process technology and circuit design, in order to
handle the higher frequencies required for data transmission with
lower power consumption.
[0003] Present semiconductor devices are typically configured such
that FET transistors and other devices, such as speed-performance
sensitive parts of a circuit, are disposed on Silicon. As such,
carrier flow is not forced to a surface channel region. This causes
short channel effects, thereby resulting in leakage and/or
increased power consumption. Additionally, as transistor sizes
shrink, the electron hole carrier mobility and the device noise
needs to be improved to provide adequate performance and circuit
design margin.
OBJECTS AND SUMMARY
[0004] A general object of an embodiment of the present invention
is to provide a semiconductor device which has at least a region
that provides Si-Ge on Silicon and a Silicon layer on the Si-Ge,
where the semiconductor device is configured such that the Si-Ge
forms the base of a bipolar transistor and the Silicon on the Si-Ge
forms the emitter of the bipolar transistor.
[0005] Another object of an embodiment of the present invention is
to provide a method of making a semiconductor device, where the
method includes depositing Si-Ge on Silicon, and the method
provides that a layer of Si-Ge forms the base of a bipolar
transistor and a layer of Silicon on the layer of Si-Ge forms the
emitter of the bipolar transistor.
[0006] Still another object of an embodiment of the present
invention is to provide a method of making semiconductor device
which eliminates processing steps which are typically required to
form an emitter over the base region.
[0007] Still yet another object of an embodiment of the present
invention is to provide a semiconductor device which includes a
strained silicon layer which provides increased mobility of
electrons through the base.
[0008] Yet still another object of an embodiment of the present
invention is to provide a semiconductor device which has a thin
base region with a high dopant concentration and abrupt doping
profiles.
[0009] Another object of an embodiment of the present invention is
to provide a semiconductor device which provides retardation in
dopant diffusion out fo the base region, caused by the
incorporation of dopants near the junction interfaces.
[0010] Another object of an embodiment of the present invention is
to provide a method of making a semiconductor device wherein oxygen
is incorporated into the base at the emitter to base junction to
increase barrier potential and subsequent emitter efficiency of the
device.
[0011] Another object of an embodiment of the present invention is
to provide a method of making a semiconductor device which consumes
less dynamic power due to a higher operating frequency.
[0012] Another object of an embodiment of the present invention is
to provide a method of making a semiconductor device which provides
that base contact is made by either tungsten plugs or by the use of
poly silicon.
[0013] Briefly, and in accordance with at least one of the forgoing
objects, an embodiment of the present invention provides a
semiconductor device which has at least a region where Si-Ge is
disposed on Silicon. Specifically, the semiconductor device
preferably includes Si-Ge disposed on a Silicon substrate. The
semiconductor device may include a Silicon region which does not
include any Si-Ge, but preferably also includes an Si-Ge region
which includes Si-Ge on Silicon. Preferably, the Si-Ge is provided
as an Si-Ge layer which is disposed between a Silicon layer and the
Silicon substrate, and the Si-Ge forms the base of a bipolar
transistor and the Silicon layer on the Si-Ge forms the emitter of
the bipolar transistor.
[0014] A method of making such a semiconductor device is also
provided, and includes steps of forming an oxide layer on a Silicon
substrate, masking at least a portion of the oxide layer to define
a deep collector implant and N well implants, Vt adjusting the
implant to define the CMOS (FET) devices, mask at least a portion
of the oxide layer and implant dopant to form a collector region of
a bipolar transistor, masking to define one or more selective areas
within a chip on which epitaxial Si-Ge and a Silicon layer will be
grown, removing (such as by wet etching) at least a portion of the
oxide layer in order to expose a portion of the Silicon substrate
and create an undercut in open areas defined by the previous
masking step, epitaxially growing an Si-Ge layer on the exposed
portion of the Silicon substrate, epitaxially growing a Silicon
layer on the Si-Ge layer, if regions are not doped then masking and
implanting dopant to define the base and emitter regions of the
bipolar transistor, and continuing manufacture of the device by
forming one or more bipolar and CMOS devices and continuing until
the end of the line to define interconnect and passivation.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The organization and manner of the structure and operation
of the invention, together with further objects and advantages
thereof, may best be understood by reference to the following
description, taken in connection with the accompanying drawings,
wherein like reference numerals identify like elements in
which:
[0016] FIG. 1 is a block diagram of a method which is in accordance
with an embodiment of the present invention; and
[0017] FIG. 2 is a general schematic view of a semiconductor device
illustrating one of the steps of the method shown in FIG. 1,
wherein layers of Silicon dioxide, Polysilicon (or Silicon
nitride), and Silicon nitride (or oxide) are disposed on a Silicon
substrate;
[0018] FIG. 3 is a general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 1,
wherein an area where an HBT device is to be formed is defined;
[0019] FIG. 4 is a general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 1,
wherein portions of layers are removed to expose an underlying
oxide layer;
[0020] FIG. 5 is a general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 1,
wherein sidewall spacers are formed;
[0021] FIG. 6 is a general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 1,
wherein oxide is removed to form an undercut;
[0022] FIG. 7 is a general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 1,
wherein an Si-Ge layer is formed and a layer of Silicon is formed
to provide a base and emitter, respectively;
[0023] FIG. 8 is a block diagram of a method which is in accordance
with another embodiment of the present invention;
[0024] FIG. 9 is general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 8,
wherein layers of Silicon dioxide and Silicon nitride are disposed
on a Silicon substrate;
[0025] FIG. 10 is general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 8,
wherein an area where an HBT device is to be formed is defined;
[0026] FIG. 11 is general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 8,
wherein a region of the Silicon dioxide layer is removed and an
undercut is formed; and
[0027] FIG. 12 is general schematic view of a semiconductor device
illustrating a subsequent step of the method shown in FIG. 8,
wherein an Si-Ge layer is formed and a layer of Silicon is formed
to provide a base and emitter, respectively.
DESCRIPTION
[0028] While the invention may be susceptible to embodiment in
different forms, there is shown in the drawings, and herein will be
described in detail, specific embodiments with the understanding
that the present disclosure is to be considered an exemplification
of the principles of the invention, and is not intended to limit
the invention to that as illustrated and described herein.
[0029] FIG. 1 illustrates, in block diagram form, a method 10 of
making a semiconductor device, and FIGS. 2-7 illustrate a
semiconductor device 20 being made in accordance with the steps
shown in FIG. 1. Both the method 10 of making the semiconductor
device 20 and the structure of the semiconductor device 20 itself
are embodiments of the present invention.
[0030] Generally, the method 10 shown in FIG. 1 includes the step
of depositing Si-Ge on Silicon. As a result, both an Si-Ge region
22 and a Silicon region 24 is formed on the semiconductor device 20
(see FIG. 7). This provides that speed performance sensitive parts
of the circuit may be built on the Si-Ge region(s) 22 within the
die, while non-speed sensitive designs or legacy designs on Silicon
may be implemented in the Silicon region(s) 24 on the chip. This is
done by integrating high performance vertical Bipolar transistors
in conjunction with high performance CMOS devices on the same chip.
While a graded Si-Ge layer forms the base of a bipolar transistor,
epitaxial Si grown on top of the graded Si-Ge layer forms the
emitter.
[0031] In addition to depositing Si-Ge on Silicon, Silicon is
deposited on the Si-Ge. Due to lattice mismatch between Si-Ge and
Silicon, the carrier mobility is improved, thereby improving the
performance of the semiconductor device. Additionally, the strain
causes the carriers to be restricted to the surface Silicon layer.
This improves short channel effects thereby reducing leakage and
therefore standby power consumption. The method 10 and the
semiconductor device 20 itself provides that the Si-Ge forms the
base of a bipolar transistor, while the Silicon on the Si-Ge forms
the emitter of the bipolar transistor. This structure offers
improved device performance because of the seamless crystal
transition from the collector to the emitter.
[0032] The method 10 shown in FIG. 1 provides that initially there
is standard CMOS process flow up to pattern zero mask layer to
define initial alignment marks (box 30 in FIG. 1). Then, a thermal
pad is grown and Silicon dioxide is screened (box 40 in FIG. 1)
thereby providing layers of oxide 32, Polysilicon (or Silicon
nitride) 34, and Silicon nitride (or oxide) 36 on a Silicon
substrate 38. Then, Field Isolation definition and subsequent
standard processing is continued (box 50 in FIG. 1). Then, regions
are defined and the collector, N-well and Vt regions are implanted
on the wafer (box 60 in FIG. 1). Then, the MOS transistors are
defined (Polysilicon gates with LDD implants, sidewall spacers and
source drain implants) (box 70 in FIG. 1). Then, a Silicon nitride
layer or any other hard masking material layer that will not
interact with a selective epitaxial deposition of Silicon Germanium
is deposited (box 80 in FIG. 1). Then, as shown in FIG. 2, a
photolithography process is used (hence, a mask 42 is typically
employed as shown in FIG. 3) to define the area 44 where an HBT
device is to be formed (over the collector region). Then, as shown
in FIG. 4, the Silicon nitride layer 36 and Polysilicon 34 is
plasma etched to expose the underlying oxide layer 32 (box 90 in
FIG. 1). Then, a Silicon nitride layer is deposited and then etched
(using a RIE etch) to leave sidewall spacers 46 on the sides of
Polysilicon layer as shown in FIG. 5 (see also FIG. 1, wherein box
100 corresponds to this step). Then, as shown in FIG. 6, a portion
of the oxide layer 32 is wet etched to remove the oxide and
undercut the Polysilicon layer (box 110 in FIG. 1). Then, as shown
in FIG. 7, selective epitaxial deposition is used to grow the
appropriately doped (preferably n-type for mobility and gain
reasons) Si-Ge layer for base region 52 (box 120 in FIG. 1) and
Silicon is deposited to provide an emitter 54, thereby providing an
HBT device which includes a Silicon substrate 38, a base 52, an
emitter 54, insulating sidewall spacers 46 and Polysilicon for base
contact. Then, the wafer is RTP annealed to activate the implants
and processing is continued to define interconnect wiring (box 130
in FIG. 1).
[0033] FIGS. 8-12 depict an alternative approach using Silicon
nitride 62 instead of layers of Polysilicon 34 and Silicon nitride
36, wherein contact to base is made by Tungsten plugs or other
metallic contacting material. Specifically, as shown in FIG. 9, a
thermal pad is grown and Silicon dioxide is screened on a Silicon
substrate 38, thereby providing layers of Silicon nitride 62 and
oxide 32 on the Silicon substrate 38 (box 200 in FIG. 8). Then, as
shown in FIG. 10, photolithography is used to define where a HBT
device will be placed and the layer of Silicon nitride 62 is etched
to expose the Silicon dioxide 32 (box 202 in FIG. 8) (area 63 in
FIG. 10). Then, as shown in FIG. 11, a region of Silicon dioxide 32
is wet etched to undercut the Silicon nitride 62 (box 204 in FIG.
8) (area 65 in FIG. 11). Then, as shown in FIG. 12, an Si-Ge base
72 and emitter 74 are grown/deposited (box 206 in FIG. 8), and the
process is continued to show the deposition of the intermetal
dielectric, tungsten plug (76) creation (to contact base 72 and
emitter 74), metal patterning and etch for contact to HBT device
(box 208 in FIG. 8). As shown in FIG. 12, preferably the device
includes an insulating material 78, such as Silicon nitride.
[0034] While embodiments of the present invention are shown and
described, it is envisioned that those skilled in the art may
devise various modifications of the present invention without
departing from the spirit and scope of the appended claims.
* * * * *