U.S. patent application number 10/826752 was filed with the patent office on 2004-10-07 for method for forming a wafer level chip scale package, and package formed thereby.
This patent application is currently assigned to ADVANPACK SOLUTIONS PTE. LTD.. Invention is credited to Alvarez, Romeo Emmanuel P..
Application Number | 20040198022 10/826752 |
Document ID | / |
Family ID | 33101996 |
Filed Date | 2004-10-07 |
United States Patent
Application |
20040198022 |
Kind Code |
A1 |
Alvarez, Romeo Emmanuel P. |
October 7, 2004 |
Method for forming a wafer level chip scale package, and package
formed thereby
Abstract
A method for fabricating a chip scale package is described. The
method utilizes wafer level processes to obtain a chip level
package. The method particularly avoids the use of mechanical
grinding by the novel use of molding, extruding, and etching
technology.
Inventors: |
Alvarez, Romeo Emmanuel P.;
(Singapore, SG) |
Correspondence
Address: |
George O. Saile
28 Davis Avenue
Poughkeepsie
NY
12603
US
|
Assignee: |
ADVANPACK SOLUTIONS PTE.
LTD.
|
Family ID: |
33101996 |
Appl. No.: |
10/826752 |
Filed: |
April 16, 2004 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
10826752 |
Apr 16, 2004 |
|
|
|
10315534 |
Dec 10, 2002 |
|
|
|
6732913 |
|
|
|
|
10826752 |
Apr 16, 2004 |
|
|
|
09843248 |
Apr 26, 2001 |
|
|
|
6592019 |
|
|
|
|
Current U.S.
Class: |
438/460 ;
257/E23.021; 438/613 |
Current CPC
Class: |
H01L 2224/13144
20130101; H01L 2224/05568 20130101; H01L 2924/3511 20130101; H01L
2924/01046 20130101; H01L 24/03 20130101; H01L 24/16 20130101; H01L
2224/1147 20130101; H01L 24/13 20130101; H01L 2224/05023 20130101;
H01L 2924/00013 20130101; H01L 2924/01029 20130101; H01L 2924/01005
20130101; H01L 2224/1308 20130101; H01L 2924/01013 20130101; H01L
2924/01018 20130101; H01L 2224/73104 20130101; H01L 2224/136
20130101; H01L 23/3114 20130101; H01L 2224/13147 20130101; H01L
2924/01322 20130101; H01L 2924/01039 20130101; H01L 2224/1357
20130101; H01L 2924/01078 20130101; H01L 2924/181 20130101; H01L
2924/01033 20130101; H01L 24/05 20130101; H01L 2924/01022 20130101;
H01L 2924/15311 20130101; H01L 2224/16 20130101; H01L 2924/01015
20130101; H01L 24/11 20130101; H01L 2224/13082 20130101; H01L
2924/01079 20130101; H01L 2924/12042 20130101; H01L 2924/01074
20130101; H01L 2224/11901 20130101; H01L 2924/014 20130101; H01L
2224/05573 20130101; H01L 2924/14 20130101; H01L 2224/0508
20130101; H01L 2924/01006 20130101; H01L 2224/05001 20130101; H01L
2224/0557 20130101; H01L 2224/13144 20130101; H01L 2924/00014
20130101; H01L 2224/13147 20130101; H01L 2924/00014 20130101; H01L
2224/136 20130101; H01L 2924/014 20130101; H01L 2924/00013
20130101; H01L 2224/13099 20130101; H01L 2924/181 20130101; H01L
2924/00 20130101; H01L 2924/12042 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
438/460 ;
438/613 |
International
Class: |
H01L 021/301 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 10, 2001 |
SG |
200107810-4 |
Claims
What is claimed:
1. A method for forming a wafer level chip scale semiconductor
package, the method comprising the steps of: a) providing a
semiconductor wafer having a surface with a plurality of pads,
wherein each of the pads has a conductor extending a first
predetermined distance away from the surface; b) forming a layer of
conductive etch resistant material on free ends of the conductors;
c) disposing electrically insulating material on the surface of the
semiconductor wafer, wherein the layer of electrically insulating
material has an exposed surface a second predetermined distance
from the surface of the semiconductor wafer, wherein the second
predetermined distance is less than the first predetermined
distance, and wherein portions of the electrically insulating
material are disposed on the layer of conductive etch resistant
material and on side surfaces of at least some of the conductors;
and d) removing substantially all the portions of the electrically
insulating material disposed on the layer of conductive etch
resistant material and on the side surfaces of some of the
conductors.
2. A method in accordance with claim 1 further comprising the steps
of: e) disposing reflowable material on the conductive etch
resistant layer on the free ends of the conductors: and f)
reflowing the semiconductor wafer causing the feflowable material
to adhere to the conductive etch resistant layer and at least some
of the side surfaces of the conductors.
3. A method in accordance with claim 1 wherein step (b) comprises
the step of depositing the conductive etch resistant material on
the free ends of the conductors.
4. A method in accordance with claim 3 wherein step (b) comprises
the step of depositing gold.
5. A method in accordance with claim 3 wherein step (b) comprises
the step of depositing solder.
6. A method in accordance with claim 3 wherein step (b) comprises
the step of depositing a layer of nickel, and subsequently
depositing a layer of gold on the layer of nickel.
7. A method in accordance with claim 1 wherein step (b) comprises
the step of plating etch resistant material on the free ends of the
conductors.
8. A method in accordance with claim 1 wherein step (c) comprises
the step of dispensing the electrically insulating material with an
extrusion coating process.
9. A method in accordance with claim 1 wherein step (c) comprises a
single extruding step.
10. A method in accordance with claim 1 wherein step (c) comprises
the step of spin coating the layer of electrically insulating
material on the surface of the semiconductor wafer.
11. A method in accordance with claim 10 wherein step (c) comprises
the step of spin coating one of the coating materials from the
group including underfill coating materials and photo imageable
materials.
12. A method in accordance with claim 1 wherein step (c) comprises
the step of molding the layer of electrically insulating material
on the surface of the semiconductor wafer using release film.
13. A method in accordance with claim 1 wherein step (d) comprises
the step of plasma etching.
14. A method in accordance with claim 1 wherein step (d) comprises
the step of employing at least one laser for etching.
15. A method in accordance with claim 1 wherein step (d) comprises
the step of employing a media deflasher for etching.
16. A method in accordance with claim 1 wherein step (e) comprises
the step of printing deposits of solder.
17. A method in accordance with claim 1 further comprising, after
step (c) and before step (d), the step of curing the electrically
insulating material.
18. A method in accordance with claim 17, after step (c) and before
the step of curing the electrically insulating material, comprising
the step of cleaning the portions of the electrically insulating
material disposed on the layer of conductive etch resistant
material.
19. A method in accordance with claim 18 wherein the step of
cleaning comprises the step of: applying release film on the layer
of conductive etch resistant material; and removing the release
film.
20. A method in accordance with claim 18 wherein the step of
cleaning comprises the step of laser cleaning.
21. A wafer level chip scale package comprising; a semiconductor
die having a plurality of pads on a surface; conductors coupled to
and extending a first predetermined distance from the surface of
the semiconductor die; an etch resistant layer on free ends of the
conductors; a layer of insulation on the surface, the layer of
insulation having an exposed surface a second predetermined
distance from the surface of the semiconductor die, wherein the
second predetermined distance is less than the first predetermined
distance; and reflowable material attached to the etch resistant
layer and to at least portions of side surfaces of substantially
all of the conductors.
22. A wafer level chip scale package in accordance with claim 21
wherein the conductors comprise copper conductors.
23. A wafer level chip scale package in accordance with claim 22
wherein each of the copper conductors comprise a plurality of
plated copper layers.
24. A wafer level chip scale package in accordance with claim 21
wherein the etch resistant layer comprises a layer of gold.
25. A wafer level chip scale package in accordance with claim 21
wherein the etch resistant layer comprises a layer of nickel with a
layer of gold thereon.
26. A wafer level chip scale package in accordance with claim 25
wherein the thickness of the layer of gold is less than the
difference between the first predetermined distance and the second
predetermined distance.
27. A wafer level chip scale package in accordance with claim 21
wherein the layer of insulation comprises a material selected from
the group including mold compound, encapsulant epoxy, underfill
coating, and photo imageable material, such as benzocyclobutene
(BCB) or polyimide.
28. A wafer level chip scale package in accordance with claim 21
wherein the reflowable material comprises solder.
29. A wafer level chip scale package in accordance with claim 28
wherein the solder comprises eutectic solder.
30. A method for forming a wafer level chip scale semiconductor
package, the method comprising the steps of: (a) providing a
semiconductor wafer having a surface with a plurality of pads,
wherein each of the pads has a conductor extending a first
predetermined distance away from the surface; (b) disposing
reflowable material on free ends of the conductors; (c) disposing
electrically insulating material on the surface of the
semiconductor wafer, wherein the layer of electrically insulating
material has an exposed surface a second predetermined distance
from the surface of the semiconductor wafer, wherein the second
predetermined distance is greater than the first predetermined
distance; and (d) selectively removing at least a portion of the
electrically insulating material such that the exposed surface is a
third predetermined distance from the semiconductor wafer, wherein
the third predetermined distance is greater than the first
predetermined distance and less than the second predetermined
distance.
31. A method in accordance with claim 30 further comprising the
step of: (e) reflowing the semiconductor wafer causing the
reflowable material to melt and reform a surface having reduced
oxide thereon.
32. A method in accordance with claim 30 after step (a) and before
step (b) comprising the step of depositing conductive etch
resistant material on the free ends of the conductors, and wherein
step (b) comprises the step of disposing reflowable material on the
etch resistant material.
33. A method in accordance with claim 32 wherein the step of
depositing conductive etch resistant material comprises the step of
depositing gold.
34. A method in accordance with claim 30 after step (a) and before
step (b) comprising the step of plating etch resistant material on
the free ends of the conductors.
35. A method in accordance with claim 30 wherein step (b) comprises
the step of printing deposits of reflowable material on the free
ends of the conductors.
36. A method in accordance with claim 30 wherein step (b) comprises
the step of printing solder on the free ends of the conductors.
37. A method in accordance with claim 30 wherein step (b) comprises
the step of attaching solder balls to the free ends of the
conductors.
38. A method in accordance with claim 30 after step (b) comprising
the step of reflowing the semiconductor wafer.
39. A method in accordance with claim 30 wherein step (c) comprises
the step of dispensing the electrically insulating material using
an extrusion coating process.
40. A method in accordance with claim 30 wherein step (c) comprises
a single dispensing step.
41. A method in accordance with claim 30 wherein step (c) comprises
the step of spin coating the layer of electrically insulating
material on the surface of the semiconductor wafer.
42. A method in accordance with claim 41 wherein step (c) comprises
the step of spin coating a material selected from the group
consisting of underfill coating materials and photo imageable
materials.
43. A method in accordance with claim 30 wherein step (c) comprises
the step of molding the layer of electrically insulating material
on the surface of the semiconductor wafer using release film.
44. A method in accordance with claim 30 wherein step (d) comprises
the step of plasma etching.
45. A method in accordance with claim 30 wherein step (d) comprises
the step of employing at least one laser.
46. A method in accordance with claim 30 wherein step (d) comprises
the step of employing a media deflasher.
47. A method in accordance with claim 30 further comprising, after
step (c) and before step (d), the step of curing the electrically
insulating material.
48. A method in accordance with claim 30, after step (b) and before
step (d) comprising the step of cleaning the semiconductor
wafer.
49. A method in accordance with claim 48 wherein the step of
cleaning comprises the step of laser cleaning.
50. A wafer level chip scale package comprising: a semiconductor
die having a plurality of pads on a surface; conductors coupled to
and extending a first predetermined distance from the surface of
the semiconductor die; reflowable material attached to the free
ends of the conductors; and a layer of insulation on the surface of
the semiconductor die and surrounding the conductors, the layer of
insulation having an exposed surface a second predetermined
distance from the surface of the semiconductor die, wherein the
second predetermined distance is greater than the first
predetermined distance.
51. A wafer level chip scale package in accordance with claim 50
further comprising an etch resistant layer between the free ends of
the conductors and the reflowable material.
52. A wafer level chip scale package in accordance with claim 50
wherein the conductors comprise copper conductors.
53. A wafer level chip scale package in accordance with claim 52
wherein the copper conductors comprise a plurality of plated copper
layers.
54. A wafer level chip scale package in accordance with claim 51
wherein the etch resistant layer comprises a layer of gold.
55. A wafer level chip scale package in accordance with claim 51
wherein the etch resistant layer comprises a layer of solder.
56. A wafer level chip scale package in accordance with claim 50
wherein the layer of insulation comprises a material selected from
the group including mold compound, encapsulant epoxy, underfill
coating, and photo imageable material, such as benzocyclobutene
(BCB) or polyimide.
57. A wafer level chip scale package in accordance with claim 50
wherein the reflowable material comprises solder.
58. A wafer level chip scale package in accordance with claim 58
wherein the solder comprises eutectic solder.
Description
RELATED PATENT APPLICATION
[0001] This application is related to U.S. patent application Ser.
No. 09/564,382 by Francisca Tung filed on Apr. 27, 2000, and
Continuation-In-Part U.S. patent application Ser. No. 09/843,248 by
Francisca Tung filed on Apr. 26, 2001, and assigned to a common
assignee as the present invention.
FIELD OF THE INVENTION
[0002] The present invention relates to forming a wafer level chip
scale package, and more particularly to forming a wafer level chip
scale package that avoids mechanical grinding in the fabrication
process.
BACKGROUND OF THE INVENTION
[0003] The following two U.S. patents and U.S. patent publication
relate in general to the methods of fabrication of chip level
packages utilizing wafer level fabrication methods.
[0004] U.S. Pat. No. 6,072,236 dated Jun. 6, 2000, issued to S.
Akram et al. discloses a wafer level process utilizing
micromachining to fabricated chip scale packages.
[0005] U.S. Pat. No. 6,468,892B1 dated Oct. 22,2002, issued to M.
H. Baker et al. describes a method utilizing a solder mask at the
wafer level for forming bumps on chip scale packages.
[0006] U.S. patent application Publication US2002/002725A1 dated
Mar. 7, 2002, issued to L. D. Kinsman et al. describes a method for
fabricating a chip scale package utilizing wafer level
processing.
[0007] With a need for smaller semiconductor packages, there are
now processes for packaging of semiconductor integrated circuits,
or dies, at the wafer level. Such processes are commonly and
collectively referred to as wafer level chip scale packaging, and
the resultant package is referred to as a wafer level chip scale
package, (WL-CSP).
[0008] With reference to FIGS. 1 and 2A-E, an example of a wafer
level chip scale packaging process 100 is now described. After
components, circuitry and pads have been fabricated on a wafer 205
by processes, as will be known to one skilled in the art, the
packaging process 100 starts 105 with providing 110 the wafer 205
with metal pillars 210 formed on the die pads 212, or under bump
material. FIG. 2A shows the wafer 205 with the metal pillars 210
formed on the die pads 212.
[0009] U.S. patent application Ser. No. 09/564,382 by Francisca
Tung, filed on Apr. 27, 2000, titled "Improved Pillar Connections
for Semiconductor Chips and Method of Manufacture", and
Continuation-In-Part U.S. patent application Ser. No. 09/843,248 by
Francisca Tung filed on Apr. 26, 2001, titled "Improved Pillar
Connections for Semiconductor Chips and Method of Manufacture", and
assigned to a common assignee as this patent application, teaches
forming at least some of such pillar structures as described
herein. These patent applications are incorporated herein by
reference.
[0010] A layer of coating material 215 such as mold compound,
encapsulant epoxy, such as underfill coating material, or photo
imageable material, such as benzocyclobutene (BCB) or polyimide, is
then applied 115 over the wafer 205 with the metal pillars 210
covered by the coating material 215, as shown in FIG. 2B. The layer
of coating material 215 is applied with a spin coating process.
Typically, two layers of material each with a thickness of about
40-50 micrometers or microns (um) are applied to produce the
resulting layer of coating material 215 with a thickness of about
100 um. The coating material should be no more than 10 um thick on
the copper pillars 210, and the layer of coating material 213 is
then cured.
[0011] After curing, the excess coating material on the copper
pillars 210 is ground 120 away using mechanical grinding, employing
abrasive compounds on grinding machines, by Okamoto Corporation of
USA or Kemet International Limited of the UK, and using a poromeric
polishing pad. Grinding 120 continues until the excess coating
material is removed and the upper surfaces 220 of the copper
pillars 210 are exposed. The ground wafer is shown in FIG. 2C.
[0012] Next a layer of gold 225 is formed 125 on the upper surfaces
220 by, for example, electroplating, as shown in FIG. 2D; and
solder balls 230 are attached 130 to the layer of gold 225.
Equipment by manufacturers including OKI, Casio, Fujitsu, all of
Japan can be used to attach the solder balls. It will be
appreciated by those skilled in the art that a subsequent reflow
process causes the solder balls 230 to melt and adhere to the layer
of gold 225. The wafer level packaging process 100 then ends 135.
After the process 100, the bumped wafer 235 is diced to singulate
the WL-CSPs.
[0013] During the grinding step 120, the wafer 205 is subjected to
severe mechanical stress, and can result in micro-cracks in the
wafer. Hence, a disadvantage of the process of making WL-CSPs using
mechanical grinding is the potential of adverse reliability caused
by micro-cracks. Another disadvantage of mechanical grinding is
that grinding is slow. Yet another disadvantage is the need to
invest in grinding equipment and an associated supply of grinding
consumables.
[0014] Since only the upper surfaces of the layer of gold are
exposed, the surface area of the gold layer to which the solder
balls 230 can adhere is limited. Hence, another disadvantage is the
limited surface area of the layer of gold to which the solder balls
can adhere, as this can adversely affect the reliability of the
WL-CSP.
[0015] The spin coating process is slow, and in addition, two spin
coating operations are required to obtain a coating with the
required thickness. In addition, the spin coating process wastes
approximately 85% of the coating material that is disposed on the
wafer 205. Therefore, still another disadvantage of the process
described is the use of spin coating, which is both slow and
expensive.
BRIEF SUMMARY OF THE INVENTION
[0016] The present invention seeks to provide a method for forming
a wafer level chip scale package and a package formed thereby,
which overcomes or at least reduces the abovementioned problems of
the prior art.
[0017] Accordingly, in one aspect, the present invention provides a
method for forming a wafer level chip scale semiconductor package,
the method comprising the steps of:
[0018] providing a semiconductor wafer having a surface with a
plurality of pads, wherein each of the pads has a conductor
extending a first predetermined distance away from the surface;
[0019] forming a layer of conductive etch resistant material on
free ends of the conductors;
[0020] disposing electrically insulating material on the surface of
the semiconductor wafer, wherein the layer of electrically
insulating material has an exposed surface a second predetermined
distance from the surface of the semiconductor wafer, wherein the
second predetermined distance is less than the first predetermined
distance, and wherein portions of the electrically insulating
material are disposed on the layer of conductive etch resistant
material and on side surfaces of at least some of the conductors;
and
[0021] removing substantially all the portions of the electrically
insulating material disposed on the layer of conductive etch
resistant material and on the side surfaces of some of the
conductors.
[0022] In another aspect, the present invention provides a wafer
level chip scale package comprising:
[0023] a semiconductor die having a plurality of pads on a
surface;
[0024] conductors coupled to and extending a first predetermined
distance from the plurality of pads;
[0025] an etch resistant layer on free ends of the conductors;
[0026] a layer of insulation on the surface, the layer of
insulation having an exposed surface a second predetermined
distance from the surface, wherein the second predetermined
distance is less than the first predetermined distance; and
[0027] reflowable material adhering to the etch resistant layer and
to at least portions of side surfaces of substantially all of the
conductors.
[0028] In yet another aspect the present invention provides a
method for forming a wafer level chip scale semiconductor package,
the method comprising the steps of:
[0029] providing a semiconductor wafer having a surface with a
plurality of pads, wherein each of the pads has a conductor
extending a first predetermined distance away from the surface;
[0030] disposing reflowable material on free ends of the
conductors;
[0031] disposing electrically insulating material on the surface of
the semiconductor wafer, wherein the layer of electrically
insulating material has an exposed surface a second predetermined
distance from the surface of the semiconductor wafer, wherein the
second predetermined distance is greater than the first
predetermined distance; and
[0032] selectively removing at least a portion of the electrically
insulating material such that the exposed surface is a third
predetermined distance from the semiconductor wafer, wherein the
third predetermined distance is greater than the first
predetermined distance and less than the second predetermined
distance.
[0033] In still another aspect the present invention provides a
wafer level chip scale package comprising:
[0034] a semiconductor die having a plurality of pads on a
surface;
[0035] conductors coupled to and extending a first predetermined
distance from the surface of the semiconductor die;
[0036] reflowable material attached to the free ends of the
conductors; and
[0037] a layer of insulation on the surface of the semiconductor
die and surrounding the conductors, the layer of insulation having
an exposed surface a second predetermined distance from the surface
of the semiconductor die, wherein the second predetermined distance
is greater than the first predetermined distance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0038] An embodiment of the present invention will now be fully
described, by way of example with reference to the drawings of
which:
[0039] FIG. 1 shows a flowchart detailing a process for forming a
WL-CSP in accordance with the prior art;
[0040] FIGS. 2A-E show cross-sectional views of the WL-CSP being
formed in accordance with the process in FIG. 1;
[0041] FIG. 3 shows a flowchart detailing a process for forming a
WL-CSP in accordance with the present invention;
[0042] FIGS. 4A-E show cross-sectional views of the WL-CSP being
formed in accordance with the process in FIG. 3;
[0043] FIGS. 5-7 show enlarged cross-sectional views of a portion
of the WL-CSP being formed in FIGS. 4C-E;
[0044] FIG. 8 shows a cross-sectional view of film placed on the
semiconductor wafer as part of enhancing the process in FIG. 3;
[0045] FIG. 9 shows a flowchart detailing an alternate process for
forming a WL-CSP in accordance with the present invention;
[0046] FIGS. 10A-D show cross-sectional views of a WL-CSP being
formed in accordance with the process in FIG. 9; and
[0047] FIGS. 11-12 show enlarged cross-sectional views of a portion
of the WL-CSP being formed in FIGS. 10C-D.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0048] A layer of gold is disposed on upper surfaces of copper
pillars on a wafer. Coating material is then applied on the wafer
with an extrusion process, where the coating material forms a layer
at a lower level relative to the height of the copper pillars,
leaving the copper pillars protruding above the upper surface of
the coating material. Etchant is disposed to remove the portions of
coating material on the layer of gold and the portions of coating
material adhering to side surfaces of the protruding copper
pillars. Solder deposits are then disposed on the layer of gold on
the copper pillars, and the assembly is reflowed. The solder
deposits form balls on the layer of gold on the copper pillars,
with the copper pillars protruding into the solder balls. Hence,
the solder balls adhere to the layer of gold and in addition, the
solder balls advantageously also adhere to the side surface of the
copper pillars.
[0049] With reference to FIG. 3 and FIGS. 4A-E, a process 300 of
forming a WL-CSP in accordance with the present invention, starts
305 with providing 310 a semiconductor wafer 205 with copper
pillars 210 extending from die pads 212 on the semiconductor wafer
205, as shown in FIG. 4A. As mentioned earlier, U.S. patent
application Ser. No. 09/564,382 by Francisca Tung, filed on Apr.
27, 2000, titled "Improved Pillar Connections for Semiconductor
Chips and Method of Manufacture:, and Continuation-In-Part U.S.
patent application Ser. No. 09/843,248 by Francisca Tung, filed on
Apr. 26, 2001, titled "Improved Pillar Connections for
Semiconductor Chips and Method of Manufacture", and assigned to a
common assignee as the present patent application, teaches forming
at least some of such pillar structures as described herein. These
patent applications are incorporated herein by reference.
[0050] A layer of gold 405 is then formed 315 on the upper surfaces
225 of the copper pillars 210, as shown in FIG. 4B. The layer of
gold 405 is often referred to as gold flash, and can be formed
using deposition, as will be known to one skilled in the art. The
layer of gold provides a conductive etch resistant layer to prevent
the copper pillars from being etched by etchant in a subsequent
etching process.
[0051] Alternatively, a layer of nickel can be first formed on the
upper surfaces 225 of the copper pillars 210, and a layer of gold
formed on the layer of nickel. The layer of nickel forms a barrier
to prevent diffusion of gold into the copper, in the event the
etching process removes portions of the layer of gold and/or
diffusion of the gold into the copper pillars 210, leaves the
copper pillars 210 exposed. When the layer of nickel is used, then
the reference "405" in the drawings refers to the two layers of
nickel and gold forming a conductive etch resistant layer. Yet
another alternative is forming a layer of solder on the upper
surfaces 225 of the copper pillars 210, where the layer of solder
provides a conductive etch resistant layer to prevent the copper
pillars 210 from being etched by etchant in the subsequent etching
process. In addition, the layer of solder advantageously enhances
the wetting angle when subsequently attaching solder balls to the
layer of solder on the copper pillars 210.
[0052] Next, with reference to FIG. 4C, coating material is applied
320 in fluid form on the semiconductor wafer 205 to form a layer of
coating 410 which has an upper surface which is lower relative to
the height of the copper pillars 210. Consequently, the copper
pillars 210 with the layer of gold 405 protrudes away from the
layer of coating material 410. Ideally, the layer of coating
material 410 is lower by 20-30 um. The layer of coating material
410 is formed using an extrusion process. This is accomplished with
equipment such as MicroE from FAS Technologies of Dallas, Tex.,
USA. The coating material used can also comprise APS epoxy Wafer
Coating Underfill (WCU), Dexter's underfill epoxy or any photo
imageable coating material. With the MicroE extrusion coating
equipment and the APS WCU epoxy, the equipment settings include POH
rate 115 micro-liters (ul) per second, shuttle velocity 2.5
millimeter (mm), coating gap 125 um, and extrusion head shim of 0.2
mm.
[0053] With the extrusion coating process 80-90% of the coating
material that is dispensed forms the layer of coating 410, and a
single dispense can produce the layer of coating 410 with the
required thickness. In addition, the extrusion coating process can
dispense the coating material having a desired thickness to a
tolerance of 2%. Extrusion coating is typically employed in the
production of flat panel displays.
[0054] Hence, the present invention as described, advantageously
forms a layer of coating material on a semiconductor wafer more
quickly and with less wastage than the spin coating process, and
with the required thickness with a single application.
[0055] The layer of coating 410 can also be formed using known spin
coating processes, however, the spin coating process must be
controlled to produce the layer of coating 410 having a
predetermined thickness. For example, the quantity of coating
material that is disposed on the semiconductor wafer 205, the type
of coating material used, and the speed and duration at which the
semiconductor wafer 205 is spun, can be selected to produce the
layer of coating material 410 having the desired thickness. An
example is a Spin Coater machine by SITE of the USA, which applies
a coating of BCB or polyimide or epoxy based coating material. The
setting for the spin coating machine includes first coating speed
of 1500 revolutions per minute (rpm) for a period of 30 seconds;
and second coating speed of 1800 rpm for 20 seconds, to coat 30-40
um layer of coating material.
[0056] Another method forming the layer of coating 410 is using a
molding process in conjunction with a Teflon.RTM. film, similar to
that taught in U.S. Pat. No. 5,891,384 assigned to Apic Yamada
Corporation of Japan, which is incorporated by reference.
[0057] After applying the layer of coating material 410, the
semiconductor wafer is then heated to cure the layer of coating
410. The heat is applied at a temperature of 350.degree. C. for 45
to 60 minutes in a nitrogen (N2) environment. Typically, an oven
with a controlled nitrogen chamber is used for curing.
[0058] FIG. 5 shows an enlarged sectional view of one of the copper
pillars 210 with the layer of gold 405, after the layer of coating
410 has been formed. Portions 505 of the cured layer of coating
material 410 adhere to the upper surface 510 of the gold layer 405,
and portions 515 of the cured coating material 410 adhere to side
surfaces 520 of the copper pillars 210.
[0059] Subsequently, etchant is applied to the coated surface of
the semiconductor wafer 205 to etch 330 away the portions 505 and
515 of the cured layer of coating material 410 on the gold layers
405 and on the side surfaces 505 of the copper pillars 210. FIG. 4D
shows the semiconductor wafer 205 after etching, and FIG. 6 shows
an enlarged side sectional view of one of the copper pillars 210
with the layer of gold, with the portions 505 and 515 of the cured
layer of coating material 410 on the gold layers 405 and on the
side surfaces 505 of the copper pillars 210, are etched away.
[0060] When plasma etching is employed the plasma etchant comprises
a gas composition of 5% CF.sub.4 90% O.sub.2, 5% Ar, with a power
setting of 400 watts for a duration of 15 minutes. Alternatively,
deflashing equipment such as laser deflashers or media deflashers,
that are typically used for leadframe and mold deflashing, may be
adapted and used to remove the portions 505 and 515 of the cured
layer of coating material 410 on the gold layers 405 and on the
side surfaces 505 of the copper pillars 210. An example of a media
deflasher is that manufactured by Fujiseiki of Japan.
[0061] The present invention advantageously forms a layer of
coating material having relatively smaller portions that need to be
removed, thus allowing etching to be used and avoiding the need for
mechanical grinding.
[0062] With reference to FIG. 4E, after etching 330, solder balls
attached to the copper pillars 210, and the semiconductor wafer 205
is reflowed 345. The process 300 then ends 355.
[0063] FIG. 7 shows an enlarged sectional view of one of the solder
balls 415 attached to the copper pillars 210 after reflow. The
copper pillar 210 with the layer of gold 405 protrudes into the
solder ball 415, and the solder adheres to the surface 510 of the
layer of gold 405. In addition, the solder adheres to the side
surfaces 520 of the copper pillar 210.
[0064] The present invention, as described, advantageously allows
solder to adhere to the layer of gold and the side surfaces of the
copper pillar resulting in a stronger mechanical joint and a more
reliable electrical connection.
[0065] With reference to FIG. 8 an additional cleaning step can be
used prior to etching 330 to enhance the efficiency of the etching
process. After applying 320 the coating material 410 on the
semiconductor wafer 205, but prior to curing the coating material
410, Teflon.RTM. film 805 is placed over the semiconductor wafer
210, and pressure applied to force the Teflon.RTM. film against the
semiconductor wafer 210. The Teflon.RTM. film 805 is then removed,
taking with it the uncured portions 505 of the coating material on
the upper surfaces 510 of the layer of gold 405. Subsequently, this
leaves less of the cured portions 505 and 515 of the coating
material that need to be removed by the etching process 330.
[0066] Teflon.RTM. film is also known as release film, which is
more commonly used in molding. When the layer of coating is formed
by a molding process in conjunction with release film, the release
film prevents the mold compound from getting on the surface 510 of
the layer of gold 405 and also on the side surfaces 520 of the
copper pillar 210, during the molding process. Examples of release
film that can be used to add cleaning uncured portions of coating
material is release film by 3M of the USA. The release film can be
applied manually.
[0067] Alternatively, laser cleaning can be employed to clean away
the uncured portions of coating material on the layer of gold 405.
Laser cleaning is known to one skilled in the art, and an example
of laser cleaning equipment that may be utilized is that
manufactured by Advanced Systems Automation Limited (ASA) of
Singapore.
[0068] As is known, the precision of an etching process is
dependent on a variety of process parameters that include: the
particular etching process employed; the etchant used; the coating
material to be etched; the amount of coating material to be etched;
etc. When etching a layer of coating material having a thickness of
10 microns, an etching process having a precision of much less than
10 microns is required. A figure of merit is defined as
follows:
(Target thickness of layer to be etched)/(Precision of etching
process) which for a reliable result must be >>1.
[0069] For example, with a target thickness of 10 microns and where
an etching process having a precision of 5 microns is employed, the
figure of merit yields 2. In contrast, when an alternative etching
process having a precision of 2 microns is employed, the figure of
merit is 5. Clearly the latter etching process is more
desirable.
[0070] When an etching process having a precision of 50 microns is
employed, with the target thickness of 10 microns, the figure of
merit is <<1. Here, there is the risk of the etchant
completely removing the layer of coating material from the surface
of the semiconductor die 205. Hence, when an etching process having
a precision of 50 microns is employed, an alternate embodiment of
the present invention, as will be described below can be used.
[0071] In accordance with the alternate embodiment, a layer of gold
is disposed on upper surfaces of copper pillars on a wafer, and
solder balls attached to the layer of gold on the copper pillars,
and the assembly reflowed. Coating material is then applied on the
wafer with an extrusion process until the solder balls are
submerged in coating material. After the coating material is cured,
etchant is then disposed to remove a portion of the layer of
coating material, such that the solder balls are substantially
exposed. Due to the large amount of coating material that needs to
be removed by etching, an etching process with reduced precision
can advantageously be employed. For example, with a solder ball
diameter of 300 microns, the target thickness is set to 250
microns, and with an etching process having a reduced precision of
50 microns, the figure of merit >>1. Thus, an etching process
having a reduced precision can advantageously be employed, without
adversely affecting the reliability of the resultant WL-CSP.
[0072] With reference to FIG. 9 and FIGS. 10A-D, a process 900, in
accordance with the alternate embodiment of the present invention,
starts 905 with providing 910 a semiconductor wafer 205 with copper
pillars 210 extending from die pads 212 on the semiconductor wafer
205, as shown in FIG. 10A. References were provided earlier as to
the formation of the pillars on the semiconductor wafer 205, and
the same references apply here. Solder balls 1005, are then
disposed 915 on the free ends of the copper pillars 210, and after
a reflow process 920, the solder balls 1005 adhere to the copper
pillars 210, as shown in FIG. 10B.
[0073] For proper adhesion and reliable coupling between the solder
balls 1005 and the copper pillars 210, as is known, it is important
that the surface of the copper pillars 210 do not have a layer of
oxide thereon, prior to attaching the solder balls 1005 thereto. As
copper tends to oxidize relatively quickly when exposed to ambient
air, one method of providing a suitable surface for the solder is
to dispose a layer of gold on the upper surface 225 of the copper
pillars 210 prior to attaching the solder balls 1005. The layer of
gold is often referred to as gold flash, and can be formed using
deposition, as will be known to one skilled in the art. As gold is
not as prone to oxidation as copper, the layer of gold provides an
oxide free surface for the solder balls to adhere to.
[0074] Alternatively, a layer of solder can be formed on the upper
surface 225 of the copper pillars 210 prior to attaching the solder
balls 1005. In addition, the layer of solder provides a surface for
solder balls to adhere to, and advantageously enhances the wetting
angle when subsequently attaching solder balls to the layer of
solder on the copper pillars 210.
[0075] Next, with reference to FIG. 10C, coating material is
applied 925 in fluid form on the semiconductor wafer 205 to form a
layer of coating 1010 having a predetermined thickness, such that
the solder balls 1005 are submerged in the layer of coating
material 1010. The layer of coating material 1010 is applied using
an extrusion coating process followed by curing. This can be
accomplished with equipment such as MicroE from FAS Technologies of
Dallas, Tex., USA. The coating material used is APS epoxy Wafer
Coating Underfill (WCU), Dexter's underfill epoxy or any photo
imageable coating material. With the MicroE extrusion coating
equipment and the APS WCU epoxy, the equipment settings include POH
rate 115 micro-liters (ul) per second, shuttle velocity 2.5
millimeter (mm), coating gap 125 um, and extrusion head shim of 0.2
mm.
[0076] With the extrusion coating process 80-90% of the coating
material that is dispensed forms the layer of coating 1010, and a
single dispense can produce the layer of coating 410 with the
required thickness. In addition, the extrusion coating process can
dispense the coating material having a desired thickness to a
tolerance of 2%.
[0077] Subsequently, after the layer of coating material 1010 is
cured, etchant is applied to the coated surface of the
semiconductor wafer 205 to etch 930 away a portion of the cured
layer of coating material 1010, to produce the etched semiconductor
wafer 205, as shown in FIG. 10D. With reference to FIG. 11 for
example, when the copper pillar 210 has a diameter of 250 microns,
and the solder ball 1005 a diameter of 300 microns, then the target
thickness for the etching process is set to 250 microns, when the
etching process has a precision of 50 microns. Hence the thickness
of the coating material 1010 that will be removed by etching will
be between 200 and 300 microns. This means that the solder balls
1005 will either be completely exposed or partially exposed, but a
sufficient portion of the solder ball 1005 is exposed to allow the
solder ball 1005 to subsequently mount the WL-CSP, reliably.
[0078] With reference to FIG. 12, height of the copper pillar 210
is a predetermined distance 1205 as measured from the surface 207
of the semiconductor die 205 to the top of the copper pillar 210.
The thickness of the layer of coating material is another
predetermined distance 1210, as measured from the surface 207 of
the semiconductor die 205 to the top of the layer of coating
material 1010. The thickness of the resultant layer of coating
material 1010 after etching is a distance 1215, that is greater
than the height of the copper pillar 210, as represented by the
distance 1205, but less than the thickness of the layer of coating
material, prior to etching, as represented by the distance 1210, as
measured from the surface 207 of the semiconductor die 205.
[0079] When plasma etching is employed the plasma etchant comprises
a gas composition of 5% CF.sub.4, 90% O.sub.2, 5% Ar, with a power
setting of 400 watts for a duration of 15 minutes. After etching
930 the process 900 ends 935. The etching process may cause a layer
of oxide to form on the surface of the solder balls 1005. A
subsequent reflow step can then be performed to melt the solder
balls 1005, to cause an oxide free surface to reform on the solder
balls 1005.
[0080] Alternatively, deflashing equipment such as laser deflashers
of media deflashers, that are typically used for leadframe and mold
deflashing may be adapted and used to remove the portion of the
cured layer of coating material 1010, to produce the etched
semiconductor wafer 205, as shown in FIG. 10D. An example of a
media deflasher is that manufactured by Fujiseiki of Japan.
[0081] Hence, the present invention, as described, advantageously
forms a layer of coating material on a semiconductor wafer more
quickly and with less wastage than the spin coating process, and
with the required thickness using a single application. An
additional advantage of the alternate embodiment of the present
invention, as described, is that the joint between the solder ball
and copper pillar is formed prior to application of the coating
material. Consequently, contamination of the surfaces of the copper
pillars, with or without a layer of gold, by the coating material
is avoided.
[0082] A further advantage of the alternate embodiment is that the
subsequent application of the coating material, after the joints
between the solder balls and the copper pillars is formed, seals
the joints within the layer of coating material, thereby improving
the reliability of the WL-CSP.
[0083] The layer of coating 1010 can also be applied using known
spin coating processes, however, the spin coating process must be
controlled to produce the layer of coating 1010 having the
predetermined thickness. For example, as mentioned before, the
quantity of coating material that is disposed on the semiconductor
wafer 205, the type of coating material used, and the speed and
duration at which the semiconductor wafer 205 is spun, can be
selected to produce the layer of coating material 1010 having the
desired thickness. Another method for forming the layer of coating
1010 is by using a molding process in conjunction with a
Teflon.RTM. film, similar to that taught in U.S. Pat. No. 5,891,384
assigned to Apic Yamada Corporation of Japan.
[0084] After applying the layer of coating material 1010, the
semiconductor wafer 205 is heated to cure the layer of coating
1010. The heat is applied at a temperature of 350.degree. C. for 45
to 60 minutes in a nitrogen (N2) environment. Typically, an oven
with a controlled nitrogen chamber is used for curing.
[0085] Hence, the present invention, as described, produces a
WL-CSP without subjecting the semiconductor wafer to mechanical
grinding. In addition, the joint between the solder balls and the
copper pillars is more reliable.
[0086] This is accomplished by forming an etch resistant conductive
layer on pillar bumps on a semiconductor wafer, disposing a layer
of coating material on the wafer with the bumps extending through
and protruding from the surface of the layer of coating material.
Subsequently, portions of the coating material on the top and the
sides of the bumps are etched away, and solder balls attached to
the exposed portion of the bumps.
[0087] In an alternate embodiment, the solder balls are attached to
pillar bumps on a semiconductor wafer, and the bumps and the solder
balls are encapsulated in a layer of coating material.
Subsequently, a portion of the layer of coating material is etched
away to substantially expose the solder balls.
[0088] Therefore, the present invention provides a method for
forming a wafer level chip scale package and package formed
thereby, which overcomes or at least reduces the above mentioned
problems of the prior art.
[0089] Although the invention has been described and illustrated
with reference to specific illustrative embodiments thereof, it is
not intended that the invention be limited to those illustrative
embodiments. Those skilled in the art will recognize that
variations and modifications can be made without departing from the
spirit of the invention It is therefore intended to include within
the invention all such variations and modifications which fall
within the scope of the appended claims and equivalents thereof
* * * * *