U.S. patent application number 10/831192 was filed with the patent office on 2004-10-07 for low voltage high performance semiconductor devices and methods.
Invention is credited to Tran, Luan C..
Application Number | 20040198004 10/831192 |
Document ID | / |
Family ID | 22456106 |
Filed Date | 2004-10-07 |
United States Patent
Application |
20040198004 |
Kind Code |
A1 |
Tran, Luan C. |
October 7, 2004 |
Low voltage high performance semiconductor devices and methods
Abstract
A method for adjusting V.sub.t while minimizing parasitic
capacitance for low voltage high speed semiconductor devices. The
method uses shadow effects and an angled punch through prevention
implant between vertical structures to provide a graded implant.
The implant angle is greater than or equal to arc tangent of S/H
where S is the horizontal distance between, and H is the height of,
such vertical structures.
Inventors: |
Tran, Luan C.; (Meridian,
ID) |
Correspondence
Address: |
DICKSTEIN SHAPIRO MORIN & OSHINSKY LLP
2101 L STREET NW
WASHINGTON
DC
20037-1526
US
|
Family ID: |
22456106 |
Appl. No.: |
10/831192 |
Filed: |
April 26, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10831192 |
Apr 26, 2004 |
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10302965 |
Nov 25, 2002 |
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6747326 |
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10302965 |
Nov 25, 2002 |
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09903623 |
Jul 13, 2001 |
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6492693 |
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09903623 |
Jul 13, 2001 |
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09132904 |
Aug 12, 1998 |
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6312997 |
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Current U.S.
Class: |
438/289 ;
257/E21.345; 257/E21.443; 257/E21.633; 257/E27.064; 257/E29.063;
438/279; 438/291 |
Current CPC
Class: |
H01L 29/1083 20130101;
H01L 27/0922 20130101; H01L 29/66537 20130101; H01L 21/823807
20130101; H01L 21/26586 20130101 |
Class at
Publication: |
438/289 ;
438/291; 438/279 |
International
Class: |
H01L 021/8238 |
Claims
1-49. (Cancelled)
50. A method of manufacturing a semiconductor device of a first
conductivity type fabricated on a semiconductor substrate, the
method comprising: providing a semiconductor substrate; isolating
an active region on the semiconductor substrate; forming a first
structure on the active region, said first structure comprising a
gate; forming a second structure on the semiconductor substrate,
said second structure having a height (H) and being formed at a
distance (S) from said first structure; implanting a dopant of said
first conductivity type into the active region to form a
source/drain region of said first conductivity type in said
substrate between said first and second structures; implanting a
dopant of a second conductivity type through said source/drain
region, wherein said dopant of second conductivity type is
implanted at an angle with respect to the surface said substrate
such that the amount of dopant of second conductivity type
implanted increases approaching said gate structure and said second
structure from a point in the active region about one-half the
distance (S) between said first structure and said second
structure.
51. The method according to claim 50, wherein the height (H) of
said second structure is sufficiently high so as to cause a shadow
effect upon the angled implantation of said dopant of second
conductivity type.
52. The method according to claim 50, wherein the dopant of second
conductivity type is implanted at an angle such that the
relationship between the height (H) of the second structure and the
distance (S) between the second structure and the first structure
blocks direct implant of the dopant of second conductivity type
into at least a central portion of the source/drain region.
53. The method according to claim 50, wherein the first structure
has a height which is substantially the same as the height (H) of
the second structure.
54. The method according to claim 50, wherein the angle of
implantation is such that said first and second structures block
implantation of the dopant of second conductivity type into at
least a central portion of the source/drain region.
55. The method according to claim 50, wherein the angle of
implantation is at least about Arctangent S/H.
56. The method according to claim 50, wherein the dopant of second
conductivity type is implanted at an angle of from 5.degree. to
45.degree. with respect to said substrate.
57. The method according to claim 50, further including implanting
the dopant of a second conductivity type with an implant energy of
about 10 keV to 100 keV.
58. The method according to claim 50, further including implanting
the dopant of a second conductivity with an implant dose of about
2.times.10.sup.11 atoms/cm.sup.2 to 8.times.10.sup.13
atoms/cm.sup.2.
59. The method according to claim 50, wherein forming the second
structure includes providing a dummy gate structure.
60. The method according to claim 50, wherein said semiconductor
device is a CMOS transistor.
61. The method according to claim 50, wherein said implanting of
said dopant of said second conductivity type lowers the threshold
voltage and parasitic junction capacitance of said transistor.
62. A method of manufacturing a semiconductor device of a first
conductivity type fabricated on a semiconductor substrate, the
method comprising: providing a semiconductor substrate; isolating
an active region on the semiconductor substrate; forming a gate
structure on the active region; forming a dummy gate on the
semiconductor substrate at a location spaced from said gate
structure; implanting a dopant of said first conductivity type into
the active region to form a source/drain region of said first
conductivity type in said substrate, said source/drain region being
adjacent to said gate structure; implanting a dopant of a second
conductivity type through said source/drain region, wherein said
dopant of second conductivity type is implanted at an angle with
respect to the surface said substrate such that the amount of
dopant of second conductivity type implanted increases approaching
said gate structure from a central portion of said source/drain
region.
Description
FIELD OF THE INVENTION
[0001] This invention relates to low voltage, high performance
semiconductor devices, such as MOS transistors for dynamic random
access memory (DRAM) cells and logic applications, and to methods
for fabricating such devices. More specifically, the present
invention relates to methods for adjusting threshold voltage for
high speed semiconductor transistor devices without the need for
any additional masks.
BACKGROUND OF THE INVENTION
[0002] MOS processes typically begin with a lightly-doped P-type or
N-type silicon substrate. For the sake of simplicity, the
conventional MOS process will be described using P-type silicon as
the starting material. If N-type silicon were used, the process
steps would be virtually identical, with the exception that the
dopant types would be reversed.
[0003] Silicon, the most commonly used semiconductor material can
be made conductive by doping (introducing an impurity into the
silicon crystal structure) with either an element such as boron,
which has one less valence electron than silicon, or with elements
such as phosphorus or arsenic, which have one more valence electron
than silicon.
[0004] In the case of boron doping, electron "holes" become the
charge carriers and the doped silicon is referred to as positive or
P-type silicon. In the case of phosphorus or arsenic doping, the
additional electrons become the charge carriers and the doped
silicon is referred to as negative or N-type silicon. If dopants of
opposite type conductivity are used, counter-doping will result,
and the conductivity type of the most abundant impurity will
prevail.
[0005] The P-well regions are oxidized using a conventional LOCOS
(LOCal Oxidation of Silicon) step to create a silicon oxide layer.
During the LOCOS process, the pad oxide serves as a stress relief
layer. Alternatively, oxide growth and oxide deposition steps over
silicon trench can replace the LOCOS step.
[0006] The channel regions of the future N-channel transistors are
then exposed to a high-energy boron punch-through implant. This
implant increases both source-to-drain breakdown voltage and the
threshold voltage (V.sub.t), thus avoiding short-channel effects.
The successful operation of MOS circuits is very dependent on the
ability to control threshold voltage (V.sub.t). The threshold
voltage (V.sub.t) of a transistor is the voltage necessary for
turning the transistor on or off. Accurate control of V.sub.t is
made possible by ion implantation. V.sub.t adjustment implantation
into the channel usually takes place through a sacrificial gate
oxide, before the growth of a gate oxide and deposition of the
polysilicon for the gate electrodes.
[0007] In conventional MOS processes, after V.sub.t adjustment a
layer of polysilicon is then deposited on top of the gate oxide
using conventional means (e.g., chemical vapor deposition). The
poly layer is then doped with phosphorus, and coated with a layer
of tungsten silicide by various possible techniques (e.g., chemical
vapor deposition, sputtering, or evaporation). A further photomask
then patterns the silicide-coated polysilicon layer to form the
transistor gates.
[0008] The N-channel source and drain regions are next exposed to a
relatively low-dosage phosphorus implant which creates
lightly-doped drain (LDD) N-regions. Following the stripping of
this mask, a layer of silicon dioxide or nitride is deposited on
the wafer. An anisotropic etch and a subsequent optional isotropic
etch of the silicon dioxide layer leave oxide spacers on the sides
of each transistor gate.
[0009] A photomask then exposes the source and drain regions to a
relatively high-dosage phosphorus or arsenic implant, which creates
heavily-doped N+ regions. A photomask is then used to define
contacts which will pass through an isolation oxide, e.g., BPSG
glass, layer to the poly structures or active area conductive
regions below. A deposition of an aluminum metal layer follows.
Another photomask is then used to pattern the aluminum layer for
circuit interconnects. Using a blanket deposition process, the
circuitry is then covered with one or more passivation layers. An
additional photomask then defines bonding pad openings, which will
expose bonding pad regions on the aluminum layer below. This
completes a conventional MOS process.
[0010] The business of producing semiconductor devices is a very
competitive, high-volume business. Process efficiency and
manufacturability, as well as product quality, reliability, and
performance (speed) are key factors that determine success or
failure. Each new generation of devices is expected to be faster
and more compact than the generation it replaces.
[0011] In low voltage design, low threshold voltage (V.sub.t) is
essential since the current drive is proportional to
(V.sub.G-V.sub.t) where V.sub.G is the gate voltage. Because very
precise quantities of impurity can be introduced using ion
implantation, it is possible to maintain close control of V.sub.t.
A problem arises, however, in connection with ion implantation for
punch through prevention in such devices. Implanting a boron
dopant, for example, for punch through prevention increases
V.sub.t, and creates a barrier layer at the junction between the N+
type source and drain regions and the underlying P-type substrate,
thus increasing parasitic capacitance at this junction. This
parasitic capacitance reduces the speed of the device.
[0012] A method is needed for adjusting V.sub.t, while minimizing
parasitic capacitance and without introducing any additional
photomasking steps.
SUMMARY OF THE INVENTION
[0013] The invention provides a low voltage, high speed
semiconductor transistor device having low V.sub.t and reduced
parasitic capacitance. Reduction in parasitic capacitance, and
hence increase in speed, is achieved by shadowing out an angled
punch through prevention ion implant between a transistor gate and
adjacent structures to shadow out a portion of the implant. The
resulting, minimally diffused implant results in a relatively
lighter dose toward the edge of the transistor gate than the
central regions of the source and drain, thus reducing V.sub.t and
parasitic junction capacitance in those, regions. The low V.sub.t
and reduced parasitic capacitance devices may be produced together
with higher V.sub.t devices elsewhere on the chip without any
additional masking steps to make the low V.sub.t devices.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a sectional view of a semiconductor wafer fragment
at one processing step in accordance with the invention.
[0015] FIG. 2 is a view of the FIG. 1 wafer taken at a step
subsequent to that shown by FIG. 1. FIG. 2 shows the formation of
actual gate, and dummy gate (or poly runners over field oxide),
structures at a predetermined height (H) and spacing (S). FIG. 2
also shows formation of a lightly doped drain LDD between such
structures.
[0016] FIG. 3 is a view of the FIG. 1 wafer taken at a step
subsequent to that shown by FIG. 2, and shows self-aligned
formation of source and drain regions.
[0017] FIG. 4 is a view of the FIG. 1 wafer taken at a step
subsequent to that shown by FIG. 3, and shows spacering of actual
gate, and dummy gates (or poly runners over field oxide), and
angled implant for punch through prevention. FIG. 4 also shows a
gradation in the P-N junction region of the active area as a result
of the shadow effects caused by the angled implant and the
structures at distances H and S.
[0018] FIG. 5 is a view of the FIG. 1 wafer taken at a step
subsequent to that shown by FIG. 4, and shows one method of contact
formation to source and drain regions.
[0019] FIG. 6 is a view of the FIG. 1 wafer taken at a step
subsequent to that shown by FIG. 4, and shows an alternative method
of contact formation to source and drain regions.
[0020] FIG. 7 is an alternative embodiment showing a view of the
FIG. 1 wafer taken at a step subsequent to FIG. 1, and shows
formation of a lightly doped drain and angled implant for punch
through prevention, both prior to spacering of actual gate and
dummy gates (or poly runners).
[0021] FIG. 8 depicts examples of various circuits containing both
low V.sub.t devices and high or normal V.sub.t devices according to
the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0022] The figures are not meant to be actual cross-sectional views
of any particular portion of a real semiconductor device, but are
merely convenient tools employed to more fully depict the process
aspect of the invention at various stages of manufacture.
[0023] The term "substrate" herein shall be understood to mean one
or more semiconductive layers or structures which include active or
operable portions of semiconductor devices.
[0024] An exemplary construction of a fabrication process for a low
voltage semiconductor transistor device according to one embodiment
of the present invention is described below. It is to be
understood, however, that this process is only one example of many
possible processes. For example, the angled V.sub.t adjustment
implant is shadowed out by a transistor gate and a dummy gate in
the following process. A series of actual gates, interconnect
structures and actual, or dummy, gates, poly runners or other
structures could also be used. As another example, additional
implant steps may be employed to optimize impurity profiles in
particular regions, and the sequence of implant steps could be
changed so long as the punch through prevention implant is carried
out after one or more structures are deposited and subsequently
patterned with sufficient height and sufficiently small spacing to
shadow out the angled implant.
[0025] Referring to FIG. 1, a first pad oxide layer 11 is grown on
lightly-doped P-type silicon substrate 12. Silicon substrate 12 is
isolated into active region 10 by field oxide regions 13. LOCal
Oxidation of Silicon (LOCOS), shallow trench isolation (STI) or
other field isolation techniques known in the art are used to
provide oxide regions 13 for patterning silicon substrate 12 into
active region 10. As an example of an STI process, a silicon
nitride layer (not shown) can be deposited on a silicon dioxide
layer which is previously thermally grown on silicon substrate 12.
The silicon nitride layer is patterned such that the silicon
nitride layer remains only on active region 10. A silicon trench is
then etched to a depth of typically 2-3 times the junction depth of
the devices, i.e., about 0.20 to 0.40 micron. The silicon sidewalls
and trench bottom are then oxidized to a thickness of about 100-200
angstroms to serve as a liner. Then a high conformal oxide
deposition is performed to fill both the trench and the wide open
field area. The oxide is subsequently planarized by chemical
mechanical polishing (CMP) to the level of the nitride underneath,
to expose the nitride. The STI process is preferred in the method
of the present invention due to the greater degree of flatness or
planarity which it provides.
[0026] Referring to FIG. 2, after isolation of active region 10,
gate structure 18 which includes polycrystalline silicon 14, an
overlying silicide layer 15 such as tungsten silicide or other
highly conductive materials, and an insulating cap 16, preferably
SiO.sub.2 or Si.sub.3N.sub.4, are formed using conventional
semiconductor gate processing techniques. In FIG. 2 gate structure
18 is the actual transistor gate above active region 10. Gate
structures 26 above field oxide regions 13 are dummy gates or poly
runners. Dummy gates 26 are preferably formed at the same time and
using the same steps as used for formation of gate structure 18.
The height (H) of deposited polycrystalline silicon 14, silicide 15
and cap 16 (with optional spacer material) is the desired final
height of gate structure 18 and dummy gate structures 26 for the
semiconductor device. This height (H) is preferably greater than
conventional gate structures so as to facilitate the shadow effects
of the angled implant to adjust V.sub.t in subsequent steps.
Patterned photoresist is used as an etch mask in forming gate
structure 18 and dummy gates 26. In FIG. 2, the patterned
photoresist has been removed.
[0027] Referring still to FIG. 2, after formation of gate structure
18, a conventional self-aligning lightly doped (LDD) implant 20 is
performed to form lightly doped regions 17 as shown. For N-channel
semiconductor devices, the LDD implant 20 is an N-type dopant. For
a P-channel device, the LDD implant is a P-type dopant.
[0028] The implant energy of the LDD implant 20 is sufficient to
penetrate the exposed portion of active region 10 but not
sufficient to penetrate active region 10 under gate structure 18.
Thus, gate structure 18 serves as an implant mask to block the LDD
implant 20. In LDD region 17, the implant energy of the LDD implant
20 controls the peak concentration depth. Lightly doped drain
region 17 reduces the electric field of the semiconductor device by
grading the doping level of active region 10. This doping level
gradation is discussed below in connection with FIG. 4.
[0029] Although not shown in FIG. 2, a patterned photoresist may
optionally be used to prevent self-aligning LDD implant 20 from
penetrating other active regions which do not require the implant.
The photoresist covered active regions include those used for
semiconductor devices with a channel of a different conductivity
type compared to that of the semiconductor device of gate structure
18 or to block certain species from being implanted into the memory
array. The patterned photoresist is removed after performing LDD
implant 20.
[0030] Referring to FIG. 3, LDD implant 20 is followed by a
chemical vapor deposition (CVD) of oxide or nitride to create a
spacer oxide layer 19 having a thickness in the range of 200 to
2000 angstroms, depending upon device geometry. Spacer oxide layer
19 is then etched with an anisotropic etch, to form a set of
sidewall spacers 19 for transistor gates 18. Spacer oxide layer 19
coats the sides of transistor gate 18, so that when the wafer is
subsequently subjected to an N-type implant, N-type source/drain
regions are created for N-channel devices, and these N-type
source/drain regions are offset from the vertical boundaries of LDD
implant regions 17 by the vertical segments of spacer oxide layer
19 on the edge of the N-channel transistor gates 18.
[0031] Referring still to FIG. 3, a high-dosage arsenic or
phosphorus implant then creates self-aligned heavily doped N-type
source/drain regions 23 for N-channel devices. The high-dosage
implant is self-aligned to the edges of the N-channel transistor
gate 18.
[0032] FIG. 3 depicts self-aligning implant 22 performed after
formation of gate structure 18 and oxide spacer 19. The
self-alignment of implant 22 is particularly preferred for small
geometry devices. Implant 22 introduces dopant into active region
10 to overlap LDD region 17 to form source and drain regions 23. To
form semiconductor devices with an N-channel, dopant 22 is a dopant
having an N-type conductivity such as phosphorous, arsenic, or the
like. Dopant 22 is, of course, of a different conductivity type
than that of the substrate to form a semiconductor device with a
channel of the different conductivity type.
[0033] The implant energy of dopant 22 during implant 22 is
sufficient to penetrate active region 10 in source and drain region
23, i.e., the implant energy is preferably low to form shallow
junctions. Gate structure 18 serves as an implant mask to block
implant 22. In source and drain region 23, the implant energy of
dopant 22 controls the depth of the peak concentration of implant
22. An additional implant can be used to optimize the dopant
profile of source and drain region 23.
[0034] As depicted in FIG. 3, a portion of source and drain region
23 will exist underneath a portion of spacer 19, in that a portion
of LDD region 17 exists underneath a portion of gate structure 18
since the LDD implant is performed prior to the formation of spacer
19. Thus, a portion of LDD region 17 is converted into source and
drain region 23 by implant 22. LDD region 17 and source and drain
region 23 are of the same conductivity type. As shown in FIG. 3,
spacer 19 is used to block implant 22 from completely overlapping
LDD region 17. Since the dose of implant 22 is higher than the dose
of the LDD implant, the doping concentration of source and drain
region 23 is higher than the doping concentration of LDD region 17,
and the doping concentration of LDD region 17 does not
significantly affect the doping concentration of source and drain
region 23. Source and drain region 23 has a higher N-type doping
concentration, and LDD region 17 has a lower N-type doping
concentration. A portion of the original LDD region exists to
provide a graded doping concentration to reduce the electric field
in active region 10 to increase the breakdown voltage of the
semiconductor device.
[0035] Referring to FIG. 4, after formation of source and drain
regions 23, the wafer is subjected to angled low-dosage boron
implant 21, using a mask which is usually the same mask as the N+
source/drain mask, to serve as an N-channel punch through voltage
enhancement, creating punch through implant regions 24 that extend
to the edges of transistor gate 18 and dummy gate 26. Punch through
prevention implant 21 introduces dopant into active region 10, and
may increase V.sub.t of small devices by as much as several hundred
mVs. To form a semiconductor device with an N-channel, the
implanted dopant 21 is a dopant having a P-type conductivity such
as boron. Dopant 21 is of a different conductivity type to prevent
punch through in a channel of the different conductivity type. A
P-type dopant is implanted into an N-channel device to prevent
punch through. Similarly, an N-type dopant, such as phosphorous,
can be implanted into an N-channel device to adjust the threshold
voltage in a negative direction.
[0036] In conventional silicon processing, the threshold voltage
adjustment implant is performed prior to formation of gate
structure 18 and spacer 19. In the process of the present
invention, the gate structure serves as a mask for the angled
implant 21, and the implant 22 (FIG. 3) which creates the source
and drain regions.
[0037] Although implant 21 is a different conductivity type than
implant 22, the implant dose of implant 22 is approximately 3
orders of magnitude higher than the implant dose of implant 21.
Therefore, although P-type punch through prevention implant 21 is
implanted into N-type source and drain region 23, the lower
concentration of P-type dopant 21 does not significantly affect the
higher concentration of N-type dopant 22. A similar effect is
observed if implant 21 uses an N-type dopant.
[0038] Implant 21 is performed at a boron implant dose of
approximately 2.times.10.sup.11 to 8.times.10.sup.13 atoms/cm.sup.2
and an implant energy of approximately 10 to 100 keV, preferably
about 40 to 60 keV.
[0039] Punch through prevention implants typically create a higher
concentration P-type region below the N-type source and drain
regions than created in the channel region under gate structures,
and thus increase source and drain junction capacitances. This
increase in P-N junction capacitance degrades speed and power
performance. In order to overcome this problem, the method of the
present invention uses an angled implant 21 in which the relatively
tall (H) gate structures partially shadow out implant 21. When the
implant angle .phi. is between 5.degree. and 45.degree. as shown in
FIG. 4, and the gate or other structures are sufficiently high so
that the implant angle is preferably slightly greater than Arc
tangent S/H, where S is the horizontal distance between gate
structure 18 and dummy gates 26 (or other structures), only a thin
layer of boron is created in region 24 below the source and drain
regions. However, a somewhat higher dose of boron is implanted in
outer regions 25 of the source and drain. Only about one-half of
the usual dose is implanted in the central region 24 of the source
and drain because, due to four rotational implants (one for each
90.degree. rotation of the substrate), only two directions are
implanted. Due to the four rotational implants, and depending upon
the angle .phi. and distances (H) and (S), three directions can be
implanted into outer regions 25. As a result of the angled implant
21 and shadow effects, the V.sub.t is about 200-300 mv lower than
would be achieved without the shadow effects and, more importantly,
the junction capacitance between the source to substrate and drain
to substrate is reduced, thus increasing device speed. Various
different angles, and distances (H) and (S) can be employed in the
method of the invention, so long as at least a portion of the
implant is shadowed out resulting in gradation of the implanted
dopant concentration.
[0040] Implants 21 and 22 are subsequently annealed to activate
implanted dopants 21 and 22, respectively. The high temperature
anneal or rapid thermal anneal is preferably of a short time
duration to prevent dopant diffusion associated with long diffusion
anneals and to eliminate problems associated with dopant
diffusion.
[0041] Referring now to FIG. 5, conventional processing technology
may be used to complete the circuitry. Preferably all structures
are first covered by an oxide isolation layer (not shown), which
may be doped with phosphorus, boron or both. In FIG. 5, a photomask
(not shown) has been used to define contacts 28 from metal layer 31
through oxide isolation layer through which connection to poly plug
structures 27 and active area conductive regions below can be made.
FIG. 5 shows buried digit line 29 as one preferred embodiment. For
example, referring to FIG. 6, an alternative embodiment is shown
which utilizes a self-aligned contact etch for tungsten metal
contacts 30. Various processing steps known in the art can be used
to complete the circuitry.
[0042] Additional variations of the present invention include
interchanging the processing order of source and drain implant 22
and punch through prevention implant 21. In addition, the implant
21 can be formed together with the LDD implant step before spacer
formation. FIG. 7 illustrates process steps in this alternative
embodiment. Furthermore, the semiconductor manufacturing process
embodied in the present invention to produce MOS semiconductor
transistor devices can also be used to produce MESFET, CMOS, and
BiCMOS devices.
[0043] One advantage of the present invention is that low V.sub.t
devices may be made on a chip containing normal or high V.sub.t
devices without the need for any additional masking step. The
invention thus lends itself well to various applications in which
low voltage devices are minority devices on a given chip. These
applications, include, for example, NMOS pass transistor devices
(FIG. 8A), pre-charge circuits (FIG. 8B) and output drivers (FIG.
8C). With reference to FIG. 8A, V.sub.TL represents a low threshold
voltage device, which preferably has a low V.sub.t so as to
maximize output level at VO, due to the V.sub.t drop. Voltage
V.sub.1 after a pass transistor is preferably high to have good
drive on the device M1. The smaller the V.sub.t, the lower the
drop. With reference to FIG. 8B, the node 1 voltage of the
pre-charge circuit V.sub.PR is preferably high so that it can
properly drive the subsequent driver. Accordingly, a V.sub.TL
device is provided between V.sub.PR and node 1. FIG. 8C shows
another circuit in which the output is a V.sub.t drop away from the
input voltage V.sub.CC. Given the disclosure and teachings of the
present invention, these and various other circuits can now be
conveniently made with both low V.sub.t and high V.sub.t devices
without additional or complex processing steps.
[0044] Although several embodiments of the improved process have
been described herein, it will be apparent to one skilled in the
art that changes and modifications may be made thereto without
departing from the spirit and the scope of the invention as
claimed. The same process flow could be used to create P-channel
and N-channel devices on a lightly-doped N-type substrate (arsenic
or phosphorus-doped silicon having a conductivity opposite to that
of the lightly-doped P-type substrate used to begin the process
described in detail heretofore). In such a case, a P-well, rather
than an N-well would be created in the substrate, and so forth.
Moreover, the process approach explained herein was in the context
of a single actual gate, but any structure may be utilized to
shadow out the punch through prevention implant. Preferably, such
structures are of sufficient height (H) and spacing (S) such that
the implant angle is greater than or equal to arc tangent S/H. The
structures may include, for example, an actual gate for one device
and an adjacent actual gate of another device, or an actual gate
for one device and an interconnect structure such as a poly runner
for that same or another device.
[0045] Accordingly, the above description and accompanying drawings
are only illustrative of preferred embodiments which can achieve
and provide the objects, features and advantages of the present
invention. It is not intended that the invention be limited to the
embodiments shown and described in detail herein. The invention is
only limited by the spirit and scope of the following claims.
* * * * *